CN113285610A - Circuit topology, control method and electronic equipment with topology - Google Patents

Circuit topology, control method and electronic equipment with topology Download PDF

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Publication number
CN113285610A
CN113285610A CN202110628171.9A CN202110628171A CN113285610A CN 113285610 A CN113285610 A CN 113285610A CN 202110628171 A CN202110628171 A CN 202110628171A CN 113285610 A CN113285610 A CN 113285610A
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switch
capacitor
direct current
bus
point
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CN202110628171.9A
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CN113285610B (en
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戴日增
周宜福
张宝
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Guangzhou Felicity Solar Technology Co ltd
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Guangzhou Felicity Solar Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Abstract

The invention discloses a circuit topology, a control method and electronic equipment with the topology. The circuit topology comprises two independent direct current conversion circuits arranged on a battery side, wherein each direct current conversion circuit is independently connected with a primary side of a transformer, a secondary side of each transformer is independently connected with a second-stage boosting/reducing circuit, and the two second-stage boosting/reducing circuits are respectively connected with a positive direct current bus and an auxiliary direct current bus. The invention can adjust the voltage balance of the double buses, improves the adaptability to unbalanced loads, and provides an effective solution for uninterruptible power supplies and inverter products with high requirements on high-voltage photovoltaic modules and load matching.

Description

Circuit topology, control method and electronic equipment with topology
Technical Field
The present invention relates to the field of power generation technologies or power supply technologies, and in particular, to a circuit topology, a control method, and an electronic device having the topology.
Background
Currently, known uninterruptible power supplies and inverters are primarily single bus architectures. With the development of photovoltaic modules, the system has higher and higher requirements on power generation efficiency, simplicity, convenience and the like for mounting the photovoltaic modules, and the design and application of high-voltage buses are more and more extensive. The direct current-to-alternating current side circuit topology in the prior art is mainly a three-level topology, and the topology has the midpoint connected to the midpoint of the double buses, so that the double-bus voltage balance problem can be caused. In grid-connected inverter products, the double-bus voltage can be controlled by a direct current to alternating current three-level circuit. However, in the application field of off-grid inverters, half-wave or positive and negative half-cycle unbalanced loads exist on a power supply side (load), the positive and negative half-cycle energy is inconsistent due to the type of the loads, and finally, double-bus voltage is unbalanced, so that the device is damaged or equipment cannot normally operate due to exceeding the specification of the device. For this reason, it is necessary to develop a new technology to solve the above technical problems.
Disclosure of Invention
The invention aims to provide a circuit topology and an off-grid inverter formed by the circuit topology to overcome the defects in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a circuit topology comprises two independent direct current conversion circuits arranged on a battery side, wherein each direct current conversion circuit is independently connected with a primary side of a transformer, a secondary side of each transformer is independently connected with a second-stage boosting/reducing circuit, and the two second-stage boosting/reducing circuits are respectively connected with a positive direct current bus and an auxiliary direct current bus.
Further, the secondary side of each transformer is connected with the corresponding second-stage boost/buck circuit through a group of full-bridge LLC series resonant circuits.
Further, the two direct current conversion circuits both adopt a full-bridge circuit.
Furthermore, the battery is connected in parallel with a first capacitor C1, one of the dc conversion circuits includes first to fourth switches S1-S4, one end of the first capacitor C1 is connected to one end of the first switch S1, the other end of the first capacitor C1 is connected to the other end of the second switch S2, the other end of the first switch S1 is connected to one end of the second switch S2, one end of the third switch S3 is connected to one end of the first switch S1, the other end of the third switch S3 is connected to one end of the fourth switch S4, the other end of the fourth switch S4 is connected to the other end of the second switch S2, one end of a primary side N1 of the first transformer TX1 is connected to a connection point of the first switch S1 and the second switch S2, and the other end of a primary side N1 of the first transformer TX1 is connected to a connection point of the third switch S3 and the fourth switch S4; the other direct current conversion circuit comprises eleventh to fourteenth switches S11-S14, one end of a first capacitor C1 is connected with one end of an eleventh switch S11, the other end of the first capacitor C1 is connected with the other end of a twelfth switch S12, the other end of an eleventh switch S11 is connected with one end of a twelfth switch S12, one end of a thirteenth switch S13 is connected with one end of an eleventh switch S11, the other end of a thirteenth switch S13 is connected with one end of a fourteenth switch S14, the other end of the fourteenth switch S14 is connected with the other end of a twelfth switch S12, one end of a primary side N3 of a second transformer TX2 is connected with a connection point of the eleventh switch S11 and the twelfth switch S12, and the other end of a primary side N3 of the second transformer TX2 is connected with a connection point of the thirteenth switch S13 and the fourteenth switch S14.
Furthermore, one full-bridge LLC series resonant circuit comprises a second inductor L2, a second capacitor C2 and fifth to eighth switches S5 to S8, wherein one end of a secondary side N2 of the first transformer TX1 is connected with the second inductor L2 and the second capacitor C2 in series and connected to a point d; the other end of the secondary side N2 of the first transformer TX1 is connected to point c, one end of a fifth switch S5 is connected to one end of a seventh switch S7, the other end of the fifth switch S5 is connected to point c with a sixth switch S6, the other end of the sixth switch S6 is connected to the other end of an eighth switch S8, and the other end of the seventh switch S7 is connected to point d with an end of an eighth switch S8; the other full-bridge LLC series resonance circuit comprises a third inductor L3, a fifth capacitor C5, a fifteenth switch to an eighteenth switch S15-S18, one end of a secondary side N4 of a second transformer TX2 is connected with the third inductor L3 and the fifth capacitor C5 in series and connected to a point h, and the other end of the secondary side N4 of the second transformer TX2 is connected to a point g; one end of the fifteenth switch S15 is connected to one end of a seventeenth switch S17, the other end of the fifteenth switch S15 is connected to the sixteenth switch S16 at a point g, the other end of the sixteenth switch S16 is connected to the other end of the eighteenth switch S18, and the other end of the seventeenth switch S17 is connected to the one end of the eighteenth switch S18 at a point h.
Furthermore, one of the second-stage boost/buck circuits includes a third capacitor C3, a fourth capacitor C4, a first inductor L1, a ninth switch S9 and a tenth switch S10, one end of the third capacitor C3 is connected to one end of a seventh switch S7 and one end of a first inductor L1, the other end of the third capacitor C3 is connected to the other end of an eighth switch S8 at the point N, the other end of the first inductor L1 is connected to one end of a ninth switch S9 and one end of a tenth switch S10, the other end of the ninth switch S9 is connected to the point N, the other end of the tenth switch S10 is connected to one end of a fourth capacitor C4, and the connection point is BUS +; the other end of the capacitor C4 is connected to a point N, the point N is grounded, and BUS + and the point N form a positive direct current BUS; the other second-stage boosting/dropping circuit comprises a sixth capacitor C6, a seventh capacitor C7, a fourth inductor L4, a nineteenth switch S19 and a twentieth switch S20, one end of the sixth capacitor C6 is connected with one end of the seventh switch S17 to a point N, the other end of the sixth capacitor C6 is connected with the other end of the eighteenth switch S18 and one end of the fourth inductor L4, the other end of the fourth inductor L4 is connected with the other end of the nineteenth switch S19 and one end of the twentieth switch S20, one end of the nineteenth switch S19 is connected to the point N, the other end of the twentieth switch S20 is connected with the other end of the seventh capacitor C7, the connection point is BUS-, one end of the seventh capacitor C7 is connected to the point N, and the point N and the BUS constitute a negative direct current BUS.
The invention also provides a control method of the circuit topology, which comprises the following steps:
s1, limiting the charging and discharging current amplitude value after the difference value between the positive and negative direct current bus total pressure Vbus and the control reference value Vbus ref of the positive and negative direct current bus total pressure passes through a PI controller to obtain a total current reference Imo;
s2, judging the size of the total current reference Imo, if the total current reference is a positive value, charging is carried out, and if the total current reference is a negative value, discharging is carried out;
s3, limiting the charging and discharging current amplitude value after the difference value between the positive direct current bus voltage Vpbus and the negative direct current bus voltage Vnbus passes through a PI controller to obtain a current difference value reference Iemo, adding the total current reference Imo and the current difference value reference Iemo to obtain a current reference Ipref of the positive direct current bus, and subtracting the total current reference Imo and the current difference value reference Iemo to obtain a current reference Inref of the negative direct current bus;
s4, limiting the charging and discharging current amplitude value after the difference value of the current reference Ipref and the current Ipbus of the first inductor L1 passes through a PI control value to obtain a duty ratio PWM1, if the duty ratio PWM1 is positive, the ninth switch S9 is turned off, and the duty ratio PWM1 is the duty ratio of the tenth switch S10; if the duty ratio PWM1 is negative, the tenth switch S10 is turned off, and the absolute value of the duty ratio PWM1 is the duty ratio of the ninth switch S9; and (3) carrying out back-limit charging and discharging current amplitude values on the difference value of the current reference Inref and the current Inbus of the fourth inductor L4 through a PI control value to obtain a duty ratio PWM2, if the duty ratio PWM2 is positive, a nineteenth switch S19 is turned off, the duty ratio PWM2 is the duty ratio of a twentieth switch S20, if the duty ratio PWM2 is negative, a twentieth switch S20 is turned off, and the absolute value of the duty ratio PWM2 is the duty ratio of a switch S19.
The invention also provides an electronic device comprising the circuit topology.
Further, the electronic equipment is an off-grid inverter and an uninterruptible power supply.
Compared with the prior art, the invention has the advantages that: the invention can adjust the voltage balance of the double buses; and for the inverter using a double-bus circuit topology (such as three levels and connection of a high-voltage photovoltaic assembly), the adaptability to unbalanced loads is improved, and an effective solution is provided for an uninterruptible power supply and an inverter product with high matching requirements on the high-voltage photovoltaic assembly and the loads.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a circuit topology of the present invention.
Fig. 2 is a circuit diagram showing the switches S2, S3, S6 and S7 turned on when the battery terminal of the present invention is discharged to the positive dc bus.
Fig. 3 is a circuit diagram showing the switches S2, S3, S6 and S7 turned off when the battery terminal of the present invention is discharged to the positive dc bus.
FIG. 4 is a circuit diagram showing the switches S2, S3, S6 and S7 being turned on when the positive DC bus charges the battery terminal.
Fig. 5 is a circuit diagram showing the switches S2, S3, S6 and S7 being turned off when the positive dc bus charges the battery terminal according to the present invention.
Fig. 6 is a circuit diagram of the switch S9 being turned on when the battery terminal is discharging to the positive dc bus according to the present invention.
Fig. 7 is a circuit diagram of the switch S9 being closed when the battery terminal of the present invention is discharging to the positive dc bus.
Fig. 8 is a circuit diagram of the switch S10 being turned on when the positive dc bus charges the battery terminal according to the present invention.
Fig. 9 is a circuit diagram of the switch S10 being turned off when the positive dc bus charges the battery terminal according to the present invention.
Fig. 10 is a circuit diagram showing the switches S12, S13, S16 and S17 being turned on when the battery terminal of the present invention is discharged to the negative dc bus.
FIG. 11 is a circuit diagram showing the switches S12, S13, S16 and S17 being turned off when the battery terminal of the present invention is discharged to the negative DC bus.
Fig. 12 is a circuit diagram showing the switches S12, S13, S16 and S17 being turned on when the negative dc bus charges the battery terminal according to the present invention.
Fig. 13 is a circuit diagram showing the switches S12, S13, S16 and S17 being turned off when the negative dc bus charges the battery terminal according to the present invention.
Fig. 14 is a circuit diagram of the switch S19 being turned on when the battery terminal is discharging to the negative dc bus according to the present invention.
Fig. 15 is a circuit diagram of the switch S19 being closed when the battery terminal of the present invention is discharging to the negative dc bus.
Fig. 16 is a circuit diagram of the switch S20 being turned on when the negative dc bus charges the battery terminal according to the present invention.
Fig. 17 is a circuit diagram of the switch S20 being turned off when the negative dc bus charges the battery terminal according to the present invention.
Fig. 18 is a control loop diagram of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, and the scope of the present invention will be more clearly and clearly defined.
Example one
The embodiment provides a circuit topology, which includes two independent dc conversion circuits disposed on a battery side, wherein each of the dc conversion circuits is independently connected to a primary side of a transformer, a secondary side of each transformer is independently connected to a second step-up/step-down circuit, and the two second step-up/step-down circuits are respectively connected to a positive dc bus and a secondary dc bus.
In this embodiment, two dc conversion circuits both adopt full bridge circuits, a battery BAT is connected in parallel with a first capacitor C1, one of the dc conversion circuits includes first to fourth switches S1-S4, one end of the first capacitor C1 is connected with one end of the first switch S1, the other end of the first capacitor C1 is connected with the other end of the second switch S2, the other end of the first switch S1 is connected with one end of the second switch S2, one end of the third switch S3 is connected with one end of the first switch S1, the other end of the third switch S3 is connected with one end of the fourth switch S4, the other end of the fourth switch S4 is connected with the other end of the second switch S2, one end of a primary side N1 of a first transformer TX1 is connected with a connection point of the first primary side S1 and the second switch S2, and the other end of the first transformer TX 1N 1 is connected with a connection point of the first switch S3 and the fourth switch S4; the other direct current conversion circuit comprises eleventh to fourteenth switches S11-S14, one end of a first capacitor C1 is connected with one end of an eleventh switch S11, the other end of the first capacitor C1 is connected with the other end of a twelfth switch S12, the other end of an eleventh switch S11 is connected with one end of a twelfth switch S12, one end of a thirteenth switch S13 is connected with one end of an eleventh switch S11, the other end of a thirteenth switch S13 is connected with one end of a fourteenth switch S14, the other end of the fourteenth switch S14 is connected with the other end of a twelfth switch S12, one end of a primary side N3 of a second transformer TX2 is connected with a connection point of the eleventh switch S11 and the twelfth switch S12, and the other end of a primary side N3 of the second transformer TX2 is connected with a connection point of the thirteenth switch S13 and the fourteenth switch S14.
In this embodiment, the secondary side of each transformer is connected to the corresponding second-stage boost/buck circuit through a set of full-bridge LLC series resonant circuits.
Preferably, one full-bridge LLC series resonant circuit comprises a second inductor L2, a second capacitor C2, and fifth to eighth switches S5-S8, one end of a secondary side N2 of the first transformer TX1 is connected in series with the second inductor L2 and the second capacitor C2, and is connected to the point d; the other end of the secondary side N2 of the first transformer TX1 is connected to point c, one end of a fifth switch S5 is connected to one end of a seventh switch S7, the other end of the fifth switch S5 is connected to point c with a sixth switch S6, the other end of the sixth switch S6 is connected to the other end of an eighth switch S8, and the other end of the seventh switch S7 is connected to point d with an end of an eighth switch S8; the other full-bridge LLC series resonance circuit comprises a third inductor L3, a fifth capacitor C5, a fifteenth switch to an eighteenth switch S15-S18, one end of a secondary side N4 of a second transformer TX2 is connected with the third inductor L3 and the fifth capacitor C5 in series and connected to a point h, and the other end of the secondary side N4 of the second transformer TX2 is connected to a point g; one end of the fifteenth switch S15 is connected to one end of a seventeenth switch S17, the other end of the fifteenth switch S15 is connected to the sixteenth switch S16 at a point g, the other end of the sixteenth switch S16 is connected to the other end of the eighteenth switch S18, and the other end of the seventeenth switch S17 is connected to the one end of the eighteenth switch S18 at a point h.
Preferably, one of the second-stage boost/buck circuits includes a third capacitor C3, a fourth capacitor C4, a first inductor L1, a ninth switch S9 and a tenth switch S10, one end of the third capacitor C3 is connected to one end of a seventh switch S7 and one end of a first inductor L1, the other end of the third capacitor C3 is connected to the other end of an eighth switch S8 at a point N, the other end of the first inductor L1 is connected to one end of a ninth switch S9 and one end of a tenth switch S10, the other end of the ninth switch S9 is connected to the point N, the other end of the tenth switch S10 is connected to one end of a fourth capacitor C4, and the connection point is BUS +; the other end of the capacitor C4 is connected to a point N, the point N is grounded, and BUS + and the point N form a positive direct current BUS; the charging voltage/current from the positive direct current bus to the battery side can be adjusted through the circuit, and the discharging voltage/current from the battery side to the positive direct current bus can also be adjusted, so that the final purpose of adjusting the positive direct current bus is achieved.
The other second-stage boosting/voltage-reducing circuit comprises a sixth capacitor C6, a seventh capacitor C7, a fourth inductor L4, a nineteenth switch S19 and a twentieth switch S20, one end of the sixth capacitor C6 is connected with one end of the seventh switch S17 to a point N, the other end of the sixth capacitor C6 is connected with the other end of the eighteenth switch S18 and one end of the fourth inductor L4, the other end of the fourth inductor L4 is connected with the other end of the nineteenth switch S19 and one end of the twentieth switch S20, one end of the nineteenth switch S19 is connected to the point N, the other end of the twentieth switch S20 is connected with the other end of the seventh capacitor C7, the connection point is BUS-, one end of the seventh capacitor C7 is connected to the point N, and the point N and the BUS form a negative direct; the charging voltage/current from the negative direct current bus to the battery side can be adjusted through the circuit, and the discharging voltage/current from the battery side to the negative direct current bus can also be adjusted, so that the final purpose of adjusting the negative direct current bus is achieved.
The circuit topology of the present embodiment is divided into four modules, which are described below:
the LLC circuit is connected from a battery end to a positive direct-current bus, when the battery end discharges to the positive direct-current bus, the battery side switches S2 and S3 are conducted, the high-voltage side switches S6 and S7 of the transformer TX1 are conducted, the battery transmits energy to the high-voltage side capacitor C3 through the transformer TX1, and a circuit loop is shown in FIG. 2; switches S2, S3, S6 and S7 are turned off, battery side switches S1 and S4 are turned on, high-voltage side switches S5 and S8 of a transformer TX1 are turned on, the battery transmits energy to a high-voltage side capacitor C3 through a transformer TX1, and a circuit loop is shown in fig. 3. Through the above two steps, the switches S1-S8 are turned on and off alternately, and the battery BAT side conducts energy to the high-voltage side capacitor C3 through the transformer TX 1. When the positive direct current bus charges the battery, the battery side switches S2 and S3 are turned on, the high-voltage side switches S6 and S7 of the transformer TX1 are turned on, the high-voltage side capacitor C3 transmits energy to the battery through the transformer TX1, and a circuit loop is shown in fig. 4; switches S2, S3, S6 and S7 are turned off, battery side switches S1 and S4 are turned on, high-voltage side switches S5 and S8 of a transformer TX1 are turned on, a high-voltage side capacitor C3 supplies energy to the battery through the transformer TX1, and a circuit loop is shown in fig. 5. Through the above two steps, the switches S1-S8 are turned on and off alternately, and the battery side conducts energy to the high-side capacitor C3 through the transformer TX 1. For this reason, the present embodiment can realize the mutual energy transfer between the battery terminal and the high-voltage side capacitor C3 of the transformer TX1 by alternately turning on and off the switches S1-S8.
Secondly, when the battery end discharges to the positive direct current bus, the switch S9 is switched on, the capacitor C3 transmits energy to the inductor L1, and a circuit loop is shown in FIG. 6; when the switch S9 is turned off, the energy stored in the capacitor C3 and the inductor L1 is transferred to the positive dc bus capacitor C4 through the switch S10 to form a boost circuit, which is shown in fig. 7. When the positive dc bus charges the battery, the switch S10 is turned on, and the positive dc bus capacitor C4 charges the capacitor C3 through the inductor L1, and the circuit loop is shown in fig. 8. When the switch S10 is turned off, the inductor L1 freewheels through the switch S9 to transfer energy to the capacitor C3, forming a step-down circuit, which is shown in fig. 9.
Thirdly, when the battery end discharges to the negative direct current bus, the battery side switches S12 and S13 are turned on, the high-voltage side switches S16 and S17 of the transformer TX2 are turned on, the battery transmits energy to the high-voltage side capacitor C6 through the transformer TX2, and a circuit loop is shown in fig. 10; switches S12, S13, S16 and S17 are turned off, battery side switches S11 and S14 are turned on, high-voltage side switches S15 and S18 of a transformer TX2 are turned on, the battery transmits energy to a high-voltage side capacitor C6 through a transformer TX2, and a circuit loop is shown in fig. 11. Through the above two steps, the switches S11-S18 are turned on and off alternately, and the battery side conducts energy to the high-side capacitor C6 through the transformer TX 2. When the negative direct current bus charges the battery, the battery side switches S12 and S13 are turned on, the high-voltage side switches S16 and S17 of the transformer TX2 are turned on, the high-voltage side capacitor C6 transmits energy to the battery through the transformer TX2, and a circuit loop is shown in fig. 12; switches S12, S13, S16 and S17 are turned off, battery side switches S11 and S14 are turned on, high-voltage side switches S15 and S18 of a transformer TX2 are turned on, high-voltage side C6 transmits energy to the battery through the transformer TX2, and a circuit loop is shown in fig. 13. Through the above two steps, the switches S11-S18 are turned on and off alternately, and the battery side conducts energy to the high-side capacitor C6 through the transformer TX 2. For this reason, the present embodiment can realize the mutual energy transfer between the battery terminal and the high-voltage side capacitor C6 of the transformer TX2 by alternately turning on and off the switches S11-S18.
Fourthly, a secondary buck-boost circuit from the battery end to the negative direct current bus, when the battery end discharges to the negative direct current bus, the switch S19 is conducted, the capacitor C6 transmits energy to the inductor L4, and a circuit loop is shown in FIG. 14; when the switch S19 is turned off, the energy stored in the capacitor C6 and the inductor L4 is transferred to the positive dc bus capacitor C7 through the switch S20 to form a boost circuit, and the circuit loop is shown in fig. 15. When the negative dc bus charges the battery, the switch S20 is turned on, and the positive dc bus capacitor C7 charges the capacitor C6 through the inductor L4, and the circuit loop is shown in fig. 16. When the switch S10 is turned off, the inductor L4 freewheels through the switch S19 to transfer energy to the capacitor C6, forming a step-down circuit, which is shown in fig. 17.
When the double-direct-current bus voltage is unbalanced in specific use, the following six different practical application conditions mainly exist:
1. the positive dc bus voltage is high (set as needed), the negative dc bus voltage is low (set as needed), and overall the energy of the dc bus needs to be charged to the battery side. Adjusting the duty ratio of a switch S10 of a secondary buck-boost circuit on the positive dc bus to control the charging current of the positive dc bus to the battery side, where the circuit loop is shown in fig. 4, 5, 8, and 9; adjusting the duty ratio of a switch S20 of the secondary buck-boost circuit on the negative dc bus to control the charging current of the negative dc bus to the battery side, where the circuit loop is shown in fig. 12, 13, 16, and 17; the total pressure of the positive and negative direct current buses under the condition can be controlled and maintained through charging of the positive and negative direct current buses; when the charging current from the positive direct current bus to the battery side is larger than the charging current from the negative direct current bus to the battery side, the voltage of the positive direct current bus can be reduced, the voltage of the negative direct current bus can be increased, and the voltage difference between the positive direct current bus and the negative direct current bus is reduced.
2. The positive current bus voltage is higher, the negative direct current bus voltage is lower, and the energy of the direct current bus is critical on the whole. Adjusting the duty ratio of a switch S10 of a secondary buck-boost circuit on the positive dc bus to control the charging current of the positive dc bus to the battery side, where the circuit loop is shown in fig. 4, 5, 8, and 9; adjusting the duty ratio of a switch S19 of a secondary buck-boost circuit on the negative dc bus to control the discharge current from the battery side to the negative dc bus, where the circuit loop is shown in fig. 10, 11, 14, and 15; through the adjustment of charging and discharging, the total pressure of the positive and negative direct current buses can be controlled and maintained under the critical condition, and because the positive direct current buses are charged to the voltage side, and the battery side is discharged to the negative direct current buses, the voltage of the positive direct current buses can be reduced, the voltage of the negative direct current buses can be increased, and the pressure difference of the positive and negative direct current buses is reduced.
3. The positive dc bus voltage is high and the negative dc bus voltage is low, generally when the battery side is required to discharge to the dc bus. Adjusting the duty ratio of a switch S9 of a secondary buck-boost circuit on the positive direct current bus to control the discharge current of the battery side to the positive direct current bus, wherein the circuit loop is shown in fig. 2, fig. 3, fig. 6 and fig. 7; adjusting the duty ratio of a switch S19 of a secondary buck-boost circuit on the negative dc bus to control the discharge current from the battery side to the negative dc bus, where the circuit loop is shown in fig. 10, 11, 14, and 15; the total pressure of the positive and negative direct current buses can be controlled and maintained through the discharge of the positive and negative direct current buses; when the discharging current from the battery side to the positive direct current bus is smaller than the discharging current from the battery side to the negative direct current bus, the voltage of the positive direct current bus is reduced, the voltage of the negative direct current bus is increased, and the voltage difference between the positive direct current bus and the negative direct current bus is reduced.
4. The positive dc bus voltage is low, the negative dc bus voltage is high, and the energy of the dc bus needs to be charged to the battery side as a whole. Adjusting the duty ratio of a switch S10 of a secondary buck-boost circuit on the positive dc bus to control the charging current of the positive dc bus to the battery side, where the circuit loop is shown in fig. 4, 5, 8, and 9; adjusting the duty ratio of a switch S20 of the secondary buck-boost circuit on the negative dc bus to control the charging current of the negative dc bus to the battery side, where the circuit loop is shown in fig. 12, 13, 16, and 17; the total pressure of the positive and negative direct current buses under the condition can be controlled and maintained through charging of the positive and negative direct current buses; when the charging current from the positive direct current bus to the battery side is smaller than the charging current from the negative direct current bus to the battery side, the voltage of the positive direct current bus can be increased, the voltage of the negative direct current bus can be reduced, and the voltage difference between the positive direct current bus and the negative direct current bus is reduced.
5. The positive current bus voltage is low, the negative direct current bus voltage is high, and the energy of the direct current bus is critical. Adjusting the duty ratio of a switch S9 of a secondary buck-boost circuit on the positive direct current bus to control the discharge current of the battery side to the positive direct current bus, wherein the circuit loop is shown in fig. 2, fig. 3, fig. 6 and fig. 7; adjusting the duty ratio of a switch S20 of the secondary buck-boost circuit on the negative dc bus to control the charging current of the negative dc bus to the battery side, where the circuit loop is shown in fig. 12, 13, 16, and 17; through the adjustment of charging and discharging, the total voltage of the positive and negative direct current buses can be controlled and maintained under the critical condition, and the voltage of the positive direct current bus can be increased and the voltage of the negative direct current bus can be reduced because the voltage side discharges to the positive direct current bus and the negative direct current bus charges to the battery side, so that the voltage difference of the positive and negative direct current buses is reduced.
6. The positive dc bus voltage is low and the negative dc bus voltage is high, generally when the battery side is required to discharge to the dc bus. Adjusting the duty ratio of a switch S9 of a secondary buck-boost circuit on the positive direct current bus to control the discharge current of the battery side to the positive direct current bus, wherein the circuit loop is shown in fig. 2, fig. 3, fig. 6 and fig. 7; adjusting the duty ratio of a switch S19 of a secondary buck-boost circuit on the negative dc bus to control the discharge current from the battery side to the negative dc bus, where the circuit loop is shown in fig. 10, 11, 14, and 15; the total pressure of the positive and negative direct current buses can be controlled and maintained through the discharge of the positive and negative direct current buses; when the discharging current from the battery side to the positive direct current bus is larger than the discharging current from the battery side to the negative direct current bus, the voltage of the positive direct current bus can be increased, the voltage of the negative direct current bus can be reduced, and the voltage difference between the positive direct current bus and the negative direct current bus is reduced.
By combining the above six different application conditions, the charging and discharging conditions of the positive and negative total direct current buses and the battery side can be judged through the comparison value of the actual total pressure of the positive and negative direct current buses and the control quantity required to control the total pressure of the positive and negative direct current buses. The charging and discharging conditions of the positive and negative direct current lines and the battery side can be judged according to the voltage difference of the positive and negative direct current lines and the charging and discharging conditions of the main direct current bus and the battery side, and finally the duty ratio adjusting conditions of the switching tubes of the secondary buck-boost circuits are obtained.
Referring to fig. 18, a control block diagram designed according to the above six cases is shown, which employs dual-loop control of the voltage outer loop and the current inner loop. The parameter Vbus is a total pressure of the positive and negative direct-current buses, the parameter Vbusref is a control reference value of the total pressure of the positive and negative direct-current buses, the parameter Vpbus is a positive direct-current bus voltage, the parameter Vnbus is a negative direct-current bus voltage, the parameter Ipbus is a current of an inductor L1, the parameter Inbus is a current of an inductor L4, the parameter PWM1 is a duty ratio of a switch S9 and a switch S10 (a positive value is a duty ratio of a switch S9 which is turned off and a switch S10, an absolute value of a negative value is a duty ratio of a switch S9 which is turned off and a switch S10), and the parameter PWM2 is a duty ratio of a switch S19 and a switch S20 (a positive value is a duty ratio of a switch S19 which is turned off and a switch S20, and an absolute value of a negative value is a duty ratio of a switch S19 which is turned off and a switch S20).
Based on the control block diagram shown in fig. 18, the control method is designed as follows:
and step S1, the difference value between the total voltage Vbus of the positive and negative direct current buses and the control reference value Vbus ref of the total voltage of the positive and negative direct current buses is subjected to back limit charge and discharge current amplitude value through a PI controller to obtain a total current reference Imo.
Step S2, the total current reference Imo is determined, and if the total current reference is positive, the charging is performed, and if the total current reference is negative, the discharging is performed.
And step S3, limiting the charging and discharging current amplitude value after the difference value between the positive direct current bus voltage Vpbus and the negative direct current bus voltage Vnbus passes through a PI controller to obtain a current difference value reference Iemo, adding the total current reference Imo and the current difference value reference Iemo to obtain a current reference Ipref of the positive direct current bus, and subtracting the total current reference Imo and the current difference value reference Iemo to obtain a current reference Inref of the negative direct current bus.
Step S4, the difference value of the current reference Ipref and the current Ipbus of the first inductor L1 is subjected to PI control value, then the charging and discharging current amplitude value is limited, a duty ratio PWM1 is obtained, if the duty ratio PWM1 is positive, the ninth switch S9 is turned off, and the duty ratio PWM1 is the duty ratio of the tenth switch S10; if the duty ratio PWM1 is negative, the tenth switch S10 is turned off, and the absolute value of the duty ratio PWM1 is the duty ratio of the ninth switch S9; and (3) carrying out back-limit charging and discharging current amplitude values on the difference value of the current reference Inref and the current Inbus of the fourth inductor L4 through a PI control value to obtain a duty ratio PWM2, if the duty ratio PWM2 is positive, a nineteenth switch S19 is turned off, the duty ratio PWM2 is the duty ratio of a twentieth switch S20, if the duty ratio PWM2 is negative, a twentieth switch S20 is turned off, and the absolute value of the duty ratio PWM2 is the duty ratio of a switch S19.
In summary, the controller and the corresponding control method are designed through the control block diagram, so that six different practical application situations can be realized, and the requirement for adjusting the imbalance of the positive and negative direct current buses is met.
The circuit topology of the embodiment can realize the voltage balance adjusting function of the positive and negative direct current buses by adjusting the charging and discharging current from the positive and negative direct current buses to the current side, and can completely solve the problem of unbalance of the double direct current buses.
Example two
The embodiment provides an off-grid inverter, which comprises the circuit topology described in the first embodiment, and the off-grid inverter can adjust double-bus voltage balance after application, so that the adaptability to unbalanced loads is improved.
The voltage balance of the double buses can be adjusted; and for the inverter using a double-bus circuit topology (such as three levels and connection of a high-voltage photovoltaic assembly), the adaptability to unbalanced loads is improved, and an effective solution is provided for an uninterruptible power supply and an inverter product with high matching requirements on the high-voltage photovoltaic assembly and the loads.
EXAMPLE III
The present embodiment provides an uninterruptible power supply, which includes the circuit topology described in the first embodiment, and the uninterruptible power supply can adjust the voltage balance of the double bus after being applied, thereby improving the adaptability to unbalanced loads.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, various changes or modifications may be made by the patentees within the scope of the appended claims, and within the scope of the invention, as long as they do not exceed the scope of the invention described in the claims.

Claims (9)

1. A circuit topology, characterized by: the direct current conversion circuit comprises two independent direct current conversion circuits arranged on a battery side, wherein each direct current conversion circuit is independently connected with a primary side of a transformer, a secondary side of each transformer is independently connected with a second-stage boosting/reducing circuit, and the two second-stage boosting/reducing circuits are respectively connected with a positive direct current bus and an auxiliary direct current bus.
2. The circuit topology of claim 1, wherein: and the secondary side of each transformer is connected with the corresponding second-stage boosting/reducing circuit through a group of full-bridge LLC series resonance circuits.
3. The circuit topology of claim 2, wherein: and the two direct current conversion circuits adopt full-bridge circuits.
4. The circuit topology of claim 3, wherein: the battery is connected with a first capacitor C1 in parallel, one of the direct current conversion circuits comprises first to fourth switches S1-S4, one end of the first capacitor C1 is connected with one end of the first switch S1, the other end of the first capacitor C1 is connected with the other end of the second switch S2, the other end of the first switch S1 is connected with one end of the second switch S2, one end of a third switch S3 is connected with one end of the first switch S1, the other end of the third switch S3 is connected with one end of the fourth switch S4, the other end of the fourth switch S4 is connected with the other end of the second switch S2, one end of a primary side N1 of a first transformer TX1 is connected with a connection point of the first switch S1 and the second switch S2, and the other end of a primary side N1 of the first transformer TX1 is connected with a connection point of the third switch S3 and the fourth switch S4; the other direct current conversion circuit comprises eleventh to fourteenth switches S11-S14, one end of a first capacitor C1 is connected with one end of an eleventh switch S11, the other end of the first capacitor C1 is connected with the other end of a twelfth switch S12, the other end of an eleventh switch S11 is connected with one end of a twelfth switch S12, one end of a thirteenth switch S13 is connected with one end of an eleventh switch S11, the other end of a thirteenth switch S13 is connected with one end of a fourteenth switch S14, the other end of the fourteenth switch S14 is connected with the other end of a twelfth switch S12, one end of a primary side N3 of a second transformer TX2 is connected with a connection point of the eleventh switch S11 and the twelfth switch S12, and the other end of a primary side N3 of the second transformer TX2 is connected with a connection point of the thirteenth switch S13 and the fourteenth switch S14.
5. The circuit topology of claim 4, wherein: one full-bridge LLC series resonance circuit comprises a second inductor L2, a second capacitor C2 and fifth to eighth switches S5-S8, wherein one end of a secondary side N2 of a first transformer TX1 is connected with the second inductor L2 and the second capacitor C2 in series and connected to a point d; the other end of the secondary side N2 of the first transformer TX1 is connected to point c, one end of a fifth switch S5 is connected to one end of a seventh switch S7, the other end of the fifth switch S5 is connected to point c with a sixth switch S6, the other end of the sixth switch S6 is connected to the other end of an eighth switch S8, and the other end of the seventh switch S7 is connected to point d with an end of an eighth switch S8; the other full-bridge LLC series resonance circuit comprises a third inductor L3, a fifth capacitor C5, a fifteenth switch to an eighteenth switch S15-S18, one end of a secondary side N4 of a second transformer TX2 is connected with the third inductor L3 and the fifth capacitor C5 in series and connected to a point h, and the other end of the secondary side N4 of the second transformer TX2 is connected to a point g; one end of the fifteenth switch S15 is connected to one end of a seventeenth switch S17, the other end of the fifteenth switch S15 is connected to the sixteenth switch S16 at a point g, the other end of the sixteenth switch S16 is connected to the other end of the eighteenth switch S18, and the other end of the seventeenth switch S17 is connected to the one end of the eighteenth switch S18 at a point h.
6. The circuit topology of claim 5, wherein: one of the second-stage boost/buck circuits includes a third capacitor C3, a fourth capacitor C4, a first inductor L1, a ninth switch S9 and a tenth switch S10, one end of the third capacitor C3 is connected to one end of a seventh switch S7 and one end of the first inductor L1, the other end of the third capacitor C3 is connected to the other end of an eighth switch S8 to a point N, the other end of the first inductor L1 is connected to one end of a ninth switch S9 and one end of the tenth switch S10, the other end of the ninth switch S9 is connected to the point N, the other end of the tenth switch S10 is connected to one end of the fourth capacitor C4, and the connection point is BUS +; the other end of the capacitor C4 is connected to a point N, the point N is grounded, and BUS + and the point N form a positive direct current BUS; the other second-stage boosting/dropping circuit comprises a sixth capacitor C6, a seventh capacitor C7, a fourth inductor L4, a nineteenth switch S19 and a twentieth switch S20, one end of the sixth capacitor C6 is connected with one end of the seventh switch S17 to a point N, the other end of the sixth capacitor C6 is connected with the other end of the eighteenth switch S18 and one end of the fourth inductor L4, the other end of the fourth inductor L4 is connected with the other end of the nineteenth switch S19 and one end of the twentieth switch S20, one end of the nineteenth switch S19 is connected to the point N, the other end of the twentieth switch S20 is connected with the other end of the seventh capacitor C7, the connection point is BUS-, one end of the seventh capacitor C7 is connected to the point N, and the point N and the BUS constitute a negative direct current BUS.
7. A method of controlling a circuit topology according to claim 5, comprising the steps of:
s1, limiting the charging and discharging current amplitude value after the difference value between the positive and negative direct current bus total pressure Vbus and the control reference value Vbus ref of the positive and negative direct current bus total pressure passes through a PI controller to obtain a total current reference Imo;
s2, judging the size of the total current reference Imo, if the total current reference is a positive value, charging is carried out, and if the total current reference is a negative value, discharging is carried out;
s3, limiting the charging and discharging current amplitude value after the difference value between the positive direct current bus voltage Vpbus and the negative direct current bus voltage Vnbus passes through a PI controller to obtain a current difference value reference Iemo, adding the total current reference Imo and the current difference value reference Iemo to obtain a current reference Ipref of the positive direct current bus, and subtracting the total current reference Imo and the current difference value reference Iemo to obtain a current reference Inref of the negative direct current bus;
s4, limiting the charging and discharging current amplitude value after the difference value of the current reference Ipref and the current Ipbus of the first inductor L1 passes through a PI control value to obtain a duty ratio PWM1, if the duty ratio PWM1 is positive, the ninth switch S9 is turned off, and the duty ratio PWM1 is the duty ratio of the tenth switch S10; if the duty ratio PWM1 is negative, the tenth switch S10 is turned off, and the absolute value of the duty ratio PWM1 is the duty ratio of the ninth switch S9; and (3) carrying out back-limit charging and discharging current amplitude values on the difference value of the current reference Inref and the current Inbus of the fourth inductor L4 through a PI control value to obtain a duty ratio PWM2, if the duty ratio PWM2 is positive, a nineteenth switch S19 is turned off, the duty ratio PWM2 is the duty ratio of a twentieth switch S20, if the duty ratio PWM2 is negative, a twentieth switch S20 is turned off, and the absolute value of the duty ratio PWM2 is the duty ratio of a switch S19.
8. An electronic device, characterized in that it comprises a circuit topology according to any of claims 1-6.
9. The electronic device of claim 8, wherein the electronic device is an off-grid inverter and an uninterruptible power supply.
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