CN113271202B

CN113271202B - Data encryption method and device

Info

Publication number: CN113271202B
Application number: CN202010092619.5A
Authority: CN
Inventors: 丁伟; 魏明江
Original assignee: China Mobile Communications Group Co Ltd; China Mobile Suzhou Software Technology Co Ltd
Current assignee: China Mobile Communications Group Co Ltd; China Mobile Suzhou Software Technology Co Ltd
Priority date: 2020-02-14
Filing date: 2020-02-14
Publication date: 2022-05-31
Anticipated expiration: 2040-02-14
Also published as: CN113271202A

Abstract

The application discloses a data encryption method, which comprises the following steps: generating a first pseudo random number, a second pseudo random number and a first state vector by a key scheduling algorithm KSA; generating a keystream sequence based on the first pseudorandom number, the second pseudorandom number, and the first state vector by a random keystream sequence generation algorithm (PRGA); and encrypting the plaintext data by using the key stream sequence to obtain encrypted data. Through the technical scheme of the embodiment of the application, the first pseudo-random number and the second pseudo-random number generated in the operation by utilizing the KSA algorithm in the RC4 algorithm can be used as the initial values of the first variable parameter and the second variable parameter of the first state vector in the PRGA algorithm process, so that the randomness of the initial values of the first variable parameter and the second variable parameter in the PRGA algorithm process is effectively improved, and the security of data encryption is improved.

Description

Data encryption method and device

Technical Field

The present disclosure relates to data encryption technologies, and in particular, to a data encryption method and apparatus.

Background

In various application scenarios, when data is transmitted, the data to be transmitted needs to be encrypted first to improve the security of data transmission, and therefore what encryption method is adopted is a problem to be considered in the process of encrypting the data. In encrypting Data, commonly used Data Encryption methods include Data Encryption Standard (DES), International Data Encryption Algorithm (IDEA), RC5 (i.e., Rivest Cipher 5), Tiny Encryption Algorithm (TEA), Skipjack Encryption Algorithm, and Advanced Encryption Standard (AES). The cipher text length of the DES algorithm and the Skipjack encryption algorithm is shorter, and the security is lower; the RC5 algorithm requires sufficient memory space at key initialization; the TEA algorithm and the IDEA algorithm are only subjected to simple XOR and shift operation during encryption and are easy to crack; the AES algorithm has good performance in terms of security, but the number of encryption rounds is too large, which reduces the efficiency of the encryption process.

Disclosure of Invention

In order to solve the above technical problem, embodiments of the present application provide a data encryption method and apparatus.

The data encryption method provided by the embodiment of the application comprises the following steps: generating a first pseudo random number, a second pseudo random number and a first state vector by a key scheduling algorithm KSA;

generating a keystream sequence based on the first pseudorandom number, the second pseudorandom number, and the first state vector by a random keystream sequence generation algorithm (PRGA);

and encrypting the plaintext data by using the key stream sequence to obtain encrypted data.

In an optional embodiment of this application, the generating, by the key scheduling algorithm KSA, the first pseudo random number, the second pseudo random number, and the first state vector includes:

generating a second state vector, and generating a temporary vector based on the key;

sequencing elements in the second state vector based on the second state vector and the temporary vector to obtain a first state vector; wherein a first pseudo-random number and a second pseudo-random number are generated in the process of ordering elements in the second state vector.

In an optional embodiment of the present application, the sorting, based on the second state vector and the temporary vector, elements in the second state vector to obtain a first state vector; wherein generating a first pseudo-random number and a second pseudo-random number in ordering elements in the second state vector comprises:

setting the values of the first variable parameter and the second variable parameter as 0;

judging whether the value of the first variable parameter is smaller than the length of the key;

if the value of the first variable parameter is smaller than the length of the key, taking the first variable parameter as index parameters of a first index pointer and a second index pointer, determining a first element in the second state vector based on the first index pointer and determining a second element in the temporary vector based on the second index pointer;

generating a pseudo-random number based on the first element and assigning the pseudo-random number to a third variable parameter;

generating a pseudo-random number based on the first element and the second element and assigning the pseudo-random number to the second variable parameter, and determining a third element in the second state vector by using the second variable parameter as an index parameter of a third index pointer and based on the third index pointer;

performing a swap operation on the first element and the third element in the second state vector, and generating a random integer assignment to a fourth variable parameter;

and updating the value of the first variable parameter according to the first step length, and circularly executing the operation of judging whether the value of the first variable parameter is smaller than the length of the secret key.

In an optional embodiment of the present application, the sorting, based on the second state vector and the temporary vector, elements in the second state vector to obtain a first state vector; wherein generating a first pseudo-random number and a second pseudo-random number during ordering of elements in the second state vector further comprises:

if the value of the first variable parameter is larger than or equal to the length of the key, assigning the value of the second variable parameter to a fifth variable parameter;

judging whether the value of the first variable parameter is smaller than the length of the second state vector;

if the value of the first variable parameter is smaller than the length of the second state vector, taking the first variable parameter as index parameters of a first index pointer and a second index pointer, determining a fourth element in the second state vector based on the first index pointer and determining a fifth element in the temporary vector based on the second index pointer;

generating a pseudo-random number based on the fourth element and assigning the pseudo-random number to a third variable parameter;

generating a pseudo-random number based on the fourth element and the fifth element and assigning the pseudo-random number to the second variable parameter, and determining a sixth element in the second state vector by using the second variable parameter as an index parameter of a third index pointer and based on the third index pointer;

performing an exchange operation on the fourth element and the sixth element in the second state vector, and generating a random integer assignment to a fourth variable parameter;

updating the value of the first variable parameter according to a first step length, and circularly executing the operation of judging whether the value of the first variable parameter is smaller than the length of the second state vector until the value of the first variable parameter is equal to the length of the second state vector;

and under the condition that the value of the first variable parameter is equal to the length of the second state vector, the value of the third variable parameter is used as a first pseudo-random number, the value of the fifth variable parameter is used as a second pseudo-random number, the value of the fourth variable parameter is used as a first random integer, and the second state vector is converted into the first state vector after the exchange operation is executed.

In an optional embodiment of the present application, the generating, by a random key stream sequence generation algorithm PRGA, a key stream sequence based on the first pseudo random number, the second pseudo random number, and the first state vector includes:

setting the value of a sixth variable parameter to 0, and assigning the first pseudo random number to a second variable parameter and assigning the second pseudo random number to the first variable parameter;

judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data;

if the value of the sixth variable parameter is smaller than the length of the plaintext data, updating the value of the first variable parameter according to a second step length;

taking the first variable parameter as an index parameter of a first index pointer, determining a seventh element in the second state vector based on the first index pointer, and generating a pseudo-random number based on the second variable parameter and the seventh element and assigning the pseudo-random number to the second variable parameter;

taking the second variable parameter as an index parameter of a second index pointer, determining an eighth element in the second state vector based on the second index pointer, generating a random integer based on a value of the fourth variable parameter and the eighth element, and assigning the random integer to the fourth variable parameter;

performing an exchange operation on the seventh element and the eighth element in the second state vector, and performing integer-modulo addition operation on the seventh element and the eighth element to obtain a first operation value;

carrying out integer mode addition operation on the values of the first operation value and the fourth variable parameter to obtain a second operation value;

taking the second operation value as an index parameter of a fourth index pointer, determining a target element in the second state vector based on the fourth index pointer, taking the target element as a kth element in a key stream sequence, wherein k is the sixth variable parameter;

and updating the value of the sixth variable parameter according to the first step length, and circularly executing the operation of judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data or not until the value of the sixth variable parameter is equal to the length of the plaintext data.

An embodiment of the present application further provides a data encryption apparatus, where the apparatus includes:

a first generation unit for generating a first pseudo random number, a second pseudo random number, and a first state vector by a key scheduling algorithm KSA;

a second generation unit configured to generate a keystream sequence based on the first pseudorandom number, the second pseudorandom number, and the first state vector through a random keystream sequence generation algorithm PRGA;

and the encryption unit is used for encrypting the plaintext data by using the key stream sequence to obtain encrypted data.

In an optional embodiment of the present application, the first generating unit is specifically configured to: generating a second state vector, and generating a temporary vector based on the key; sequencing elements in the second state vector based on the second state vector and the temporary vector to obtain a first state vector; wherein a first pseudo-random number and a second pseudo-random number are generated in the process of ordering elements in the second state vector.

In an optional embodiment of the present application, the first generating unit is further specifically configured to: setting the values of the first variable parameter and the second variable parameter as 0; judging whether the value of the first variable parameter is smaller than the length of the key; if the value of the first variable parameter is smaller than the length of the key, taking the first variable parameter as index parameters of a first index pointer and a second index pointer, and determining a first element in the second state vector based on the first index pointer and a second element in the temporary vector based on the second index pointer; generating a pseudo-random number based on the first element and assigning a third variable parameter; generating a pseudo-random number based on the first element and the second element and assigning the pseudo-random number to the second variable parameter, and determining a third element in the second state vector by using the second variable parameter as an index parameter of a third index pointer and based on the third index pointer; performing a swap operation on the first element and the third element in the second state vector, and generating a random integer assignment to a fourth variable parameter; and updating the value of the first variable parameter according to the first step length, and circularly executing the operation of judging whether the value of the first variable parameter is smaller than the length of the secret key.

In an optional embodiment of the present application, the first generating unit is further specifically configured to: if the value of the first variable parameter is larger than or equal to the length of the key, assigning the value of the second variable parameter to a fifth variable parameter; judging whether the value of the first variable parameter is smaller than the length of the second state vector; if the value of the first variable parameter is smaller than the length of the second state vector, taking the first variable parameter as index parameters of a first index pointer and a second index pointer, determining a fourth element in the second state vector based on the first index pointer and determining a fifth element in the temporary vector based on the second index pointer; generating a pseudo-random number based on the fourth element and assigning the pseudo-random number to a third variable parameter; generating a pseudo-random number based on the fourth element and the fifth element and assigning the pseudo-random number to the second variable parameter, and determining a sixth element in the second state vector by using the second variable parameter as an index parameter of a third index pointer and based on the third index pointer; performing an exchange operation on the fourth element and the sixth element in the second state vector, and generating a random integer assignment to a fourth variable parameter; updating the value of the first variable parameter according to a first step length, and circularly executing the operation of judging whether the value of the first variable parameter is smaller than the length of the second state vector until the value of the first variable parameter is equal to the length of the second state vector; and under the condition that the value of the first variable parameter is equal to the length of the second state vector, the value of the third variable parameter is used as a first pseudo-random number, the value of the fifth variable parameter is used as a second pseudo-random number, the value of the fourth variable parameter is used as a first random integer, and the second state vector is converted into the first state vector after the exchange operation is executed.

In an optional embodiment of the present application, the second generating unit is specifically configured to: setting the value of a sixth variable parameter to 0, and assigning the first pseudo random number to a second variable parameter and assigning the second pseudo random number to the first variable parameter; judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data; if the value of the sixth variable parameter is smaller than the length of the plaintext data, updating the value of the first variable parameter according to a second step length; taking the first variable parameter as an index parameter of a first index pointer, determining a seventh element in the second state vector based on the first index pointer, and generating a pseudo-random number based on the second variable parameter and the seventh element and assigning the pseudo-random number to the second variable parameter; taking the second variable parameter as an index parameter of a second index pointer, determining an eighth element in the second state vector based on the second index pointer, generating a random integer based on a value of the fourth variable parameter and the eighth element, and assigning the random integer to the fourth variable parameter; performing an exchange operation on the seventh element and the eighth element in the second state vector, and performing integer-modulo addition operation on the seventh element and the eighth element to obtain a first operation value; performing integer-mode addition operation on the values of the first operation value and the fourth variable parameter to obtain a second operation value; taking the second operation value as an index parameter of a fourth index pointer, determining a target element in the second state vector based on the fourth index pointer, taking the target element as a kth element in a key stream sequence, wherein k is the sixth variable parameter; and updating the value of the sixth variable parameter according to the first step length, and circularly executing the operation of judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data until the value of the sixth variable parameter is equal to the length of the plaintext data.

An embodiment of the present application provides an electronic device, including: the processor is used for calling and running the computer program stored in the memory to execute the data encryption method.

An embodiment of the present application provides a computer-readable storage medium, which is configured to store a computer program, where the computer program enables a computer to execute the data encryption method.

In the technical scheme of the embodiment of the application, a first pseudo-random number, a second pseudo-random number and a first state vector are generated through a key scheduling algorithm KSA; generating a keystream sequence based on the first pseudorandom number, the second pseudorandom number, and the first state vector by a random keystream sequence generation algorithm (PRGA); and encrypting the plaintext data by using the key stream sequence to obtain encrypted data. In this way, the first pseudo-random number and the second pseudo-random number generated in the operation by using the KSA algorithm in the RC4 algorithm can be respectively used as the initial value of the second variable parameter and the first variable parameter of the first state vector in the PRGA algorithm process, so that the randomness of the initial values of the first variable parameter and the second variable parameter in the PRGA algorithm process is effectively improved, and the security of data encryption is improved.

Drawings

Fig. 1 is a schematic flowchart of a data encryption method according to an embodiment of the present application;

fig. 2 is a flow chart for executing a KSA algorithm according to an embodiment of the present application;

fig. 3 is a flowchart for executing a PRGA algorithm according to an embodiment of the present disclosure;

FIG. 4 is a block diagram of an overall architecture of a system according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a pin connection between a main control chip and part of functional hardware according to an embodiment of the present disclosure;

fig. 6 is a layout diagram of a printed circuit board of a terminal node according to an embodiment of the present application;

fig. 7 is a schematic structural component diagram of a data encryption device according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a chip according to an embodiment of the present application.

Detailed Description

So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.

When designing a data encryption method, three methods are generally used: 1. the existing encryption method is directly used, for example, the application of the AES encryption algorithm to the wireless sensor node is researched; 2. the existing encryption method is improved, for example, the chaotic mapping system is used for improving the RC5 algorithm so as to improve the operation efficiency and safety of the RC 5; 3. a new set of encryption methods is designed for limited hardware resources. The encryption method used at the terminal node is mostly a lightweight encryption method improved based on the existing encryption method.

The traditional RC4 (i.e. Rivest Cipher 4) encryption algorithm is one of the common symmetric encryption algorithms, and has the advantages of fast encryption and decryption speed, simple key management, etc., but also causes a series of disadvantages of simple algorithm, limited key length, low encryption strength, etc. The conventional RC4 Algorithm mainly involves Key Scheduling Algorithm (KSA) and Pseudo-Random Key stream sequence Generation Algorithm (PRGA). In the KSA algorithm, an initial S box is an ordered sequence of 0-255, and after subsequent disorder processing, the S box sequence after the disorder processing has pseudo-randomness. However, in the PRGA algorithm, the initial values of the position pointer variable i and the pseudo random number j are always 0, and the step size is a fixed value, so that an attacker can easily know which element of the pseudo random S-box sequence after the out-of-order processing is the first byte of the key stream, and is vulnerable to attack. Moreover, the PRGA algorithm only generates a pseudo-random number through a variable j, so that the randomness of a finally generated key stream is not high, and the security of a key is easily threatened.

The technical scheme of the embodiment of the application is mainly that on the basis of a traditional RC4 encryption algorithm, a first pseudo-random number and a second pseudo-random number generated in the process of executing a KSA algorithm are stolen, random integers are continuously generated in the process of executing the KSA algorithm, the final value of the random integer is used as the input of the PRGA algorithm, the random integer is continuously generated based on the random integer finally generated by the KSA algorithm in the process of executing the PRGA algorithm, and elements of a key stream sequence are generated by utilizing the random integer.

Fig. 1 is a schematic flowchart of a data encryption method provided in an embodiment of the present application, and as shown in fig. 1, the data encryption method includes the following steps:

step 101: the first pseudo random number, the second pseudo random number and the first state vector are generated by the key scheduling algorithm KSA.

In an optional embodiment of this application, the generating, by the key scheduling algorithm KSA, a first pseudo random number, a second pseudo random number, and a first state vector includes:

Here, the RC4 algorithm includes a KSA algorithm and a PRGA algorithm, wherein the KSA algorithm is an initialization algorithm, the second state vector can be converted into the first state vector by executing the KSA algorithm, and the first pseudo random number and the second pseudo random number are generated during execution.

Specifically, during execution of the KSA algorithm, a second state vector (i.e., S) needs to be generated₂) Will S₂The middle elements are assigned values in ascending order from 0 to 255, i.e. S₂[0]＝00，S₂[1]＝1，…，S₂[255]255. Here, S is generated₂Is also called initializing S-boxes.

Except for generating S₂In addition, a temporary vector (i.e., T) needs to be generated based on the key sequence, where T is generated based on the key. Specifically, when T is generated, if the length of the key is 256, the value of the key is directly given to T; in the case where the key has a length m, which is an integer less than 256, the value of the key is assigned to the first m data of T, and the values of the key are cyclically reused to the remaining elements of T until all elements of T are assigned.

Based on S₂And T, to S₂Can obtain a first state vector (i.e., S)₁)，S₁And S₂Compared with the same permutation combination of 8 bits from 0 to 255, only relative toS₂，S₁The position of the middle element is changed. Wherein, in the pair S₂Generates a first pseudo-random number and a second pseudo-random number during the sequencing of the elements in (A) and finally generates (S)₁。

Fig. 2 is a flow chart for executing the KSA algorithm according to an embodiment of the present application. As shown in fig. 2, in the embodiment of the present application, in order not to increase the time complexity of the KSA algorithm, the key length is used as a demarcation point, the main loop task of the KSA algorithm is divided into two loop tasks, a first pseudo random number and a second pseudo random number are determined during the execution of the two loop tasks, and the second state vector is scrambled after the loop is completed, so as to generate a first state vector. In addition, the KSA algorithm execution process continuously generates random integers, and a final random integer is generated as an input of the PRGA algorithm after the KSA algorithm execution is finished.

Specifically, as shown in fig. 2, the embodiment of the present application takes the first variable parameter (i.e., i) as S₂Can determine S based on i₂One element (i.e., S)₂[i]) The second variable parameter (i.e., j) is taken as S₂Can also determine S based on j₂One element (i.e., S)₂[j]) Furthermore, one element in T can also be determined based on i (i.e., T [ i;)])。

In the embodiment of the application, the initial values of i and j are defined as zero, and when the value of i is judged to be smaller than the key length, S is used as the basis₂The first element (i.e. S) in (1)₂[i]) A pseudo-random number is generated and assigned to the third variable parameter (i.e., i)_temp) (ii) a Based on S₂[i]And the second element in T (i.e. T [ i ]]) Generating a pseudo-random number and assigning the pseudo-random number to j, wherein S can be determined by the value of j₂The third element (i.e. S) in (1)₂[j]) By exchanging S₂[i]And S₂[j]Can disorder the original S₂Of (1). As an alternative embodiment, for the S-based₂[i]A pseudo-random number is generated and assigned to the third variable parameter (i.e., i)_temp) Specifically, the operation |256 × sin (S) may be performed by₂[i]) The generated result is given to i_temp。

In addition, S is executed₂[i]And S₂[j]After the exchange, an operation of generating a random integer is also required to be executed, and a value is assigned to the fourth variable parameter. Here, the specific method for generating the random integer may be to generate a random integer by generating a secret random integer, and then assign the random integer to the fourth variable parameter.

By performing a pair S₂[i]And S₂[j]After the sequential exchange operation, the value of i needs to be updated according to the first step length, and the operation of judging whether the value of i is smaller than the key length is executed in a circulating manner until the value of i is equal to the key length. Here, the first step size may be set to 1.

In an optional embodiment of the present application, the sorting, based on the second state vector and the temporary vector, elements in the second state vector to obtain a first state vector; wherein generating a first pseudo-random number and a second pseudo-random number in ordering elements in the second state vector further comprises:

Specifically, as shown in fig. 2, when i is updated by the first step length until the value of i is equal to the length of the key, the final value of j is assigned to the fifth variable parameter (i.e., j_temp) When the value of i is less than 256, based on S₂[i]Generate a pseudo-random number and continue assigning value to i_temp(ii) a Continued on the basis of S₂[i]And T [ i ]]Generating a pseudo-random number and assigning the pseudo-random number to j, and determining S according to the value of j₂The third element (i.e. S) in (1)₂[j]) By exchanging S₂[i]And S₂[j]Continue to execute the scrambling S₂The operation of the element in (1). Likewise, for S-based₂[i]A pseudo-random number is generated and assigned to the third variable parameter (i.e., i)_temp) It is still possible to perform the arithmetic |256 × sin (S)₂[i]) The generated result is given to i_tempAnd (4) determining. In execution of S₂[i]And S₂[j]After the exchange, the operation of generating the random integer still needs to be executed, and the fourth variable parameter is assigned. Here, the specific method for generating the random integer may still generate a random integer by generating the secret random integer, and then assign the random integer to the fourth variable parameter.

By performing a pair S₂[i]And S₂[j]After the sequential switching operation, the value of i needs to be updated according to the first step length, and the cyclic execution judges whether the value of i is smaller than S₂Until the value of i equals S₂Length of (d). In fig. 2, the first step length may be set to 1, or may be set to other values by the user as needed.

Here, when the value of i is equal to S₂The first and second pseudo random numbers and the first state vector may be finally determined. Specifically, when the value of i is equal to S₂Length of (c), i to be finally generated_tempIs taken as a first pseudo random number, j_tempIs taken as a second pseudo random number, S₂The element in (1) is transformed into S after performing the exchange operation₁。

By executing the KSA algorithm, it is possible to determine a first pseudo random number, a second pseudo random number and a first state vector, to provide initial first state variables and second state variables for executing a subsequent PRGA algorithm, and to scramble the second state vector to the first state vector.

Step 102: generating, by a random key stream sequence generation algorithm PRGA, a key stream sequence based on the first pseudo random number, the second pseudo random number, and the first state vector.

performing integer-mode addition operation on the values of the first operation value and the fourth variable parameter to obtain a second operation value;

Specifically, fig. 3 is a flowchart for executing a PRGA algorithm according to an embodiment of the present disclosure, and as shown in fig. 3, in the embodiment of the present disclosure, a sixth variable parameter (i.e., count) is first introduced as an index pointer of a key stream sequence, and i is used as_tempAssign j to j, assign j_tempAssigning to i, updating i by a stride coefficient 3 when the value of the sixth variable parameter is smaller than the length of the plaintext, wherein S can be determined based on i by taking i as the index parameter of the first index pointer₂Is also an element of S₁Element of (i.e. S)₁[i]) Based on j and S₁[i]A pseudo-random number is generated and assigned to j. After j is determined, S can be determined based on j, taking j as the index parameter of the second index pointer₂Is also an element of S₁Element (i.e. S) in (C)₁[j]). Then, based on the fourth variable parameter and S₁[j]Can generate a random integer again, and integrate the random integerThe value of the number continues to be assigned to the fourth variable parameter. And then executes S₁[i]And S₁[j]And for S₁[i]And S₁[j]Executing integer modular addition operation, continuously carrying out integer modular addition operation on the first operation value obtained after operation and the value of the fourth variable parameter to obtain a second operation value, and determining S based on the second operation value₁And assigning the element to the kth element of the key stream sequence, wherein the value of k is the same as the count. Here, it should be noted that, during the loop process of executing the PRGA algorithm, the initial value of the fourth variable parameter is a random integer finally generated by the KSA algorithm process (i.e., the fourth variable parameter finally generated by the KSA algorithm). Based on the fourth variable parameter and S₁[j]The process of generating a random integer again can still be implemented by generating a secret random integer, and continuously assigning the value of the generated random integer to the fourth variable parameter.

And updating the value of the count according to the first step length, and circularly executing the operation of judging whether the value of the count is smaller than the length of the plaintext data until the value of the count is equal to the length of the plaintext data.

By executing the step, the first pseudo random number and the second pseudo random number generated by the KSA algorithm process can be respectively used as initial values of a second variable parameter and a first variable parameter when the PRGA algorithm starts to be executed, random integers are introduced in the PRGA algorithm executing process, and elements of the key stream sequence are determined by the random integers in the PRGA algorithm executing process. Thereby further improving the randomness of the keystream sequence.

Step 103: and encrypting the plaintext data by using the key stream sequence to obtain encrypted data.

Specifically, after the key stream sequence is generated, the encrypted data can be generated by performing an exclusive or operation or other related operations on the key stream sequence and the plaintext data. Correspondingly, after the encrypted data is obtained, the encrypted data and the key stream sequence are subjected to exclusive or operation or other corresponding related operations, so that the encrypted data can be decrypted, and plaintext data is obtained.

According to the technical scheme of the embodiment of the application, the first pseudo random number and the second pseudo random number are determined in the process of executing the KSA algorithm by adopting a pseudo random number stealing method, and the first pseudo random number and the second pseudo random number generated in the process of executing the KSA algorithm are respectively used as the initial values of the second variable parameter and the first variable parameter when the PRGA algorithm starts to execute, so that the randomness of the initial values adopted in the process of executing the PRGA algorithm is effectively improved, and the security of data encryption is ensured. In addition, because the pseudorandom nature of the key stream sequence generated by adopting the KSA algorithm is low, the random integers are continuously generated when the KSA algorithm is executed, the value of the finally generated random integer is used as the initial value of the random integer generated by the PRGA algorithm, the random integer finally generated by executing the KSA algorithm is used as the initial value of the random integer of the PRGA algorithm to continuously generate the random integer in the process of executing the PRGA algorithm, and the element for generating the key stream sequence is determined based on the generated random integer, so that the randomness of the key stream sequence is effectively improved, and the reliability of data encryption and transmission is improved.

The technical scheme of the embodiment of the application can be used for various application scenes in a communication system, wherein data needs to be encrypted. The embodiment of the present application takes an application environment of Narrowband Internet of Things (NB-IoT, Narrowband Internet of Things) as an example to illustrate the technical solution of the embodiment of the present application. The application of NB-IoT is still in the early stage, but after large-scale deployment, how to ensure the secure transmission of data between the controller and the device terminal in NB-IoT becomes increasingly important. The adoption of a proper encryption method when data is transmitted in the internet of things equipment is a common means for ensuring the safe transmission of the data.

In order to verify the security of the data encryption method in the embodiment of the present application in the data transmission process, a set of NB-IoT hardware platform is first built in the embodiment of the present application, and fig. 4 is a diagram of the overall architecture of the system provided in the embodiment of the present application. In the process of designing the terminal node of the hardware platform, the embodiment of the application needs to consider whether the limitations of the capability and the cost of the processor can meet the requirements. The terminal node needs to implement basic functions such as environmental data acquisition, control of external devices, conversion of communication formats, network access, forwarding and processing of data, and the terminal node needs to have a hardware system with superior performance when implementing the functions. In the embodiment of the application, when a hardware system of a terminal node is designed, in terms of the type selection of a CPU, an MCU of an MKL36Z64VLH4 (KL 36 for short) of a Cortex-M4 architecture is used as a main control chip of an NB-IoT terminal node. The chip has high main frequency, large cache and rich external interfaces, and can fully meet the requirements of NB-IoT terminal nodes.

The communication module that this application embodiment chose for use is BC95, and this communication module wide application has extensive peripheral hardware interface and easily extension in fields such as wisdom city, security protection and intelligent house. The characteristic parameters of the BC95 communication module part are as follows:

(1) communication frequency band: BC 95-B8: 900 megahertz (MHz); BC 95-B5: 850 MHz; BC 95-B20: 800 MHz.

(2) Working temperature: minus 40 ℃ to plus 85 ℃.

(3) Data transmission rate: 100 bit rate (bps) < bit rate <100kbps

(4) Power consumption: a sleep mode: power consumption <10 microamperes (μ a), operating mode: power consumption <6 milliamps (mA).

(5) Wireless transmission power: 23 decibel-milliwatt (dBm) ± 2 decibel (dB).

The master control chip KL36 and the communication module BC95 are integrated on a PCB backplane. The expansion bottom plate also comprises interfaces such as a contact pin, a display screen, a Touch Sensing module (TSI), a serial port and a writer. The master control chip KL36 realizes control of each external device through the expansion backplane, and further realizes basic functions of data acquisition, data forwarding and processing and the like. Fig. 5 is a schematic diagram of pin connection between a main control chip and a part of functional hardware according to an embodiment of the present disclosure, where the functional hardware includes a power module, a Universal Asynchronous Receiver/Transmitter (UART), a Serial Debug (SWD) interface, a capacitor, and an LED tri-color lamp.

Fig. 6 is a layout diagram of a Printed Circuit Board (PCB) layout of a terminal node according to an embodiment of the present disclosure. In the process of distributing the PCB to the terminal node, the electrical characteristics, the welding difficulty and the reasonability of wiring among the electronic components need to be considered, and the drawing of the PCB of the controller of the terminal node designed in the embodiment of the application needs to pay attention to the following aspects:

(1) the master control chip KL36 should be arranged in the position of the whole PCB relative to the center, so that other peripheral interfaces can be conveniently arranged at the edge of the PCB, and the plugging expansion is convenient.

(2) The NB-IoT communication chip BC95 is a communication chip and should be placed at a position where interference is low. In addition, isolation of BC95 is required to ensure no interference.

(3) Unused ports of the main control chip need to be reserved and led out, so that later expansion is facilitated.

Table 1 is a test result table of security tests performed on the conventional RC4 encryption method and the data encryption method provided in the embodiment of the present application, where the security tests for both methods are performed based on the NB-IoT hardware platform provided in the embodiment of the present application.

TABLE 1

In testing the security of data encryption, randomness test is an important means for evaluating the security of a sequence cipher, and the method detects whether the sequence cipher is random by a probability statistics method. The Special Publication 800-22 test package, available from the National Institute of Standards and Technology (NIST), is a commonly used sequence cipher keystream randomness test kit, and embodiments of the present application perform randomness tests and comparisons on keystream sequences generated by a conventional RC4 encryption method and a data encryption method of embodiments of the present application, respectively, using a NIST randomness detection method. In the testing process, the length of the key stream is set to be 500KB and kept unchanged, then the traditional RC4 encryption method and the data encryption method of the embodiment of the application are divided into 50 groups according to the key length, then 50 groups of key sequences are generated, and the average value of the test results of the 50 groups of key sequences is used as the final test result. The test results for each item of NIST randomness test are stored in an assumed probability (i.e., P-value), with a higher value of P-value indicating better randomness for the item of test results. The test procedure sets the significance level to be 0.01, and the average result P-value of the security of the conventional RC4 encryption algorithm and the data encryption method of the embodiment of the present application, which are finally tested using the NIST randomness detection method, is shown in table 1 by adjusting parameters.

As can be seen from the test results of table 1, the P-value values of 14 test items of the NIST randomness test method are all greater than the significant level α, indicating that both the conventional RC4 algorithm and the data encryption method of the embodiment of the present application can pass the randomness test. In the test results of the data encryption method in the embodiment of the application, the P-value values of the three indexes of the most important frequency test, the run detection, the global general statistical test and the like have better test results compared with the traditional RC4 algorithm, and meanwhile, the results of the other 5 tests (approximate entropy detection, accumulation and test-forward, accumulation and test-reverse, linear complexity detection and serial test) are higher than those of the traditional RC4 encryption method. Therefore, the randomness of the keystream sequence finally generated by the data encryption method of the embodiment of the application is higher than that of the keystream sequence generated by the traditional RC4 encryption method. The data encryption method of the embodiment of the application is verified to have higher security from the perspective of cryptostatistics.

An embodiment of the present application further provides a data encryption device, and fig. 7 is a schematic structural composition diagram of the data encryption device provided in the embodiment of the present application, and as shown in fig. 7, the device includes:

a first generating unit 701 configured to generate a first pseudo random number, a second pseudo random number, and a first state vector by using a key scheduling algorithm KSA;

a second generating unit 702 configured to generate a keystream sequence based on the first pseudorandom number, the second pseudorandom number, and the first state vector through a random keystream sequence generation algorithm PRGA;

an encrypting unit 703 is configured to encrypt plaintext data by using the key stream sequence to obtain encrypted data.

In an optional embodiment of the present application, the first generating unit 701 is specifically configured to: generating a second state vector, and generating a temporary vector based on the key; sequencing elements in the second state vector based on the second state vector and the temporary vector to obtain a first state vector; wherein a first pseudo-random number and a second pseudo-random number are generated in the process of ordering elements in the second state vector.

In an optional embodiment of the present application, the first generating unit 701 is further specifically configured to: setting the values of the first variable parameter and the second variable parameter as 0; judging whether the value of the first variable parameter is smaller than the length of the key or not; if the value of the first variable parameter is smaller than the length of the key, taking the first variable parameter as index parameters of a first index pointer and a second index pointer, determining a first element in the second state vector based on the first index pointer and determining a second element in the temporary vector based on the second index pointer; generating a pseudo-random number based on the first element and assigning the pseudo-random number to a third variable parameter; generating a pseudo-random number based on the first element and the second element and assigning the pseudo-random number to the second variable parameter, and determining a third element in the second state vector by using the second variable parameter as an index parameter of a third index pointer and based on the third index pointer; performing a swap operation on the first element and the third element in the second state vector, and generating a random integer assignment to a fourth variable parameter; and updating the value of the first variable parameter according to the first step length, and circularly executing the operation of judging whether the value of the first variable parameter is smaller than the length of the secret key.

In an optional embodiment of the present application, the first generating unit 701 is further specifically configured to: if the value of the first variable parameter is larger than or equal to the length of the key, assigning the value of the second variable parameter to a fifth variable parameter; judging whether the value of the first variable parameter is smaller than the length of the second state vector; if the value of the first variable parameter is smaller than the length of the second state vector, taking the first variable parameter as index parameters of a first index pointer and a second index pointer, determining a fourth element in the second state vector based on the first index pointer and determining a fifth element in the temporary vector based on the second index pointer; generating a pseudo-random number based on the fourth element and assigning a third variable parameter; generating a pseudo-random number based on the fourth element and the fifth element and assigning the pseudo-random number to the second variable parameter, and determining a sixth element in the second state vector by using the second variable parameter as an index parameter of a third index pointer and based on the third index pointer; performing an exchange operation on the fourth element and the sixth element in the second state vector, and generating a random integer assignment to a fourth variable parameter; updating the value of the first variable parameter according to a first step length, and circularly executing the operation of judging whether the value of the first variable parameter is smaller than the length of the second state vector until the value of the first variable parameter is equal to the length of the second state vector; and under the condition that the value of the first variable parameter is equal to the length of the second state vector, the value of the third variable parameter is used as a first pseudo-random number, the value of the fifth variable parameter is used as a second pseudo-random number, the value of the fourth variable parameter is used as a first random integer, and the second state vector is converted into the first state vector after the exchange operation is executed.

In an optional embodiment of the present application, the second generating unit 702 is specifically configured to: setting the value of a sixth variable parameter to 0, and assigning the first pseudo random number to a second variable parameter and assigning the second pseudo random number to the first variable parameter; judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data or not; if the value of the sixth variable parameter is smaller than the length of the plaintext data, updating the value of the first variable parameter according to a second step length; taking the first variable parameter as an index parameter of a first index pointer, determining a seventh element in the second state vector based on the first index pointer, and generating a pseudo-random number based on the second variable parameter and the seventh element and assigning the pseudo-random number to the second variable parameter; taking the second variable parameter as an index parameter of a second index pointer, determining an eighth element in the second state vector based on the second index pointer, generating a random integer based on a value of the fourth variable parameter and the eighth element, and assigning the random integer to the fourth variable parameter; performing an exchange operation on the seventh element and the eighth element in the second state vector, and performing integer-modulo addition operation on the seventh element and the eighth element to obtain a first operation value; performing integer-mode addition operation on the values of the first operation value and the fourth variable parameter to obtain a second operation value; taking the second operation value as an index parameter of a fourth index pointer, determining a target element in the second state vector based on the fourth index pointer, taking the target element as a kth element in a key stream sequence, wherein k is the sixth variable parameter; and updating the value of the sixth variable parameter according to the first step length, and circularly executing the operation of judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data until the value of the sixth variable parameter is equal to the length of the plaintext data.

It will be appreciated by those skilled in the art that the functions implemented by the units in the data encryption apparatus shown in fig. 7 can be understood with reference to the foregoing description of the data encryption method. The functions of the units in the data encryption device shown in fig. 7 may be implemented by a program running on a processor, or may be implemented by specific logic circuits.

Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device may be a server, the electronic device includes the data encryption apparatus shown in fig. 8, the electronic device 800 shown in fig. 8 includes a processor 810, and the processor 810 may call and execute a computer program from a memory to implement the method in the embodiment of the present application.

Optionally, as shown in fig. 8, the electronic device 800 may also include a memory 820. From the memory 820, the processor 810 may call and run a computer program to implement the method in the embodiment of the present application.

The memory 820 may be a separate device from the processor 810 or may be integrated into the processor 810.

Optionally, as shown in fig. 8, the electronic device 800 may further include a transceiver 830, and the processor 810 may control the transceiver 830 to communicate with other devices, and specifically, may transmit information or data to the other devices or receive information or data transmitted by the other devices.

The transceiver 830 may include a transmitter and a receiver, among others. The transceiver 830 may further include antennas, and the number of antennas may be one or more.

Optionally, the electronic device 800 may specifically be a network device in the embodiment of the present application, and the electronic device 800 may implement a corresponding process implemented by the network device in each method in the embodiment of the present application, which is not described herein again for brevity.

Optionally, the electronic device 800 may specifically be a mobile terminal/terminal device according to this embodiment, and the electronic device 800 may implement a corresponding process implemented by the mobile terminal/terminal device in each method according to this embodiment, which is not described herein again for brevity.

Fig. 9 is a schematic structural diagram of a chip of an embodiment of the present application. The chip 900 shown in fig. 9 includes a processor 910, and the processor 910 can call and run a computer program from a memory to implement the method in the embodiment of the present application.

Optionally, as shown in fig. 9, the chip 900 may further include a memory 920. From the memory 920, the processor 910 can call and run a computer program to implement the method in the embodiment of the present application.

The memory 920 may be a separate device from the processor 910, or may be integrated in the processor 910.

Optionally, the chip 900 may further comprise an input interface 930. The processor 910 may control the input interface 930 to communicate with other devices or chips, and in particular, may obtain information or data transmitted by other devices or chips.

Optionally, the chip 900 may further include an output interface 940. The processor 910 may control the output interface 940 to communicate with other devices or chips, and in particular, may output information or data to the other devices or chips.

Optionally, the chip may be applied to the network device in the embodiment of the present application, and the chip may implement the corresponding process implemented by the network device in each method in the embodiment of the present application, and for brevity, details are not described here again.

Optionally, the chip may be applied to the mobile terminal/terminal device in the embodiment of the present application, and the chip may implement the corresponding process implemented by the mobile terminal/terminal device in each method in the embodiment of the present application, and for brevity, no further description is given here.

It should be understood that the chips mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip or a system-on-chip, etc.

It should be understood that the processor of the embodiments of the present application may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method embodiments may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The Processor may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

It will be appreciated that the memory in the embodiments of the subject application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of example, but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (DDR SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchronous link SDRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

It should be understood that the above memories are exemplary but not limiting illustrations, for example, the memories in the embodiments of the present application may also be Static Random Access Memory (SRAM), dynamic random access memory (dynamic RAM, DRAM), Synchronous Dynamic Random Access Memory (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (enhanced SDRAM, ESDRAM), Synchronous Link DRAM (SLDRAM), Direct Rambus RAM (DR RAM), and the like. That is, the memory in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.

The embodiment of the application also provides a computer readable storage medium for storing the computer program.

Optionally, the computer-readable storage medium may be applied to the network device in the embodiment of the present application, and the computer program enables the computer to execute the corresponding process implemented by the network device in each method in the embodiment of the present application, which is not described herein again for brevity.

Optionally, the computer-readable storage medium may be applied to the mobile terminal/terminal device in the embodiment of the present application, and the computer program enables the computer to execute the corresponding process implemented by the mobile terminal/terminal device in each method in the embodiment of the present application, which is not described herein again for brevity.

Embodiments of the present application also provide a computer program product comprising computer program instructions.

Optionally, the computer program product may be applied to the network device in the embodiment of the present application, and the computer program instruction enables the computer to execute a corresponding process implemented by the network device in each method in the embodiment of the present application, which is not described herein again for brevity.

Optionally, the computer program product may be applied to the mobile terminal/terminal device in the embodiment of the present application, and the computer program instructions enable the computer to execute the corresponding processes implemented by the mobile terminal/terminal device in the methods in the embodiment of the present application, which are not described herein again for brevity.

The embodiment of the application also provides a computer program.

Optionally, the computer program may be applied to the network device in the embodiment of the present application, and when the computer program runs on a computer, the computer is enabled to execute the corresponding process implemented by the network device in each method in the embodiment of the present application, and for brevity, details are not described here again.

Optionally, the computer program may be applied to the mobile terminal/terminal device in the embodiment of the present application, and when the computer program runs on a computer, the computer is enabled to execute the corresponding process implemented by the mobile terminal/terminal device in each method in the embodiment of the present application, which is not described herein again for brevity.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for data encryption, the method comprising:

sequencing elements in the second state vector based on the second state vector and the temporary vector to obtain a first state vector; wherein a first pseudo random number and a second pseudo random number are generated during ordering of elements in the second state vector;

encrypting plaintext data by using the key stream sequence to obtain encrypted data;

wherein the generating a keystream sequence based on the first pseudorandom number, the second pseudorandom number, and the first state vector by a random keystream sequence generation algorithm, PRGA, comprises:

judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data or not;

taking the second variable parameter as an index parameter of a second index pointer, determining an eighth element in the second state vector based on the second index pointer, generating a random integer based on a value of a fourth variable parameter and the eighth element, and assigning the random integer to the fourth variable parameter;

and updating the value of the sixth variable parameter according to the first step length, and circularly executing the operation of judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data until the value of the sixth variable parameter is equal to the length of the plaintext data.

2. The method of claim 1, wherein the sorting of the elements in the second state vector based on the second state vector and the temporary vector results in a first state vector; wherein generating a first pseudo-random number and a second pseudo-random number in ordering elements in the second state vector comprises:

3. The method of claim 2, wherein the sorting of the elements in the second state vector based on the second state vector and the temporary vector results in a first state vector; wherein generating a first pseudo-random number and a second pseudo-random number in ordering elements in the second state vector further comprises:

and under the condition that the value of the first variable parameter is equal to the length of the second state vector, the value of the third variable parameter is used as a first pseudo-random number, the value of the fifth variable parameter is used as a second pseudo-random number, and the second state vector is converted into the first state vector after the exchange operation is executed.

4. An apparatus for encrypting data, the apparatus comprising:

a first generation unit configured to generate a second state vector and a temporary vector based on the key; sequencing elements in the second state vector based on the second state vector and the temporary vector to obtain a first state vector; wherein a first pseudo random number and a second pseudo random number are generated during ordering of elements in the second state vector;

the encryption unit is used for encrypting plaintext data by using the key stream sequence to obtain encrypted data;

wherein the second generating unit is specifically configured to: setting the value of a sixth variable parameter to 0, and assigning the first pseudo random number to a second variable parameter and assigning the second pseudo random number to the first variable parameter; judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data; if the value of the sixth variable parameter is smaller than the length of the plaintext data, updating the value of the first variable parameter according to a second step length; taking the first variable parameter as an index parameter of a first index pointer, determining a seventh element in the second state vector based on the first index pointer, and generating a pseudo-random number based on the second variable parameter and the seventh element and assigning the pseudo-random number to the second variable parameter; taking the second variable parameter as an index parameter of a second index pointer, determining an eighth element in the second state vector based on the second index pointer, generating a random integer based on a value of a fourth variable parameter and the eighth element, and assigning the random integer to the fourth variable parameter; performing an exchange operation on the seventh element and the eighth element in the second state vector, and performing integer-modulo addition operation on the seventh element and the eighth element to obtain a first operation value; performing integer-mode addition operation on the values of the first operation value and the fourth variable parameter to obtain a second operation value; taking the second operation value as an index parameter of a fourth index pointer, determining a target element in the second state vector based on the fourth index pointer, taking the target element as a kth element in a key stream sequence, wherein k is the sixth variable parameter; and updating the value of the sixth variable parameter according to the first step length, and circularly executing the operation of judging whether the value of the sixth variable parameter is smaller than the length of the plaintext data or not until the value of the sixth variable parameter is equal to the length of the plaintext data.

5. The apparatus of claim 4, wherein the first generating unit is further specifically configured to: setting the values of the first variable parameter and the second variable parameter as 0; judging whether the value of the first variable parameter is smaller than the length of the key; if the value of the first variable parameter is smaller than the length of the key, taking the first variable parameter as index parameters of a first index pointer and a second index pointer, determining a first element in the second state vector based on the first index pointer and determining a second element in the temporary vector based on the second index pointer; generating a pseudo-random number based on the first element and assigning the pseudo-random number to a third variable parameter; generating a pseudo-random number based on the first element and the second element and assigning the pseudo-random number to the second variable parameter, and determining a third element in the second state vector by using the second variable parameter as an index parameter of a third index pointer and based on the third index pointer; performing a swap operation on the first element and the third element in the second state vector, and generating a random integer assignment to a fourth variable parameter; and updating the value of the first variable parameter according to the first step length, and circularly executing the operation of judging whether the value of the first variable parameter is smaller than the length of the secret key.

6. The apparatus of claim 5, wherein the first generating unit is further specifically configured to: if the value of the first variable parameter is larger than or equal to the length of the key, assigning the value of the second variable parameter to a fifth variable parameter; judging whether the value of the first variable parameter is smaller than the length of the second state vector; if the value of the first variable parameter is smaller than the length of the second state vector, taking the first variable parameter as index parameters of a first index pointer and a second index pointer, determining a fourth element in the second state vector based on the first index pointer and determining a fifth element in the temporary vector based on the second index pointer; generating a pseudo-random number based on the fourth element and assigning the pseudo-random number to a third variable parameter; generating a pseudo-random number based on the fourth element and the fifth element and assigning the pseudo-random number to the second variable parameter, and determining a sixth element in the second state vector by using the second variable parameter as an index parameter of a third index pointer and based on the third index pointer; performing an exchange operation on the fourth element and the sixth element in the second state vector, and generating a random integer assignment to a fourth variable parameter; updating the value of the first variable parameter according to a first step length, and circularly executing the operation of judging whether the value of the first variable parameter is smaller than the length of the second state vector until the value of the first variable parameter is equal to the length of the second state vector; and under the condition that the value of the first variable parameter is equal to the length of the second state vector, the value of the third variable parameter is used as a first pseudo-random number, the value of the fifth variable parameter is used as a second pseudo-random number, the value of the fourth variable parameter is used as a first random integer, and the second state vector is converted into the first state vector after the exchange operation is executed.

7. An electronic device, comprising: a processor and a memory for storing a computer program, the processor being configured to invoke and execute the computer program stored in the memory to perform the method of any of claims 1 to 3.

8. A computer-readable storage medium for storing a computer program which causes a computer to perform the method of any one of claims 1 to 3.