CN113271075B - Automatic gain control device and method based on transmit-receive time division multiplexing - Google Patents
Automatic gain control device and method based on transmit-receive time division multiplexing Download PDFInfo
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Abstract
The application provides a rapid automatic gain control device and a method based on time division multiplexing of receiving and transmitting, the device comprises: the device comprises a gain adjusting circuit, an ADC module, a power statistics module, a state machine, a delay circuit, an automatic gain control circuit, a gain selection circuit and a gain latch circuit; the output end of the gain adjusting circuit is connected with the input end of the ADC module, the output end of the ADC module is connected with the input end of the power statistics module, the first output end of the power statistics module is connected with the first input end of the state machine, the second output end of the power statistics module is connected with the input end of the automatic gain control circuit, the output end of the delay circuit is connected with the first input end of the gain selection circuit, the output end of the automatic gain control circuit is connected with the second input end of the gain selection circuit, the port of the gain latch circuit is connected with the third input end of the gain selection circuit, and the output end of the gain selection circuit is connected with the first input end of the gain adjusting circuit.
Description
Technical Field
The present invention relates to the field of wireless communication technologies, and in particular, to an automatic gain control apparatus and method based on transmit-receive time division multiplexing.
Background
In the process of signal transmission, due to long distance or large loss of transmission medium, attenuation exists, and Automatic Gain Control (AGC) needs to be added on a receiving channel. The traditional control circuit judges the power or the number of peak values after ADC output by statistics, and then adjusts the receiving gain, but because the receiving circuit is closed in the sending stage, AGC still works, the gain is pushed to the maximum, and the gain returns to the ideal gain after being adjusted for a long time when entering the receiving state next time. Therefore, there is a need for a mechanism to ensure that the gain is locked quickly upon re-entering the receiving state.
At present, in the prior art, a method of starting AGC after TDMA signal pilot frequency is counted and adopting an initial value when AGC is not started is adopted, or a method of setting gain to be maximum and then counting power to reduce is adopted. The former has the disadvantage that AGC may not be started at all once in a place where the signal is not ideal, and the latter has the disadvantage that the convergence speed is slow due to the need of reducing from the maximum gain value to the minimum gain value in a large signal scene, which is not favorable for a fast transceiving switching scene.
Disclosure of Invention
The present application is directed to provide an automatic gain control apparatus and method based on transmit-receive time division multiplexing, so as to effectively overcome the technical defect of slow gain convergence speed in the prior art during transmit-receive switching.
In a first aspect, an embodiment of the present application provides an automatic gain control apparatus based on time division multiplexing for transceiving, where the apparatus includes: the device comprises a gain adjusting circuit, an ADC module, a power statistics module, a state machine, a delay circuit, an automatic gain control circuit, a gain selection circuit and a gain latch circuit; the output end of the gain adjusting circuit is connected with the input end of the ADC module, the output end of the ADC module is connected with the input end of the power statistics module, the first output end of the power statistics module is connected with the first input end of the state machine, the second output end of the power statistics module is connected with the input end of the automatic gain control circuit, the second input end of the state machine is connected with an input receiving and transmitting signal, the output end of the state machine is connected with the input end of the delay circuit, the output end of the delay circuit is connected with the first input end of the gain selecting circuit, the output end of the automatic gain control circuit is connected with the second input end of the gain selecting circuit, a port of the gain latching circuit is connected with the third input end of the gain selecting circuit for bidirectional transmission, the output end of the gain selecting circuit is connected with the first input end of the gain adjusting circuit, and the second input end of the gain adjusting circuit is externally connected with an analog input signal.
With reference to the first aspect, in a first possible implementation manner, the delay circuit includes: the circuit comprises a first trigger, a second trigger, an exclusive-OR logic gate, a counter and a third trigger; the input end of the first trigger is connected with the output signal of the output end of the state machine, the output end of the first trigger is connected with the input end of the second trigger, the first input end of the XOR logic gate is connected with the output end of the first trigger, the second input end of the XOR logic gate is connected with the output end of the second trigger, the output end of the XOR logic gate is connected with the input end of the counter, the output end of the counter is connected with the first input end of the third trigger, the output signal of the output end of the state machine is connected with the second input end of the third trigger, and the output end of the third trigger outputs a selection signal.
With reference to the first aspect, in a second possible implementation manner, a gain latch circuit includes: the fourth trigger, the subtracter, the comparator and the fifth trigger; the input end of the fourth trigger is connected with the first output signal of the automatic gain control circuit, the output end of the fourth trigger is connected with the first input end of the subtracter, the first output signal of the automatic gain control circuit is connected with the second input end of the subtracter, the output end of the subtracter is connected with the first input end of the comparator, the second input end of the comparator is connected with a latch threshold signal with a first preset threshold, the output end of the comparator is connected with the first input end of the fifth trigger, the second input end of the fifth trigger is connected with the output end of the fourth trigger, and the output end of the fifth trigger is connected with the gain selection circuit.
In a second aspect, an embodiment of the present application provides a method for automatic gain control based on transmit-receive time division multiplexing, which is applied to an automatic gain control device based on transmit-receive time division multiplexing in the first aspect and any possible implementation manner in combination with the first aspect, and the method includes: judging whether the current selection signal is in an effective state; if the judgment result is yes, the gain selection circuit inputs the first output signal of the automatic gain control circuit to the gain adjustment circuit for gain control; if the judgment result is negative, the gain selection circuit inputs a second output signal of the selective gain latch circuit to the gain adjustment circuit for gain control, wherein the second output signal is an automatic gain control signal which is latched when the gain is stable and unchanged.
With reference to the second aspect, in a first possible implementation manner, the determining whether the current selection signal is in an active state includes: judging whether the receiving and transmitting signal is in a high level state representing a receiving state, if so, enabling the selection signal through a delay circuit to obtain the selection signal in an effective state; if not, the selection signal in the invalid state is obtained through the delay circuit.
With reference to the second aspect, in a second possible implementation manner, the determining whether the current selection signal is in an active state further includes: and judging whether an instantaneous power signal is smaller than a second preset threshold value or not based on the power statistical module, and if so, processing the current signal into a selection signal in an invalid state through a delay circuit.
With reference to the second aspect, in a third possible implementation manner, before determining whether the current selection signal is in an active state, the method further includes: and judging whether the current gain is stably changed within a first preset threshold value within a preset time length, and if so, latching and storing the current automatic gain control signal.
With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner, the method further includes: after an analog input signal is sequentially input to the gain adjustment circuit, the ADC module and the power statistics module, at least one of a high and low level state of a transmission and reception signal and an output result of the power statistics module is monitored by using a state machine.
Compared with the prior art, the invention has the beneficial effects that: the gain latch circuit may latch the gain before the reception state is ended when the transmission/reception state is switched. In a receiving state, when the selection signal after enabling operation is in an effective state, the gain selection circuit selects the current first output signal of the automatic gain control circuit to be input to the gain adjustment circuit for gain control; when the state is switched to a sending state or when the change amplitude of the input signal exceeds a first preset threshold range and the selection signal is in an invalid state, the gain selection circuit selects the second output signal of the gain latch circuit to be input to the gain adjustment circuit for gain control. By this means, a gain value close to the ideal gain can be provided quickly based on the second output signal of the gain latch circuit after entering the receiving state, thereby achieving the effect of rapid convergence.
Drawings
Fig. 1 is a schematic structural diagram of a fast automatic gain control device based on time division multiplexing for transceiving according to an embodiment of the present application;
FIG. 2 is an exemplary circuit diagram of a delay circuit according to an embodiment of the present disclosure;
fig. 3 is an exemplary circuit diagram of a gain latch circuit according to an embodiment of the present disclosure;
fig. 4 is an exemplary circuit diagram of a gain selection circuit provided in an embodiment of the present application;
fig. 5 is a flowchart illustrating a fast automatic gain control method based on time division multiplexing for transceiving according to an embodiment of the present application.
Reference numerals: 10-automatic gain control device based on time division multiplexing of receiving and transmitting, 110-gain adjusting circuit, 120-ADC module, 130-power statistic module, 140-state machine, 150-time delay circuit, 160-automatic gain control circuit, 170-gain selection circuit and 180-gain latch circuit.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not construed as indicating or implying relative importance.
Referring to fig. 1, an embodiment of the present application provides an automatic gain control apparatus based on transmit-receive time division multiplexing. The automatic gain control device 10 based on the time division multiplexing for transmission and reception includes: the gain adjusting circuit 110, the ADC module 120, the power statistics module 130, the state machine 140, the delay circuit 150, the automatic gain control circuit 160, the gain selection circuit 170, and the gain latch circuit 180; the output end of the gain adjusting circuit 110 is connected to the input end of the ADC module, the output end of the ADC module 120 is connected to the input end of the power statistics module 130, the first output end of the power statistics module 130 is connected to the first input end of the state machine 140, the second output end of the power statistics module 130 is connected to the input end of the automatic gain control circuit 160, the second input end of the state machine 140 is connected to the input end of the delay circuit 150, the output end of the delay circuit 150 is connected to the first input end of the gain selection circuit 170, the output end of the automatic gain control circuit 160 is connected to the second input end of the gain selection circuit 170, the port of the gain latch circuit 180 is connected to the third input end of the gain selection circuit 170 for bidirectional transmission, the output end of the gain selection circuit 170 is connected to the first input end of the gain adjusting circuit 110, the second input end of the gain adjusting circuit 110 is externally connected to an analog input signal, wherein the ADC module 120 is configured to convert the analog signal into a digital signal.
Referring to fig. 2 to 4, in detail, the delay circuit 150 includes: the circuit comprises a first trigger, a second trigger, an exclusive-OR logic gate, a counter and a third trigger; the input end of the first trigger is connected with the output signal of the output end of the state machine 140, the output end of the first trigger is connected with the input end of the second trigger, the first input end of the exclusive-or logic gate is connected with the output end of the first trigger, the second input end of the exclusive-or logic gate is connected with the output end of the second trigger, the output end of the exclusive-or logic gate is connected with the input end of the counter, the output end of the counter is connected with the first input end of the third trigger, the output signal of the output end of the state machine 140 is connected with the second input end of the third trigger, and the output end of the third trigger outputs the selection signal. In this embodiment, the first flip-flop and the second flip-flop are D flip-flops, the third flip-flop is a D flip-flop with an enable terminal, and the first input terminal of the third flip-flop is an enable terminal. It should be noted that the first flip-flop, the second flip-flop, and the third flip-flop are D flip-flops, which are only exemplary embodiments, and a specific type of the flip-flop is not limited.
In this embodiment, the output signal from the output terminal of the state machine 140 is delayed by two clocks by the first flip-flop and the second flip-flop, and then is input to the xor gate, the output of the xor gate is used as the reset signal of the counter, and when the state of the reset signal is the preset trigger signal state, the counter starts counting. The output end of the counter is connected with the first input end of the third flip-flop, when a clock edge is triggered, the second input end of the third flip-flop connected with the output end of the state machine 140 is in a high level state, and the first input end of the third flip-flop connected with the output end of the counter meets a preset delay value, the output end of the third flip-flop is 1, so that delay is realized, and whether the selection signal is in an effective state is determined according to the high and low level states of the output end of the third flip-flop, wherein two inputs of the exclusive-or logic gate are signals passing through the first flip-flop and the second flip-flop respectively, when the signal state values corresponding to the two input ends are different respectively, the output is 1, and when the signal state values corresponding to the two input ends are the same respectively, the output is 0; and the preset delay value can be specifically set according to specific application. That is, the state of the signal output by the third flip-flop may be determined according to the clock signal and the state signal of the state machine 140.
As a possible implementation, the gain latch circuit 180 includes: the fourth trigger, the subtracter, the comparator and the fifth trigger; the input end of the fourth flip-flop is connected with the first output signal of the automatic gain control circuit 160, the output end of the fourth flip-flop is connected with the first input end of the subtracter, the first output signal of the automatic gain control circuit 160 is connected with the second input end of the subtracter, the output end of the subtracter is connected with the first input end of the comparator, the second input end of the comparator is connected with the latch threshold signal with the first preset threshold, the output end of the comparator is connected with the first input end of the fifth flip-flop, the second input end of the fifth flip-flop is connected with the output end of the fourth flip-flop, and the output end of the fifth flip-flop is connected with the gain selection circuit 170.
Specifically, a first input terminal of the subtractor is connected to an output terminal delayed by one clock by the fourth flip-flop, and a second input terminal of the subtractor is connected to a first output signal of the automatic gain control circuit 160; after the difference operation between the first input end and the second input end of the subtractor is based, the output end of the subtractor is connected with the first input end of the comparator, the second input end of the comparator is connected with a latch threshold signal with a first preset threshold, the comparator is used for comparing the difference between the output end signal of the subtractor and the preset latch threshold, the output end of the comparator is connected with the first input end of the fifth trigger, the second input end of the fifth trigger is connected with the output end delayed by one clock through the fourth trigger, and the clock input end of the fourth trigger and the clock input end of the fifth trigger are connected with the automatic gain control updating signal, so that the output signal state of the gain latch circuit 180 changes in real time along with the automatic gain control signal. When the first output signal which is triggered by the clock edge and delayed by one clock through the fourth flip-flop is in a high level state and the output signal of the comparator is in a preset state, the output end of the fifth flip-flop is 1, so that the current gain is latched when the gain is stable. In the embodiment of the present application, the fourth flip-flop is a D flip-flop, and the fifth flip-flop is a D flip-flop having an enable terminal. It should be noted that the fourth flip-flop and the fifth flip-flop are D flip-flops, which are only exemplary embodiments, and the specific flip-flop type is not limited.
In the embodiment of the present application, a first input terminal of the gain selection circuit 170 is connected to the selection signal output by the output terminal of the delay circuit 150, a second input terminal of the gain selection circuit 170 is connected to the first output signal output by the output terminal of the automatic gain control circuit 160, and a third input terminal of the gain selection circuit 170 is connected to the second output signal output by the port of the gain latch circuit 180; the gain selection circuit 170 selects to output the gain output signal corresponding to the automatic gain control circuit 160 or the gain latch signal latched by the gain latch circuit 180 based on the validity of the input signals of the first input terminal, the second input terminal, and the third input terminal. If the selection signal of the delay circuit 150 is in an active state, the first output signal of the agc circuit 160 is selected to be output; if the selection signal of the delay circuit 150 is inactive, the second output signal of the gain latch circuit 180 is selected and outputted.
Referring to fig. 5, an embodiment of the present application provides a flowchart of an automatic gain control method based on time division multiplexing for transceiving. In the embodiment of the present application, the method for automatic gain control based on transmit-receive time division multiplexing includes steps S11 and S12, and is applied to the above-mentioned apparatus for automatic gain control based on transmit-receive time division multiplexing.
Step S11: judging whether the current selection signal is in an effective state;
step S12: if the judgment result is yes, the gain selection circuit inputs the first output signal of the automatic gain control circuit to the gain adjustment circuit for gain control; if the judgment result is negative, the gain selection circuit inputs a second output signal of the selective gain latch circuit to the gain adjustment circuit for gain control, wherein the second output signal is an automatic gain control signal which is latched when the gain is stable and unchanged.
The specific implementation flow of the automatic gain control method based on the time division multiplexing for transceiving is described in detail below.
Before step S11, the method for controlling an automatic gain based on transmit-receive time division multiplexing further includes: and judging whether the current gain is stably changed within a first preset threshold value within a preset time length, and if so, latching and storing the current automatic gain control signal.
In detail, in the embodiment of the present application, it is determined whether or not the current gain is stabilized within a first preset threshold range, where the first preset threshold is related to a latch threshold signal based on a first preset threshold set in the automatic gain control device for time division multiplexing transmission and reception. The first preset threshold may be a specific value or a range of values, that is, the current gain is kept at a fixed value within a preset time period or stably changes within a certain range of values, it may be determined that the output of the current automatic gain control circuit is in a stable state, and thus the output is latched, where the first preset threshold may be set according to a specific input analog input signal.
Step S11: and judging whether the current selection signal is in an effective state or not.
In detail, it is determined whether the transceive signal is in a high level state for indicating a receiving state, and it is determined whether there is an instantaneous power signal smaller than a first preset threshold value based on the power statistics.
As a possible embodiment, the transmission/reception signal has a high state and a low state, and the transmission/reception signal is changed between the high state and the low state according to the clock signal, wherein the high state indicates the reception state and the low state indicates the transmission state. When the receiving and transmitting signal is in a high level state, the selection signal is enabled through the delay circuit to obtain the selection signal in an effective state; when the transmitting and receiving signal is in low level state, the selection signal in inactive state is obtained by the delay circuit. It should be noted that the delay circuit has at least two functions in the embodiment of the present application, one is to align with the power statistics time, and the other is to align the analog circuit settling time after the transmission state is converted into the receiving mode.
As another possible implementation manner, power statistics is performed after the output of the ADC module, the instantaneous power level at each moment can be determined through the power statistics, and when the instantaneous power signal is lower than a second preset threshold, it indicates that the amplitude of the analog input signal changes excessively, and at this time, the corresponding selection signal is in an invalid state, where the second preset threshold may be determined according to the input amplitude variation range of the analog input signal, and the specific second preset threshold may be a specific numerical value or a numerical range. Specifically, the instantaneous power signal can be directly compared with the fixed second preset threshold value by setting the fixed second preset threshold value, and when the instantaneous power signal is lower than the fixed second preset threshold value, the selection signal at the moment is determined to be in an invalid state.
Step S12: if the judgment result is yes, the gain selection circuit inputs the first output signal of the automatic gain control circuit to the gain adjustment circuit for gain control; if the judgment result is negative, the gain selection circuit inputs a second output signal of the selective gain latch circuit to the gain adjustment circuit for gain control, wherein the second output signal is an automatic gain control signal which is latched when the gain is stable and unchanged.
In detail, when the selection signal is determined to be in an active state, the selection signal inputs the first output signal of the selection automatic gain control circuit to the gain adjustment circuit for gain control.
When the selection signal is in the effective state, the receiving and transmitting signal is in the receiving state or the change amplitude of the analog input signal is not large, the automatic gain control circuit can quickly adjust the gain meeting the conditions, and therefore automatic gain control adjustment can be carried out through the automatic gain control circuit, so that when the analog input signal dynamically changes in a certain range, the output voltage signal keeps stable and is not influenced by the analog input signal.
When the selection signal is in an invalid state, the transceiving signal is in a transmitting state or the analog input signal has a large variation amplitude, if the gain is directly adjusted from the current gain to the gain meeting the condition for a period of time, the second output signal of the gain latch circuit can be input to the gain adjustment circuit for gain control, and the gain latch circuit latches the gain when the gain is stably changed, so that when the variation amplitude of the analog input signal is large, the gain adjusted from the gain when the gain is stabilized to the gain when the condition is met can be quickly adjusted and converged, thereby keeping the output voltage signal to keep stable output without being influenced by the analog input signal.
As a possible implementation manner, the automatic gain control method based on transmit-receive time division multiplexing further includes: after an analog input signal is sequentially input to the gain adjustment circuit, the ADC module and the power statistics module, a state machine is used for monitoring at least one of a high-low level state of a transmitting-receiving signal and an output result of the power statistics module.
Specifically, the state machine is responsible for monitoring the transceiving signal and the power statistic result, and when the transceiving signal is converted into the low level state and the power statistic result is at least one of the voltage signal is instantly lower than the preset threshold value, the selection signal is invalid through the delay circuit, so that the output result of the gain selection circuit selection gain latch circuit is input to the gain adjusting circuit.
To sum up, the embodiment of the present application provides a fast automatic gain control device based on time division multiplexing for transceiving, and the device includes: the device comprises a gain adjusting circuit, an ADC module, a power statistics module, a state machine, a delay circuit, an automatic gain control circuit, a gain selection circuit and a gain latch circuit; the output end of the gain adjusting circuit is connected with the input end of the ADC module, the output end of the ADC module is connected with the input end of the power statistics module, the first output end of the power statistics module is connected with the first input end of the state machine, the second output end of the power statistics module is connected with the input end of the automatic gain control circuit, the second input end of the state machine is connected with an input receiving and transmitting signal, the output end of the state machine is connected with the input end of the delay circuit, the output end of the delay circuit is connected with the first input end of the gain selecting circuit, the output end of the automatic gain control circuit is connected with the second input end of the gain selecting circuit, a port of the gain latching circuit is connected with the third input end of the gain selecting circuit for bidirectional transmission, the output end of the gain selecting circuit is connected with the first input end of the gain adjusting circuit, and the second input end of the gain adjusting circuit is externally connected with an analog input signal.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. An automatic gain control apparatus based on transmit-receive time division multiplexing, the apparatus comprising: the device comprises a gain adjusting circuit, an ADC module, a power statistics module, a state machine, a delay circuit, an automatic gain control circuit, a gain selection circuit and a gain latch circuit;
the output end of the gain adjusting circuit is connected with the input end of the ADC module, the output end of the ADC module is connected with the input end of the power statistics module, the first output end of the power statistics module is connected with the first input end of the state machine, the second output end of the power statistics module is connected with the input end of the automatic gain control circuit, the second input end of the state machine is connected with an input receiving and transmitting signal, the output end of the state machine is connected with the input end of the delay circuit, the output end of the delay circuit is connected with the first input end of the gain selection circuit, the output end of the automatic gain control circuit is connected with the second input end of the gain selection circuit, the port of the gain latch circuit is connected with the third input end of the gain selection circuit for bidirectional transmission, the output end of the gain selection circuit is connected with the first input end of the gain adjusting circuit, and the second input end of the gain adjusting circuit is externally connected with an analog input signal.
2. The apparatus of claim 1, wherein the delay circuit comprises: the circuit comprises a first trigger, a second trigger, an exclusive-OR logic gate, a counter and a third trigger;
the input of first trigger with the output signal of the output of state machine is connected, the output of first trigger with the input of second trigger is connected, the first input of XOR logic gate with the output of first trigger is connected, the second input of XOR logic gate with the output of second trigger is connected, the output of XOR logic gate with the input of counter is connected, the output of counter with the first input of third trigger is connected, the output of state machine's output with the second input of third trigger is connected, the output of third trigger output select signal.
3. The apparatus of claim 1, wherein the gain latch circuit comprises: the fourth trigger, the subtracter, the comparator and the fifth trigger;
the input of fourth trigger with automatic gain control circuit's first output signal is connected, the output of fourth trigger with the first input of subtractor is connected, automatic gain control circuit's first output signal with the second input of subtractor is connected, the output of subtractor with the first input of comparator is connected, the second input of comparator is connected with the latch threshold value signal that has first preset threshold value, the output of comparator with the first input of fifth trigger is connected, the second input of fifth trigger with the output of fourth trigger is connected, the output of fifth trigger with gain selection circuit connects.
4. An automatic gain control method based on transmit-receive time division multiplexing, which is applied to the automatic gain control device based on transmit-receive time division multiplexing according to any one of claims 1-3, the method comprising:
judging whether the current selection signal is in an effective state;
if the judgment result is yes, the gain selection circuit inputs the first output signal of the automatic gain control circuit to the gain adjustment circuit for gain control;
if the judgment result is negative, the gain selection circuit inputs a second output signal of the selective gain latch circuit to the gain adjustment circuit for gain control, wherein the second output signal is an automatic gain control signal which is latched when the gain is stable and unchanged.
5. The method of claim 4, wherein the determining whether the current selection signal is active comprises:
judging whether the receiving and transmitting signal is in a high level state representing a receiving state, if so, enabling the selection signal through a time delay circuit to obtain the selection signal in an effective state;
if not, the selection signal in an invalid state is obtained through the delay circuit.
6. The method of claim 5, wherein the determining whether the current selection signal is active further comprises:
and judging whether an instantaneous power signal is smaller than a second preset threshold value or not based on the power statistical module, and if so, processing the current signal into a selection signal in an invalid state through the delay circuit.
7. The method of claim 4, wherein before the determining whether the current selection signal is active, the method further comprises:
and judging whether the current gain is stably changed within a first preset threshold value within a preset time length, and if so, latching and storing the current automatic gain control signal.
8. The method of claim 7, further comprising:
after an analog input signal is sequentially input to the gain adjustment circuit, the ADC module and the power statistics module, at least one of a high and low level state of a transmission and reception signal and an output result of the power statistics module is monitored by using a state machine.
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