CN113257311A

CN113257311A - Control method and device of phase change memory and storage medium

Info

Publication number: CN113257311A
Application number: CN202110358178.3A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-04-01
Filing date: 2021-04-01
Publication date: 2021-08-13
Anticipated expiration: 2041-04-01
Also published as: CN113257311B

Abstract

The embodiment of the invention provides a control method and device of a phase change memory and a storage medium. Wherein the control method comprises the following steps: selecting two memory cells in a memory array block of the phase change memory; the phase change memory comprises a plurality of first address line layers and second address line layers which are arranged at intervals, and a storage unit layer positioned between the first address line layers and the second address line layers; the first address line layer comprises a plurality of first address lines extending along a first direction; the second-type address line layer comprises a plurality of second-type address lines extending along a second direction perpendicular to the first direction; the first-type address lines which are activated and controlled commonly exist in the first-type address line layers of different layers; the two selected memory cells include two memory cells coupled to a second type of address line in a second type of address line layer of a different layer; and simultaneously performing reading operation or writing operation on the two storage units.

Description

Control method and device of phase change memory and storage medium

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for controlling a phase change memory, and a storage medium.

Background

Phase Change Memory (english may be expressed as Phase Change Memory, and abbreviated as PCM) is a Memory technology using chalcogenide as a storage medium, and uses the resistance difference of materials in different states to store data. The phase change memory has the advantages of being addressable by bits, not losing data after power failure, high storage density, high read-write speed and the like, and is considered to be the most promising next-generation memory.

In the related art, the mainstream architecture of the phase change memory comprises a two-layer stacked memory cell architecture. However, the two-layer stacked Memory cell architecture cannot provide sufficient bit density and cannot compete with the mainstream Dynamic Random Access Memory (DRAM) and NAND type Memory. Based on this, a multi-layer stacked memory cell architecture larger than two layers, such as a four-layer stacked memory cell architecture, is proposed. However, in the related art, the phase change memory having the multi-layered stacked memory cells larger than two layers does not have an advantage of access efficiency in performing a read operation or a write operation, compared to the phase change memory having the two-layered stacked memory cells.

Disclosure of Invention

In order to solve the related technical problems, embodiments of the present invention provide a method and an apparatus for controlling a phase change memory, and a storage medium.

The embodiment of the invention provides a control method of a phase change memory, which comprises the following steps:

selecting two memory cells in a memory array block of the phase change memory; the phase change memory comprises a plurality of first address line layers and second address line layers which are arranged at intervals, and a storage unit layer positioned between the first address line layers and the second address line layers; the first address line layer comprises a plurality of first address lines extending along a first direction; the second-type address line layer comprises a plurality of second-type address lines extending along a second direction perpendicular to the first direction; the memory cell layer includes a plurality of memory cells, each of the plurality of memory cells coupled to first-type address lines and second-type address lines adjacent to the respective memory cell; the first-type address lines which are activated and controlled commonly exist in the first-type address line layers of different layers; the two selected memory cells include two memory cells coupled to a second type of address line in a second type of address line layer of a different layer;

and simultaneously performing reading operation or writing operation on the two storage units.

In the scheme, the phase change memory comprises four stacked memory unit layers, and a top first-type address line layer, a top second-type address line layer, a middle first-type address line layer, a bottom second-type address line layer and a bottom first-type address line layer which are sequentially distributed from top to bottom; the top first-type address line layer and the bottom first-type address line layer are provided with first-type address lines which are activated and controlled together;

the selected two memory cells include: a first memory cell coupled to the top first-type address line layer and the top second-type address line layer, and a second memory cell coupled to the bottom first-type address line layer and the bottom second-type address line layer.

the selected two memory cells include: a first memory cell coupled to the top second-type address line layer and the middle first-type address line layer, and a second memory cell coupled to the bottom second-type address line layer and the middle first-type address line layer.

In the above solution, the first type address line coupled to the first memory cell and the first type address line coupled to the second memory cell are activated and controlled together.

In the above scheme, during the process of performing read operation or write operation on the two memory cells simultaneously, a first voltage is applied to the selected first-type address lines coupled to the two memory cells; applying a second voltage to both selected second-type address lines coupled to the two memory cells; the first voltage is a negative voltage, and the second voltage is a positive voltage;

applying a third voltage to all unselected address lines of the first type in the selected memory array block; a fourth voltage is applied to all unselected address lines of the second type in the selected memory array block.

In the above scheme, in the process of simultaneously performing the read operation on the two memory cells, the storage states of the two memory cells are obtained by sensing the change of the voltage on the second-type address line.

In the above scheme, in the process of performing write operation on the two memory cells simultaneously, the two-bit binary mode is adopted for writing.

An embodiment of the present invention further provides a control apparatus for a phase change memory, including:

a selection unit for selecting two memory cells in one memory array block of the phase change memory; the phase change memory comprises a plurality of first address line layers and second address line layers which are arranged at intervals, and a storage unit layer positioned between the first address line layers and the second address line layers; the first address line layer comprises a plurality of first address lines extending along a first direction; the second-type address line layer comprises a plurality of second-type address lines extending along a second direction perpendicular to the first direction; the memory cell layer includes a plurality of memory cells, each of the plurality of memory cells coupled to first-type address lines and second-type address lines adjacent to the respective memory cell; the first-type address lines which are activated and controlled commonly exist in the first-type address line layers of different layers; the two selected memory cells include two memory cells coupled to a second type of address line in a second type of address line layer of a different layer;

and the processing unit is used for simultaneously performing reading operation or writing operation on the two storage units.

An embodiment of the present invention further provides a control apparatus for a phase change memory, including: a processor and a memory configured to store a computer program operable on the processor;

wherein the processor is configured to implement the steps of any of the above methods when the computer program is executed.

An embodiment of the present invention further provides a storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of any one of the above-mentioned methods.

The embodiment of the invention provides a control method and device of a phase change memory and a storage medium. Wherein the control method comprises the following steps: selecting two memory cells in a memory array block of the phase change memory; the phase change memory comprises a plurality of first address line layers and second address line layers which are arranged at intervals, and a storage unit layer positioned between the first address line layers and the second address line layers; the first address line layer comprises a plurality of first address lines extending along a first direction; the second-type address line layer comprises a plurality of second-type address lines extending along a second direction perpendicular to the first direction; the memory cell layer includes a plurality of memory cells, each of the plurality of memory cells coupled to first-type address lines and second-type address lines adjacent to the respective memory cell; the first-type address lines which are activated and controlled commonly exist in the first-type address line layers of different layers; the two selected memory cells include two memory cells coupled to a second type of address line in a second type of address line layer of a different layer; and simultaneously performing reading operation or writing operation on the two storage units. In the embodiment of the invention, two memory cells in one memory array block in the phase change memory can be selected at one time to simultaneously perform read operation or write operation, so that two memory cells in the phase change memory can be simultaneously accessed at one time. In this way, it is possible to improve access efficiency when a read operation or a write operation is performed on a multi-layer stacked phase change memory greater than two layers.

Drawings

FIG. 1 is a schematic diagram of a phase change memory cell array observed by a scanning electron microscope according to an embodiment of the present invention;

FIG. 2 is a three-dimensional schematic diagram of bit lines, word lines and memory cells in a two-layer stacked phase change memory according to an embodiment of the invention;

fig. 3 is a schematic flow chart illustrating an implementation of a method for controlling a phase change memory according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a four-layer stacked phase change memory cell according to an embodiment of the present invention;

FIG. 5a is a partial horizontal schematic view of a phase change memory cell array having four stacked memory cells according to an embodiment of the present invention;

FIG. 5b is a schematic diagram illustrating the distribution of word line decoder regions and bit line decoder regions of a phase change memory having four stacked memory cells according to an embodiment of the present invention;

FIG. 6a is a first schematic diagram illustrating a bit line distribution of another phase change memory cell array having four stacked memory cells according to an embodiment of the present invention;

FIG. 6b is a second schematic diagram illustrating a bit line distribution of another phase change memory cell array having four stacked memory cells according to an embodiment of the present invention;

FIG. 6c is a schematic diagram illustrating a word line distribution of another phase change memory cell array having four stacked memory cells according to an embodiment of the present invention;

FIG. 6d is a schematic diagram illustrating the distribution of word line decoder regions and bit line decoder regions of another phase change memory having four stacked memory cells according to an embodiment of the present invention;

FIG. 7a is a partial Y-direction diagram of a phase change memory cell array with a four-layer stack according to an embodiment of the present invention;

FIG. 7b is a schematic diagram illustrating a partial X-direction of a phase change memory cell array having a four-layer stack according to an embodiment of the present invention;

FIG. 7c is a partial Z-direction schematic diagram of a phase change memory cell array having a four-layer stack according to an embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating a structure of a control device of a phase change memory according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a hardware configuration of a control device of a phase change memory according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the following will describe specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.

In practical applications, the phase change memory may include a memory cell array and peripheral circuits; wherein the memory cell array may be integrated on the same die of the peripheral circuit, which allows for a wider bus and higher operating speed. In practical applications, the memory cell array and the peripheral circuit may be formed in different regions on the same plane; or the memory cell array and the peripheral circuit may form a stacked structure, i.e., they are formed on different planes. For example, the memory cell array may be formed over peripheral circuits to reduce the chip size.

In some embodiments, the peripheral circuitry includes any suitable digital, analog, and/or mixed-signal circuitry for facilitating phase change memory operations. For example, the peripheral circuits may include control logic, data buffers, decoders (which may also be referred to as decoders), drivers, and read/write circuits, among others. When the control logic receives the read-write operation command and the address data, under the action of the control logic, the decoder can apply corresponding voltages generated by the driver to corresponding bit lines and word lines based on the decoded address so as to realize the read operation or write operation of the data, and perform data interaction with the outside through the data buffer.

In some embodiments, the memory cell array may include at least one memory array block, and each memory array block may include a plurality of stacked memory cell layers therein, each memory cell layer including a plurality of memory cells. After receiving the read operation or write operation command and the address data, the control logic may determine, under the action of the decoder, a selected word line and a selected bit line corresponding to the selected memory cell among the plurality of memory cells.

In the related art, the mainstream architecture of the phase change memory includes a two-layer stacked memory cell architecture, and fig. 1 is a schematic diagram of a two-layer stacked phase change memory cell array observed by a scanning electron microscope. As can be seen from fig. 1, a phase change memory chip is composed of a plurality of small memory array blocks having a single bit line, word line, and memory cell. Phase change memories generally include a top bit line, a word line, a bottom bit line, and a memory cell located at the intersection of the bit line and the word line. In practical applications, the word lines, the top bit lines and the bottom bit lines are typically formed by a pattern of lines of constant width (L/S, Line/Space) of 20nm/20nm formed after a patterning process. Where contacts to top and bottom bit lines and word lines are placed in the middle of the memory array, having separate bit line and word line contacts.

In practical applications, the two-layer stacked phase change memory is shown in fig. 2, and each memory cell may include a two-layer stacked phase change memory element 202, a selector 204, and a plurality of electrodes 201, 203, and 205. The phase change memory element 202 may electrothermal-based heat and quench the phase change material such that the phase change material may be switched between amorphous and crystalline phases-here, a current may be applied to repeatedly switch the phase change material of the phase change memory element 202 (or at least a portion thereof that blocks the current path) between the two phases to store data. A single bit of data may be stored in each memory cell and a read or write operation of a single bit may be performed by varying the voltage applied to the corresponding selector 204.

Referring to fig. 2, the memory cell array includes: a plurality of top bit lines 23 in parallel and a plurality of bottom bit lines 24 in parallel; there is an offset between the top bit line 23 and the corresponding bottom bit line 24 (one bottom bit line below the top bit line); a top bit line connection portion 231 (here, the english language of the connection portion may be expressed as Contact, and the connection portion may also be referred to as a Contact) contacting the top bit line 23 and extending from between two adjacent bottom bit lines 24 for connecting the top bit line 23 and the related device; a bottom bit line connection portion 241 contacting the bottom bit line 24 for enabling connection of the bottom bit line 24 with an associated device; a plurality of word lines 25 between the top bit lines 23 and the bottom bit lines 24; a plurality of word lines 25 are in the same plane and parallel to the top bit lines 23 and the bottom bit lines 24; a word line connection portion 241 contacting the word line 25 for connecting the word line 25 to an associated device; an upper memory cell 21 between the top bit line 23 and the word line 25 and connected to the corresponding top bit line 23 and the word line 25, the plurality of upper memory cells forming a top memory cell layer; a lower memory cell 22 between the word line 25 and the bottom bit line 24, the plurality of lower memory cells forming a bottom memory cell layer.

In some embodiments, the material of the phase change memory element 202 comprises a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase change material; the material of the selector 204 may include any suitable Ovonic Threshold Switch (OTS) material, such as Zn_xTe_y、Ge_xTe_y、Nb_xO_y、Si_xAs_yTe_zAnd the like. It should be understood that the structure, configuration, and materials of the memory cell are not limited to the example in fig. 2 and may include any suitable structure, configuration, and materials. Electrodes 201, 203, and 205 may comprise a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of electrodes 201, 203, and 205 comprises carbon, such as amorphous carbon.

However, the two-layer stacked memory cell architecture does not provide sufficient bit density to compete with the mainstream DRAM and NAND type memory. Based on this, a multi-layer stacked memory cell architecture larger than two layers is proposed, such as a four-layer stacked phase change memory, which reduces the manufacturing cost while increasing the bit density. However, in the related art, the phase change memory of the multi-layer stacked memory cells larger than two layers and the two-layer stacked phase change memory can only select one memory cell in one memory array block at a time to perform a read operation or a write operation when the read operation or the write operation is performed on the selected memory cell; thus, compared to a two-layer stacked phase change memory, a phase change memory having a memory cell stacked in multiple layers larger than two layers has a structure in which the bit density is increased, but the access efficiency is not increased when a read operation or a write operation is performed.

Based on this, in various embodiments of the present invention, two memory cells in one memory array block in the phase change memory can be selected at a time to perform a read operation or a write operation simultaneously, thereby implementing simultaneous access to two memory cells in the phase change memory at a time. In this way, access efficiency can be improved when a read operation or a write operation is performed in a multi-layer stacked phase change memory greater than two layers.

The embodiment of the invention provides a control method of a phase change memory. Fig. 3 is a schematic flow chart illustrating an implementation of a control method of a phase change memory according to an embodiment of the invention. As shown in fig. 3, the method comprises the steps of:

step 301: selecting two memory cells in a memory array block of the phase change memory; the phase change memory comprises a plurality of first address line layers and second address line layers which are arranged at intervals, and a storage unit layer positioned between the first address line layers and the second address line layers; the first address line layer comprises a plurality of first address lines extending along a first direction; the second-type address line layer comprises a plurality of second-type address lines extending along a second direction perpendicular to the first direction; the memory cell layer includes a plurality of memory cells, each of the plurality of memory cells coupled to first-type address lines and second-type address lines adjacent to the respective memory cell; the first-type address lines which are activated and controlled commonly exist in the first-type address line layers of different layers; the two selected memory cells include two memory cells coupled to a second type of address line in a second type of address line layer of a different layer;

step 302: and simultaneously performing reading operation or writing operation on the two storage units.

Here, the phase change memory includes at least one memory array block; the memory array block includes a first type address line layer, a second type address line layer, and a memory cell layer between the first type address line layer and the second type address line layer. In practical applications, the phase change memory in the embodiment of the present invention may include more than two memory cell layers, and a plurality of first type address line layers and a plurality of second type address line layers corresponding to the more than two memory cell layers. The phase change memory as in the embodiment of the present invention may include four stacked memory cell layers, six stacked memory cell layers, and the like.

In practical application, the first address line layer and the second address line layer are parallel; the first address line layer comprises a plurality of first address lines extending along a first direction; the second-type address line layer includes a plurality of second-type address lines extending in a second direction perpendicular to the first direction. Here, the first direction may be a direction in which the first-type address lines in the first-type address line layer extend; the second direction may be a direction in which a second-type address line in a second-type address line layer extends; wherein the first direction is perpendicular to the second direction. In practical applications, the first direction may be an X direction or a Y direction; the second direction may be the Y direction or the X direction; when the first direction is the X direction, the second direction is the Y direction; when the first direction is the Y direction, the second direction is the X direction. For clarity, in the present embodiment, the first direction is taken as the X direction, and the second direction is taken as the Y direction for explanation.

In practical application, a first type address line of the first type address line layer is vertical to a second type address line of the second type address line layer; each memory unit in the memory unit layer is perpendicular to the first address line of the first address line layer and the second address line of the second address line layer.

In practical applications, the first address lines in the first address line layer may include word lines or bit lines; the second type address lines in the second type address line layer may include bit lines or word lines, but the first type address lines need to be different from the second type address lines. Illustratively, the first type of address line layer may comprise a word line layer, and correspondingly the second type of address line layer may comprise a bit line layer; alternatively, the first type of address line layer may comprise a bit line layer and correspondingly the second type of address line layer may comprise a word line layer. In practical applications, the material of the first type address line and the second type address line may include tungsten.

In practical application, the phase change memory comprises a plurality of memory cell layers; the memory cell layer includes a plurality of memory cells. The plurality of memory cells are each coupled to first and second types of address line layers adjacent the plurality of memory cells, and each of the plurality of memory cells is coupled to a word line and a bit line adjacent the memory cell corresponding to the first and second types of address line layers adjacent the plurality of memory cells.

Here, it is considered that each of the plurality of memory cells needs to be coupled to a first type address line layer and a second type address line layer adjacent to the corresponding memory cell in the phase change memory. In order to access the memory unit, the first-type address lines of each first-type address line layer and the second-type address lines of each second-type address line layer need to be connected into a peripheral circuit through corresponding connecting parts. With the increase of the number of layers of the memory unit, the number of layers of the first-type address line layer and the second-type address line layer is correspondingly increased, so that under the condition of ensuring that the size is as small as possible, all the first-type address lines and the second-type address lines are difficult to be connected to a peripheral circuit. In order to make the manufacturing process of the connection simpler, at least two address lines of the first type present in different layers of the address line layers of the first type may be arranged to be jointly actively controlled. That is, there are address lines of the first type in different layers of the address line layer of the first type that are collectively activated to be controlled. It should be noted that the collective activation control does not affect the selection of individual memory cells. In practice, the address lines of the first type of the address line layer of the spacer layer are typically arranged to be activated and controlled in common in order not to affect the selection of a single memory cell.

When two memory cells in a memory array block of the phase change memory are selected, the selected two memory cells include two memory cells coupled to a second type address line in a second type address line layer of a different layer. Therefore, the two different selected memory units cannot be mistakenly selected due to the first-type address lines which are activated and controlled together. In other words, selecting two memory cells in this manner ensures that no read or write disturb will be caused during simultaneous read or write operations to two memory cells in different memory cell layers being selected.

It should be noted that, when at least two first-type address lines controlled by common activation are included in different first-type address line layers to which two selected memory cells are coupled, the two selected memory cells are respectively coupled to second-type address lines in different second-type address line layers; or when at least two second-type address lines which are activated and controlled jointly exist in different second-type address line layers, the two selected memory units are respectively coupled to different first-type address line layers.

The following takes a phase change memory including four stacked memory cell layers as an example, and further explains the scheme of the present embodiment.

Referring to fig. 4, an architecture diagram of a four-layer stacked phase change memory cell is shown in fig. 4. As shown in fig. 4, the phase change memory in the embodiment of the invention has four memory cell layers, and three first-type address line layers and two second-type address line layers corresponding to the four memory cell layers.

Here, the first address line layer 41 of the three first address line layers includes at least one first address line 41-1, and the first address line layer 41 may also be referred to as a top first address line layer; the first-type address lines of the first-layer first-type address line layer 41 extend in the Y direction; when the first-type address line layer 41 includes a plurality of first-type address lines (41-1, 41-2 …), the length of the first-type address lines of the first-type address line layer is the same (the length is L1), and the first-type address lines are arranged in parallel along the X direction. In some embodiments, the plurality of first-type address lines of the first-type address line layer are aligned in a column in parallel along the X-direction. The second layer first type address line layer 42 of the three first type address line layers comprises at least one first type address line, the first type address line of the second layer first type address line layer 42 can also be called as a middle first type address line, and the first type address line of the second layer first type address line layer 42 extends along the Y direction; when the second layer first address line layer 42 includes a plurality of first address lines (42-1, 42-2, 42-3 …), the plurality of first address lines of the second layer first address line layer 42 have the same length (the length is L2), and are arranged in parallel along the X direction. In some embodiments, the plurality of first-type address lines of the second-layer first-type address line layer 42 are arranged in a column in parallel along the X-direction. The third first type address line layer 43 of the three first type address line layers comprises at least one first type address line, the first type address line of the third first type address line layer 43 can also be called as a bottom first type address line layer, and the first type address line of the third first type address line layer 43 extends along the Y direction; when the third first address line layer 43 includes a plurality of first address lines (43-1, 43-2, 43-3 …), the plurality of first address lines of the third first address line layer 43 have the same length (the length is L3), and are arranged in parallel along the X direction. In some embodiments, the plurality of first-type address lines of the third first-type address line layer 43 are arranged in a column in parallel along the X direction. The length of each first-type address line of first-layer first-type address line layer 41, the length of each first-type address line of second-layer first-type address line layer 42, and the length of each first-type address line of third-layer first-type address line layer 43 may all be the same.

Here, the first plane may include a plane parallel to a plane formed by X, Y. Each first-type address line of the first-layer first-type address line layer 41 coincides with a projection of a corresponding first-type address line of the second-layer first-type address line layer 42 onto the first plane. That is, each first-type address line of the first-layer first-type address line layer 41 is offset from the first-type address line of the corresponding second-layer first-type address line layer 42 in the projection of the first plane and the Y direction, and the offset may be about half the length of the first-type address line of the first-layer first-type address line layer, or may be other amounts. Each first-type address line of said first-level first-type address line layer 41 coincides with a projection of a corresponding first-type address line of said third-level first-type address line layer 43 onto said first plane. That is, each first-type address line of the first-layer first-type address line layer 41 coincides with a projection of the first-type address line of the corresponding third-layer first-type address line layer 43 in the first plane and along the Y direction.

In practical applications, projections of each first-type address line of the first-layer first-type address line layer 41, each first-type address line of the second-layer first-type address line layer 42, and each first-type address line of the third-layer first-type address line layer 43 on the first plane and along the X direction may coincide, or a small amount of offset may exist.

In practical application, each first-type address line of the first-layer first-type address line layer 41 in a memory array block is connected with a third-layer first-type address line layer 43 right below the address line through a first connecting part 411; meanwhile, each third-type address line of the third first-type address line layer 43 is connected to a functional device corresponding to the address line through the third connection portion 431. I.e. the first type bit lines of two corresponding first type bit line layers of different layers are activated and controlled together. Each first-type address line of the second first-type address line layer 42 is connected to a functional device corresponding to the address line through a second connection portion 421.

Here, the first address line layer 44 of the two address line layers of the second type includes a plurality of address lines of the second type, and the first address line layer 44 of the second type may also be referred to as a top address line layer of the second type; the plurality of address lines of the second type of address line layer extend in the X direction and are arranged in a plurality of rows (the number of rows is related to the number of memory cells) in the Y direction. The second-layer second-type address line layer 45 in the two second-type address line layers comprises a plurality of second-type address lines, and the second-layer second-type address line layer 45 can also be called a bottom second-type address line layer; the plurality of second-type address lines of the second-layer second-type address line layer 45 extend in the X direction and are arranged in a plurality of rows (the number of rows is related to the number of memory cells) in the Y direction. Each second-type address line of the first-layer second-type address line layer 44 has the same length, each second-type address line of the second-layer second-type address line layer 45 has the same length, and each first-type address line of the first-layer second-type address line layer 44 has the same length as each second-type address line of the second-layer second-type address line layer 45.

Each of the address lines of the first layer and the second type 44 coincides with a projection of the corresponding address line of the second type 45 of the second layer on the first plane. That is, each second-type address line of the first-layer second-type address line layer 44 and the second-type address line of the corresponding second-layer second-type address line layer 45 have an offset in the projection in the first plane and along the X direction, and the offset may be about half the length of the second-type address line layer, or may be other amounts.

In practical applications, each address line of the second type of the first layer and second type of the address line layer 41 in one memory array block is connected to the corresponding functional device of the address line through a fourth connection portion (not shown in fig. 4). Each second-type address line of the second-layer second-type address line layer 42 is connected to the corresponding functional device of the address line through a fifth connection portion (not shown in fig. 4).

In practical applications, each of the four memory cell layers included in one memory array block is similar to each of the two stacked memory cell layers included in the aforementioned one memory array block, and thus, the description thereof is omitted here.

In some embodiments, the first type of address line layer comprises a bit line layer and the second type of address line layer comprises a word line layer. The phase change memory includes a memory cell array and peripheral circuits. In practical applications, the memory cell array includes at least one memory array block, and the peripheral circuit includes at least one functional device. In some embodiments, the functional device may include a decoder or a driver, and may specifically include a bit line decoder, a word line decoder, a bit line driver, and a word line driver. In practical application, in order to avoid insufficient driving force or excessive line loss, each bit line layer and each word line layer in one memory array block correspond to one functional device, that is, one functional device is responsible for activation control of all word lines and bit lines in one memory array block.

In practical applications, based on the phase change memory including the four stacked memory cell layers, the phase change memory may have a variety of functional devices in peripheral circuits, such as a layout manner of a decoder.

In practical applications, each memory array block of the phase change memory of the four-layer stacked memory cell layer includes two bit line decoders (a first layer of bit line layer and a third layer of bit line layer) and two word line decoders, the two bit line decoders are disposed on two bit line decoder regions, and the two word line decoders are disposed on two word line decoder regions.

In some embodiments, there is no offset between the two word line decoder regions and the two bit line decoder regions, and the specific distribution can refer to fig. 5a, 5 b. FIG. 5a is a partial horizontal schematic view of a phase change memory cell array having four stacked memory cells according to an embodiment of the present invention; FIG. 5b is a schematic diagram illustrating the distribution of word line decoder regions and bit line decoder regions of a phase change memory having four stacked memory cells according to an embodiment of the present invention. The distribution of the bit lines and word lines in fig. 5a can be understood by referring to the arrangement of the bit lines and word lines in fig. 4 described above.

As can be seen from fig. 5b, the two bit line decoder regions are aligned in the Y direction, the two word line decoder regions are aligned in the X direction, and there is no offset between the two word line decoder regions and the two bit line decoder regions in the Y direction.

It should be noted that fig. 5a and 5b are only examples of providing a phase change memory having four stacked memory cells, and are not intended to limit the structure of the phase change memory provided by the present invention. For example, in practical applications, the number of memory cells connected to each bit line is not limited to the number shown in fig. 5a and 5b, and can be adjusted according to practical situations, and accordingly, the number of bit lines and word lines in each memory array block is not limited to the number shown in fig. 5a and 5 b.

In other embodiments, there is an offset between the two word line decoder regions and the two bit line decoder regions, and the specific distribution can refer to fig. 6a to 6 d.

FIG. 6a is a first schematic diagram illustrating a bit line distribution of another phase change memory cell array having four stacked memory cells according to an embodiment of the present invention; FIG. 6b is a second schematic diagram illustrating a bit line distribution of another phase change memory cell array having four stacked memory cells according to an embodiment of the present invention; FIG. 6c is a schematic diagram illustrating a word line distribution of another phase change memory cell array having four stacked memory cells according to an embodiment of the present invention; FIG. 6d is a block diagram illustrating the distribution of word line decoder regions and bit line decoder regions of another phase change memory having four stacked memory cells according to an embodiment of the present invention.

The bit lines in fig. 6a can be understood with reference to the arrangement of the top first type address line layer and the bottom first type address line layer in fig. 4, which completely overlap as seen in the Z-direction, so that only one address line layer is shown in fig. 6 a.

The bit lines in fig. 6b can be understood with reference to the arrangement of the middle first-type address line layer in fig. 4.

The word lines in fig. 6c can be understood with reference to the arrangement of the top second type address line layer and the bottom second type address line layer in fig. 4.

As can be seen from fig. 6d, two bit line decoder regions are divided into a plurality of bit line sub-blocks, adjacent two of which are both offset in the Y direction, and two of which are divided into a plurality of word line sub-blocks, adjacent two of which are both offset in the X direction.

It should be noted that fig. 6a to 6d are only examples of providing a phase change memory having four stacked memory cells, and are not intended to limit the structure of the phase change memory provided by the present invention. For example, in practical applications, the number of memory cells connected to each bit line is not limited to the number shown in fig. 6a to 6d, and may be adjusted according to practical situations, and accordingly, the number of bit lines and word lines in each memory array block is not limited to the number shown in fig. 6a to 6 d. In some embodiments, the phase change memory comprises four stacked memory cell layers, and a top first type address line layer, a top second type address line layer, a middle first type address line layer, a bottom second type address line layer and a bottom first type address line layer which are sequentially distributed from top to bottom; the top first-type address line layer and the bottom first-type address line layer are provided with first-type address lines which are activated and controlled together;

the selected two memory cells include: a first memory cell coupled to the top first-type address line layer and the top second-type address line layer and a second memory cell coupled to the bottom first-type address line layer and the bottom second-type address line layer;

or,

Here, in the above phase change memory including four memory cell layers stacked, the phase change memory includes three first-type address line layers and two second-type address line layers; the three first-type address line layers and the two second-type address line layers are arranged at intervals; the first-type top address line layer, the second-type top address line layer, the first-type middle address line layer, the second-type bottom address line layer and the first-type bottom address line layer are sequentially arranged from top to bottom. The selected two memory cells include a first memory cell and a second memory cell. The first memory cell is positioned between the top first-type address line layer and the top second-type address line layer; the second memory cell is located between the bottom first-type address line layer and the bottom second-type address line layer.

In the architecture diagram of a four-layer stacked phase change memory cell array shown in fig. 4, the first type address line layer includes a bit line layer, and the second type address line layer includes a word line layer. It will be appreciated that the phase change memory comprises three

wordline layers

41, 42, 43 and two

wordline layers

44, 45; a top bit line layer 41, a top word line layer 44, a middle bit line layer 42, a bottom word line layer 45, and a bottom bit line layer 43 are sequentially disposed from top to bottom. The first bit line 41-1 in the top bit line layer 41 is electrically connected to the third bit line 43-1 in the bottom bit line layer 43 through the connection 411, so that the first bit line 41-1 and the third bit line 43-1 can be commonly activated and controlled.

FIG. 7a is a partial schematic view of a phase change memory cell array having four stacked memory cells along the Y direction according to an embodiment of the present invention; FIG. 7b is a partial schematic view of a phase change memory cell array having four stacked memory cells according to an embodiment of the present invention along the X direction; FIG. 7c is a partial schematic view of another phase change memory cell array having four stacked memory cells according to an embodiment of the invention, taken along the Z-direction.

For example, the first of the two selected memory cells may be located between the top bit line layer 41 and the top word line layer 44, as in position D in fig. 7 a; it is understood that there are a plurality of memory cells between the top bit line layer 41 and the top word line layer 44 in the phase change memory, and the memory cell at the D position is one of the plurality of memory cells that satisfy the defined condition (between the top bit line layer 41 and the top word line layer 44). Also, the second of the two memory cells selected is located between the bottom bit line layer 43 and the bottom word line layer 45, as in position a in fig. 7a, which is one of the plurality of memory cells that satisfy the defined condition (between the bottom bit line layer 43 and the bottom word line layer 45).

Illustratively, the first of the two memory cells selected may also be located between the top word line layer 44 and the middle bit line layer 42, as in position C in fig. 7 a; it is to be understood that there are a plurality of memory cells between the top word line layer 44 and the middle bit line layer 42 in the phase change memory, and the memory cell at the C-position is one of the plurality of memory cells that satisfy the defined condition (between the top word line layer 44 and the middle bit line layer 42). Likewise, the second of the two memory cells selected is located between bottom word line layer 45 and middle bit line layer 42, as in position B in fig. 7a, which is one of a plurality of memory cells that satisfy the defined condition (located between bottom word line layer 45 and middle bit line layer 42).

It should be noted that the A, B, C, D position can also refer to the A, B, C, D position shown in fig. 7 c.

It will be appreciated that the simultaneous read or write operations to selected two memory cells can double the data throughput compared to selecting only one memory cell in one memory array block in a phase change memory at a time.

In some embodiments, the first type of address line coupled to the first memory cell and the first type of address line coupled to the second memory cell are jointly actively controlled.

Here, the first type address line coupled to the first memory cell and the first type address line coupled to the second memory cell are commonly activated and controlled, which may be understood as that the bit lines coupled to the selected two memory cells are commonly activated and controlled.

Illustratively, as shown in FIG. 7b, the selected first memory cell may be located at an E-position between the top bit line layer and the top word line layer; the selected second memory cell may be located at a-position between the bottom bit line layer and the bottom word line layer. The bit line coupled to E and the bit line coupled to A are connected by a connection section and are controlled by common activation.

Illustratively, as shown in FIG. 7b, the selected first memory cell may be located at position F between the top word line layer and the middle bit line layer; the selected second memory cell may be located at a B-site between the middle bit line layer and the bottom word line layer. The bit line coupled to F and the bit line coupled to B are the same bit line, which must be controlled by common activation.

It will be appreciated that when two memory cells selected as described above are selected simultaneously, only one bit line may be activated. In some embodiments, during a simultaneous read operation or write operation on the two memory cells, a first voltage is applied to selected address lines of a first type coupled to the two memory cells; applying a second voltage to both selected second-type address lines coupled to the two memory cells; the first voltage is a negative voltage, and the second voltage is a positive voltage;

In practical applications, two memory cells in one memory array block in a phase change memory can be selected at a time for a read operation or a write operation. After the control logic receives the read operation or write operation command and the address data, the decoder (including the word line decoder and the bit line decoder) can determine to select the first-type address line and the second-type address line corresponding to the selected memory cell.

In practical applications, the drivers (including the word line driver and the bit line driver) may be used to generate corresponding voltages and apply the voltages to the corresponding first-type address lines or the second-type address lines.

In practical applications, the first voltage comprises a first voltage value-Vhh; the second voltage comprises a second voltage value Vhh; the third voltage comprises a third voltage value Vuw; the fourth voltage includes a fourth voltage value Vub. When the two selected memory cells are located at A, D in FIG. 7a, the voltages applied to the bit lines and word lines can be referred to in Table 1; when the two selected memory cells are located at B, C in fig. 7a, the voltages applied to the respective bit lines and word lines can be referred to in table 2.

It should be noted that the first stacked layer where the a position shown in table 1 and table 2 is located can be understood as the memory cell layer 59 coupled to the third layer of the first type address line layer 43 and the second layer of the second type address line layer 45 in fig. 4; the second stack layer in which the B site is located can be understood as the memory cell layer 58 coupled to the second layer first type address line layer 42 and the second layer second type address line layer 45 in fig. 4; the third stacked layer in which the C-site is located can be understood as a memory cell layer 57 coupled to the second layer of the first type address line layer 42 and the first layer of the second type address line layer 44 in fig. 4; the fourth stacked layer in which the D-site is located can be understood as a memory cell layer 56 in fig. 4 coupled to the first layer of the first type address line layer 41 and the first layer of the second type address line layer 44.

TABLE 1

TABLE 2

In this way, under the action of the first voltage, the second voltage, the third voltage and the fourth voltage, the voltage difference applied to the first-type address lines and the second-type address lines corresponding to the selected two memory cells is greater than the threshold voltage of the selector of the selected two memory cells, and the voltage difference applied to the first-type address lines and the second-type address lines corresponding to all unselected memory cells in the selected memory array block is less than the threshold voltage.

Here, the threshold voltage of the selector may include a critical voltage at which the selector is turned on. In practical applications, the specific value of the threshold voltage is related to the material and structure of the selector.

In practical application, during the process of simultaneously reading the two memory cells, the storage states of the two memory cells are obtained by sensing the change of the voltage on the second-type address line.

It is understood that, during the read operation of the phase change memory, since the bit lines (address lines of the first type) controlled by common activation exist in the bit line layers (address line layers of the first type) of different layers, there may be read disturb in obtaining the memory states of the two memory cells by sensing the voltage change on the bit lines, so that the read data is inaccurate. And the storage states of the two storage units are obtained by sensing the change of the voltage on the word line (the second-class address line), so that no read interference exists, and the correctness of read data can be ensured.

In practical application, in the process of simultaneously performing write operation on the two memory cells, a two-bit binary mode is adopted for writing.

It will be appreciated that a one-bit binary typically scales data with two states, 0 and 1; the two-bit binary scale measures the data using four states, 00, 01, 10, and 11. Here, in the process of simultaneously performing the write operation on the two memory cells, it can be performed according to four states of a two-bit binary system. That is, a mixed mode of crystalline and amorphous states can be used to program a selected two different memory cells simultaneously.

The control method of the phase change memory provided by the embodiment of the invention selects two memory cells in one memory array block of the phase change memory; the phase change memory comprises a plurality of first address line layers and second address line layers which are arranged at intervals, and a storage unit layer positioned between the first address line layers and the second address line layers; the first address line layer comprises a plurality of first address lines extending along a first direction; the second-type address line layer comprises a plurality of second-type address lines extending along a second direction perpendicular to the first direction; the memory cell layer includes a plurality of memory cells, each of the plurality of memory cells coupled to first-type address lines and second-type address lines adjacent to the respective memory cell; the first-type address lines which are activated and controlled commonly exist in the first-type address line layers of different layers; the two selected memory cells include two memory cells coupled to a second type of address line in a second type of address line layer of a different layer; and simultaneously performing reading operation or writing operation on the two storage units. In the embodiment of the invention, two memory cells in one memory array block in the phase change memory can be selected at one time to simultaneously perform read operation or write operation, so that two memory cells in the phase change memory can be simultaneously accessed at one time. In this way, it is possible to improve access efficiency when a read operation or a write operation is performed on a multi-layer stacked phase change memory greater than two layers.

In order to implement the method according to the embodiment of the present invention, an embodiment of the present invention further provides a control apparatus for a phase change memory, fig. 8 is a schematic structural diagram of an apparatus according to an embodiment of the present invention, and as shown in fig. 8, the control apparatus 800 for a phase change memory includes: a selection unit 801 and a processing unit 802, wherein:

the selection unit 801 is used for selecting two memory cells in one memory array block of the phase change memory; the phase change memory comprises a plurality of first address line layers and second address line layers which are arranged at intervals, and a storage unit layer positioned between the first address line layers and the second address line layers; the first address line layer comprises a plurality of first address lines extending along a first direction; the second-type address line layer comprises a plurality of second-type address lines extending along a second direction perpendicular to the first direction; the memory cell layer includes a plurality of memory cells, each of the plurality of memory cells coupled to first-type address lines and second-type address lines adjacent to the respective memory cell; the first-type address lines which are activated and controlled commonly exist in the first-type address line layers of different layers; the selected two memory cells include two memory cells coupled to a second type of address line in a second type of address line layer of a different layer.

Wherein, in some embodiments, selecting two memory cells in one memory array block of the phase change memory comprises selecting a first memory cell in one memory array block of the phase change memory and selecting a second memory cell in one memory array block of the phase change memory.

The processing unit 802 performs a read operation or a write operation on the two memory cells simultaneously.

In practical applications, the selection unit 801 and the processing unit 802 may be implemented by a processor in a control device of the phase change memory.

In some embodiments, the phase change memory comprises four stacked memory cell layers, and a top first type address line layer, a top second type address line layer, a middle first type address line layer, a bottom second type address line layer and a bottom first type address line layer which are sequentially distributed from top to bottom; when the first address line type controlled by common activation exists in the top first address line type layer and the bottom first address line type layer,

In some embodiments, the processing unit 802 is further configured to apply a first voltage to a selected first type address line coupled to the two memory cells during a simultaneous read operation or write operation on the two memory cells; applying a second voltage to both selected second-type address lines coupled to the two memory cells; the first voltage is a negative voltage, and the second voltage is a positive voltage;

In some embodiments, the processing unit 802 is further configured to obtain the storage states of the two memory cells by sensing the change of the voltage on the second type address line during the simultaneous read operation of the two memory cells.

In some embodiments, the processing unit 802 is further configured to perform writing in a two-bit binary manner during the simultaneous writing operation on the two memory cells.

It should be noted that: in the above-mentioned embodiment, when performing the control read operation of the phase change memory, the control device of the phase change memory is only illustrated by the division of the program modules, and in practical applications, the above-mentioned processing may be distributed to be completed by different program modules according to needs, that is, the internal structure of the device is divided into different program modules to complete all or part of the above-mentioned processing. In addition, the control device of the phase change memory provided in the above embodiments and the control method embodiment of the phase change memory belong to the same concept, and the specific implementation process thereof is described in the method embodiment and is not described herein again.

Based on the hardware implementation of the program module, and in order to implement the method according to the embodiment of the present invention, the embodiment of the present invention provides a control apparatus 900 for a phase change memory, as shown in fig. 9, the control apparatus 900 for a phase change memory includes: a processor 901 and a memory 902 configured to store a computer program operable on the processor, wherein:

the processor 901 is configured to execute the method provided by one or more of the above technical solutions when running the computer program.

In practical applications, as shown in fig. 9, various components in the control device 900 of the phase change memory are coupled together through a bus system 903. It will be appreciated that the bus system 903 is used to enable communications among the components. The bus system 903 includes a power bus, a control bus, and a status signal bus in addition to a data bus. For clarity of illustration, however, the various buses are labeled as the bus system 903 in FIG. 9.

In an exemplary embodiment, the present invention further provides a storage medium, which is a computer readable storage medium, such as a memory 902 including a computer program, which can be executed by a processor 901 of a control apparatus 900 of a phase change memory to implement the steps of the foregoing method. The computer-readable storage medium may be any medium that can store program codes, such as a removable storage device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A method of controlling a phase change memory, comprising:

2. The method of claim 1, wherein the phase change memory comprises four stacked memory cell layers, and a top first address line layer, a top second address line layer, a middle first address line layer, a bottom second address line layer and a bottom first address line layer, which are sequentially arranged from top to bottom; the top first-type address line layer and the bottom first-type address line layer are provided with first-type address lines which are activated and controlled together;

3. The method of claim 1, wherein the phase change memory comprises four stacked memory cell layers, and a top first address line layer, a top second address line layer, a middle first address line layer, a bottom second address line layer and a bottom first address line layer, which are sequentially arranged from top to bottom; the top first-type address line layer and the bottom first-type address line layer are provided with first-type address lines which are activated and controlled together;

4. A method as claimed in claim 2 or 3, characterized in that the address lines of the first type coupled to the first memory element and the address lines of the first type coupled to the second memory element are jointly activated to be controlled.

5. A method as claimed in claim 2 or 3, characterized in that during a simultaneous read or write operation on the two memory cells, a first voltage is applied to both selected address lines of a first type coupled to the two memory cells; applying a second voltage to both selected second-type address lines coupled to the two memory cells; the first voltage is a negative voltage, and the second voltage is a positive voltage;

6. The method of claim 1, wherein the memory states of the two memory cells are obtained by sensing a change in voltage on the second type address line during a simultaneous read operation of the two memory cells.

7. The method of claim 1, wherein during the simultaneous write operation to the two memory cells, the writing is performed in a two-bit binary manner.

8. A control apparatus for a phase change memory, comprising:

9. A control apparatus for a phase change memory, comprising: a processor and a memory configured to store a computer program operable on the processor;

wherein the processor is adapted to perform the steps of the method of any one of claims 1 to 7 when running the computer program.

10. A storage medium having a computer program stored thereon, the computer program, when being executed by a processor, performing the steps of the method of any one of claims 1 to 7.