CN113241813A - Intelligent load identification circuit and method and photovoltaic power generation system - Google Patents

Intelligent load identification circuit and method and photovoltaic power generation system Download PDF

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Publication number
CN113241813A
CN113241813A CN202110464790.9A CN202110464790A CN113241813A CN 113241813 A CN113241813 A CN 113241813A CN 202110464790 A CN202110464790 A CN 202110464790A CN 113241813 A CN113241813 A CN 113241813A
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China
Prior art keywords
circuit
voltage
power supply
load
power
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CN202110464790.9A
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Chinese (zh)
Inventor
陈萼
唐春国
王冬梅
张慧慧
胡学潮
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Shenzhen Lemi Technology Development Co ltd
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Shenzhen Lemi Technology Development Co ltd
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Priority to CN202110464790.9A priority Critical patent/CN113241813A/en
Publication of CN113241813A publication Critical patent/CN113241813A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00302—Overcharge protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0063—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with circuits adapted for supplying loads from the battery
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/35—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering with light sensitive cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

The application relates to the field of photovoltaic energy storage equipment, in particular to an intelligent load identification circuit, a method and a photovoltaic power generation system, wherein the intelligent load identification circuit comprises a control circuit, a power supply circuit and a load interface, the power supply circuit comprises a power input end used for receiving electric energy and a first power output end, the first power output end is connected to the control circuit, a sampling circuit is connected between the control circuit and the load interface, and the sampling circuit is used for detecting voltage and/or current output by an external load received by the load interface; the power supply circuit further comprises a second power supply output end, a switch circuit is connected between the second power supply output end and the load interface, the switch circuit is connected with the control circuit, and the switch circuit is used for controlling the power supply circuit to be connected with or disconnected from a circuit between the load interface. The application has the effect of improving the safety of external load charging.

Description

Intelligent load identification circuit and method and photovoltaic power generation system
Technical Field
The application relates to the field of photovoltaic off-grid energy storage equipment, in particular to an intelligent load identification circuit and method and a photovoltaic power generation system.
Background
At present, a photovoltaic power generation system is widely applied due to the characteristics of cleanness, safety, convenience, high efficiency and the like of solar photovoltaic power generation.
In the related art, a photovoltaic power generation system generates power through a solar panel and stores electric energy in a storage battery, the solar panel and the storage battery jointly form a photovoltaic power generation module and serve as an external load charging power supply, and a charging interface of an external load is connected with a load interface of the photovoltaic power generation system, so that the external load can be charged.
In view of the above-mentioned related art, the inventor believes that if the external load is not provided with the charging protection circuit, the charging interface of the external load may output voltage and current to the outside, and the charging limit voltage of the external load is lower than the output voltage of the load interface, and during the process of charging the external load using the load interface, the external load may be overcharged, so that there is a possibility of explosion, and there is a safety hazard.
Disclosure of Invention
In order to improve the charging safety of an external load, the application provides an intelligent load identification circuit and method and a photovoltaic power generation system.
In a first aspect, the present application provides an intelligent load identification circuit, which adopts the following technical scheme:
an intelligent load identification circuit comprises a control circuit, a power supply circuit and a load interface, wherein the power supply circuit comprises a power input end for receiving electric energy and a first power output end, the first power output end is connected to the control circuit, a sampling circuit is connected between the control circuit and the load interface, and the sampling circuit is used for detecting voltage and/or current output by an external load received by the load interface;
the power supply circuit further comprises a second power supply output end, a switch circuit is connected between the second power supply output end and the load interface, the switch circuit is connected with the control circuit, and the switch circuit is used for controlling the power supply circuit to be connected with or disconnected from a circuit between the load interface.
By adopting the technical scheme, when the external load is charged, the control circuit controls the switch circuit to be switched off; if the external load is not provided with the charging protection circuit, the charging interface of the external load outputs voltage and current to the outside, the sampling circuit detects that the voltage and/or the current exist in the load interface, and the control circuit continues to control the switch circuit to be disconnected, so that the circuit between the power supply circuit and the load interface is disconnected, and the power supply circuit cannot charge the external load; if the external load is provided with the charging protection circuit, the charging interface of the external load does not output voltage and current to the outside, the control circuit controls the switching circuit to be switched on and communicates a circuit between the power supply circuit and the load interface, so that the power supply circuit charges the external load. Therefore, by additionally arranging the switch circuit and the sampling circuit, the possibility of overcharging the external load can be reduced, and the charging safety of the external load is improved.
Optionally, the switch circuit includes a MOS transistor T11, a gate of the MOS transistor T11 is connected to the signal output terminal of the control circuit, a drain of the MOS transistor T11 is connected to the load interface, and a source of the MOS transistor T11 is connected to the second power output terminal of the power supply circuit.
By adopting the technical scheme, the control circuit outputs a high-level signal, the grid voltage of the MOS tube T11 is pulled high, the drain and the source of the MOS tube T11 are conducted, and the power supply circuit is conducted with the load interface. The control circuit outputs a low level signal, the voltage of the grid electrode of the MOS tube T11 is pulled low, the drain electrode and the source electrode of the MOS tube T11 are disconnected, and the power supply circuit is disconnected with the load interface. The high-low level signal output by the control circuit controls the on-off of the MOS transistor T11, and further controls the on-off of a circuit between the power supply circuit and the load interface.
Optionally, the sampling circuit includes:
the voltage sampling circuit is used for detecting whether the load interface receives the voltage output by the external load or not;
and the current sampling circuit is used for detecting whether the load interface receives the current output by the external load.
By adopting the technical scheme, the voltage sampling circuit can be arranged to sample the voltage of the load interface, or the current sampling circuit can be arranged to sample the current of the load interface, and the voltage sampling circuit and the current sampling circuit can be arranged to sample the voltage and the current of the load interface.
Optionally, the power supply circuit further includes a voltage reduction circuit, a voltage input end of the voltage reduction circuit is connected to a power input end of the power supply circuit, and a voltage output end of the voltage reduction circuit is connected to a second power output end of the power supply circuit.
By adopting the technical scheme, the voltage reduction circuit is used for reducing the voltage of the power supply voltage, so that the voltage at the load interface meets the use requirement of a user.
Optionally, the voltage-reducing circuit includes a voltage-reducing chip U3 and a feedback circuit, a voltage input terminal of the voltage-reducing chip U3 is connected to the power input terminal of the power supply circuit, and a voltage output terminal of the voltage-reducing chip U3 is connected to the second power output terminal of the power supply circuit;
the voltage reduction chip U3 comprises a current feedback end, a voltage feedback end and a voltage output end, and the feedback circuit is respectively connected to the current feedback end, the voltage feedback end and the voltage output end.
Through adopting above-mentioned technical scheme, set up feedback circuit for step-down chip, not only can carry out step-down processing to supply voltage, can guarantee the voltage output of constant current constant voltage moreover.
Optionally, a first diode D1 is connected in series between the power input end of the power supply circuit and the voltage input end of the voltage reduction circuit, an anode end of the first diode D1 is connected to the power input end of the power supply circuit, and a cathode end of the first diode D1 is connected to the voltage input end of the voltage reduction circuit.
Through adopting above-mentioned technical scheme, set up first diode D1 between supply circuit and step-down circuit, can reduce the possibility that the electric current flows in reverse, and then reduce the possibility that the electronic component of supply circuit's power input one side damaged, play the guard action.
Optionally, a filter circuit is connected between the cathode terminal of the first diode D1 and the analog ground GND.
By adopting the technical scheme, clutter in the direct current power supply can be filtered by the filter circuit, so that the direct current voltage input of the voltage input end of the voltage reduction circuit is more stable.
Optionally, the power supply circuit further includes a voltage stabilizing circuit, a voltage input end of the voltage stabilizing circuit is connected to a power input end of the power supply circuit, and a voltage output end of the voltage stabilizing circuit is connected to a first power output end of the power supply circuit.
By adopting the technical scheme, the mutual interference between the control circuit power supply circuit and the voltage reduction circuit can be effectively reduced, and stable working voltage input is provided for the control circuit.
In a second aspect, the present application provides a photovoltaic power generation system, which adopts the following technical solution:
a photovoltaic power generation system comprises the intelligent load identification circuit and a photovoltaic power generation module, wherein a power input end of a power supply circuit is connected to the photovoltaic power generation module.
By adopting the technical scheme, when the photovoltaic power generation system charges the load, the control circuit controls the switch circuit to be switched off; if the charging interface of the external load outputs voltage and current to the outside, the sampling circuit detects that the voltage and/or the current exist in the load interface, and the control circuit continues to control the switch circuit to be disconnected, so that the circuit between the power supply circuit and the load interface is disconnected, and the power supply circuit cannot charge the load; if the charging interface of the external load does not output voltage and current to the outside, the control circuit controls the switching circuit to be conducted, and the circuit between the power supply circuit and the load interface is communicated, so that the power supply circuit charges the external load. Therefore, by additionally arranging the switching circuit and the sampling circuit in the photovoltaic power generation system, the external load can be prevented from being overcharged, so that the charging safety of the external load is improved.
In a third aspect, the present application provides an intelligent load identification method using the intelligent load identification circuit of the first aspect, which adopts the following technical solution:
an intelligent load identification method, comprising:
the control circuit controls the switch circuit to be switched off;
after the switch circuit is switched off, the control circuit detects whether the load interface receives the voltage and/or the current output by the external load through a sampling circuit;
if not, the control circuit controls the switch circuit to be conducted, and meanwhile, the control circuit starts timing and records the current timing value;
and judging whether the current timing value is equal to a preset value or not, if so, returning to the step that the control circuit controls the switching circuit to be switched off.
By adopting the technical scheme, when the external load is charged, the control circuit controls the switch circuit to be switched off; if the external load is not provided with the charging protection circuit, the charging interface of the external load outputs voltage and current to the outside, the sampling circuit detects that the voltage and/or the current exist in the load interface, and the control circuit continues to control the switch circuit to be disconnected, so that the circuit between the power supply circuit and the load interface is disconnected, and the power supply circuit cannot charge the external load; if the external load is provided with the charging protection circuit, the charging interface of the external load does not output voltage and current to the outside, and the control circuit controls the switching circuit to be conducted to communicate a circuit between the power supply circuit and the load interface, so that the power supply circuit charges the external load; and meanwhile, the control circuit starts timing and records the current timing value, and after the current timing value is equal to the preset value, the control circuit controls the switching circuit to be switched off and detects whether voltage and/or current exist at the interface of the load. By additionally arranging the switching circuit and the sampling circuit and circularly timing and judging, the external load without the protection circuit is prevented from being charged, and the charging safety of the external load is improved.
In summary, the present application includes at least one of the following beneficial technical effects:
1. if the external load is not provided with the charging protection circuit, the charging interface of the load outputs voltage and current to the outside, the sampling circuit detects that the voltage and/or the current exist in the load interface, and the control circuit continues to control the switch circuit to be disconnected, so that the circuit between the power supply circuit and the load interface is disconnected, and the power supply circuit cannot charge the external load; if the external load is provided with the charging protection circuit, the charging interface of the external load does not output voltage and current to the outside, the control circuit controls the switching circuit to be switched on and communicates a circuit between the power supply circuit and the load interface, so that the power supply circuit charges the load. Therefore, the switching circuit and the sampling circuit are additionally arranged, so that the external load can be prevented from being overcharged, and the charging safety of the external load is improved;
2. the high-low level signal output by the control circuit controls the on-off of the MOS transistor T11, and further controls the on-off of a circuit between the power supply circuit and the load interface.
Drawings
Fig. 1 is a block diagram of a smart load identification circuit according to an embodiment of the present application.
Fig. 2 is a circuit schematic diagram of a sampling circuit, a switching circuit, and a control circuit according to an embodiment of the present application.
Fig. 3 is a circuit schematic diagram of a power supply circuit of an embodiment of the present application.
Fig. 4 is a block diagram of a photovoltaic power generation system according to an embodiment of the present application.
Fig. 5 is a flowchart illustrating an intelligent load identification method according to an embodiment of the present application.
Description of reference numerals: 101. a control circuit; 102. a power supply circuit; 1021. a voltage reduction circuit; 10211. a feedback circuit; 1022. a filter circuit; 1023. a voltage stabilizing circuit; 10231. a triode voltage stabilizing circuit; 103. a load interface; 104. a sampling circuit; 1041. a voltage sampling circuit; 1042. a current sampling circuit; 105. a switching circuit; 201. provided is a photovoltaic power generation module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to fig. 1-5 and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The embodiment of the application discloses an intelligent load identification circuit. Referring to fig. 1, the smart load identification circuit includes a control circuit 101, a power supply circuit 102, a load interface 103, a sampling circuit 104, and a switching circuit 105.
In this embodiment, the power supply circuit 102 includes a power input terminal VCC, a first power output terminal, and a second power output terminal S. A first output end of the power supply circuit 102 is connected with a power supply input end of the control circuit 101, and a second power supply output end S of the power supply circuit 102 is connected with the load interface 103 through the switch circuit 105; the load interface 103 is also connected to the control circuit 101 via a sampling circuit 104.
Referring to fig. 2, the control circuit 101 includes a control chip U1, and the control chip U1 may be a chip of model N76E003AT 20.
As an alternative to this embodiment, referring to fig. 3, the power supply circuit 102 includes a voltage stabilizing circuit 1023. The voltage input terminal of the voltage stabilizing circuit 1023 is connected to the power input terminal VCC of the power supply circuit 102, and the voltage output terminal of the voltage stabilizing circuit 1023 is connected to the first power output terminal VCC of the power supply circuit 102.
In this alternative embodiment, the voltage stabilizing circuit 1023 includes a triode 10231 and a three-terminal regulator U2. The power supply voltage received by the power input end VCC is regulated to 10V through the voltage-stabilizing triode circuit 10231, and then is converted by the three-terminal voltage-stabilizing tube U2 to output 5V voltage, and the 5V voltage is transmitted to the control circuit 101 through the first power output end to provide working voltage for the control chip U1.
Further, referring to fig. 2 and 3, the voltage stabilizing triode circuit 10231 includes a triode T1 and a voltage stabilizing diode D2, a second diode D3 and a first resistor R1 are connected in series with a collector of the triode T1, an anode terminal of the second diode D3 is connected to a voltage input terminal of the voltage stabilizing circuit 1023, a cathode terminal of the second diode D3 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to a collector of the triode T1. The base electrode of the triode T1 is connected with the cathode terminal of the voltage stabilizing diode D2, and the anode terminal of the voltage stabilizing diode D2 is connected with the analog ground GND; a second resistor R2 is connected between the base and the collector of the transistor T1.
The second resistor R2 and the zener diode D3 in the zener triode 10231 form a basic circuit for voltage regulation, a stable voltage is obtained at the zener diode D3, the base of the triode T1 is connected to the cathode of the zener diode D3 to form an emitter follower, and the emitter voltage of the triode T1 is the voltage following the base, so that a stable voltage can be output at the emitter of the triode T1.
An emitting electrode of the triode T1 is connected with an input end (pin 3) of a three-terminal voltage regulator tube U2; the common end (pin 1) of the three-terminal regulator tube U2 is connected to the analog ground GND, the output end (pin 1) of the three-terminal regulator tube U2 is connected to the first power output end, the first power output end is connected to the 4 th pin of the control chip U1, and the control chip U1 is powered by 5V voltage.
7805 three-terminal regulator is selected as the three-terminal regulator U2. The three-terminal regulator tube U2 has the characteristics of low power consumption, low voltage drop and high precision, and can provide stable 5V voltage while reducing loss.
Further, a first capacitor C1 is connected between a connection point of the first resistor R1 and the collector of the transistor T1 and the analog ground GND. A second capacitor C2 and a third capacitor C3 are connected in parallel between the emitter of the triode T1 and the anode terminal of the zener diode D2, and the first capacitor C1, the second capacitor C2 and the third capacitor C3 all play a role in filtering. A fourth capacitor C4 and a fifth capacitor C5 are connected in parallel between the common end of the three-terminal regulator tube U2 and the output end of the three-terminal regulator tube U2, and similarly, the fourth capacitor C4 and the fifth capacitor C5 both play a role in filtering.
As an alternative implementation manner of this embodiment, referring to fig. 3, the power supply circuit 102 includes a voltage dropping circuit 1021, a voltage input terminal of the voltage dropping circuit 1021 is connected to the power input terminal VCC of the power supply circuit 102, and a voltage output terminal of the voltage dropping circuit 1021 is connected to the second power output terminal S of the power supply circuit 102.
In this optional embodiment, the voltage-reducing circuit 1021 includes a voltage-reducing chip U3, and the selectable type of the voltage-reducing chip U3 is a synchronous voltage-reducing DC-DC controller of CX 8812. A voltage input end of the voltage reduction circuit 1021 is connected with the 3 rd pin of the voltage reduction chip U3 through the third resistor R3 and the eighth capacitor C8 in sequence; the 4 th pin of the buck chip U3 is connected to the voltage input terminal of the buck circuit 1021; the 5 th pin and the 6 th pin of the buck chip U3 are both 5V voltage output pins, and only the 5 th pin is used in this embodiment; the 7 th and 8 th pins of the buck chip U3 are connected to the analog ground GND.
The voltage dropping circuit 1021 further includes a third diode D4, the 5 th pin of the voltage dropping chip U3 is connected to the cathode terminal of the third diode D4, and the anode terminal of the third diode D4 is connected to the analog ground GND; the cathode terminal of the third diode D4 is connected to the analog ground GND after being connected to the fourth resistor R4 and the ninth capacitor C9 in sequence. The third diode D4 provides a freewheeling circuit for the output pin of the buck chip U3, which acts as a freewheeling circuit, and the ninth capacitor C9 can prevent the third diode D4 from being damaged due to an excessively large peak.
Further, referring to fig. 3, the voltage dropping circuit 1021 further includes a feedback circuit 10211, and the feedback circuit 10211 includes a first inductor L1, a fifth resistor R5, and a sixth resistor R6. One end of the first inductor L1 is connected to the 5 th pin of the buck chip U3, the other end of the first inductor L1 is connected to the voltage output end of the buck circuit 1021 through a sixth resistor R6, the voltage output end of the buck circuit 1021 is the second power output end S of the power supply circuit 102, and the fifth resistor R5 is connected in parallel to the sixth resistor R6. The sixth resistor R6 is connected to one end of the first inductor L1 and is also connected to the 2 nd pin of the buck chip U3; the connection point of the sixth resistor R6 and the fifth resistor R5 is connected to the 1 st pin of the buck chip U3.
The voltage reduction chip U3 utilizes the feedback circuit 10211, relies on the internal constant voltage control loop to stabilize the output voltage at 5V, detects the output current through the voltage difference between the 1 st pin and the 2 nd pin, and relies on the internal constant current control loop to adjust the current output, so that the output current value is a preset value, and the voltage output end of the voltage reduction circuit 1021 can output constant voltage and constant current.
A twelfth capacitor C12 and a thirteenth capacitor C13 are connected in parallel between the voltage output terminal of the voltage-reducing circuit 1021 and the analog ground GND, and the twelfth capacitor C12 and the thirteenth capacitor C13 are used for filtering noise, so that the dc output of the voltage output terminal of the voltage-reducing circuit 1021 is more stable.
Further, referring to fig. 3, one end of the third resistor R3 far from the eighth capacitor C8 is connected with a first diode D1, a cathode end of the first diode D1 is connected with the third resistor R3, and an anode end of the first diode D1 is connected with the power input terminal VCC.
When a current flows from the power supply circuit 102 to the voltage step-down circuit 1021, the first diode D1 is in an on state; when the current flows from the voltage dropping circuit 1021 to the power supply circuit 102, the first diode D1 is turned off, so that the first diode D1 can prevent the current from flowing backward, reduce the possibility of damaging the electrical components connected to the power input terminal VCC, and protect the electrical components. The first diode D1 can be a SS34 diode.
Further, the power supply circuit 102 further includes a filter circuit 1022. The filtering circuit 1022 includes a sixth capacitor C6 and a seventh capacitor C7 connected in parallel; one end of the sixth capacitor C6 is connected to the cathode of the first diode D1, the other end of the sixth capacitor C6 is connected to the analog ground GND, and the sixth capacitor C6 and the seventh capacitor C7 are used to filter noise, so that the dc input of the voltage dropping circuit 1021 is more stable.
As an alternative implementation manner of this embodiment, referring to fig. 2 and fig. 3, the switch circuit 105 includes a MOS transistor T11, a source of the MOS transistor T11 is connected to the second power output terminal S, a drain of the MOS transistor T11 is connected to the anode a + of the load interface 103, a seventh resistor R7 is connected in series between a gate of the MOS transistor T11 and the 12 th pin of the control chip U1, the gate of the MOS transistor T11 is further electrically connected to a pull-up resistor R22, and the other end of the pull-up resistor R22 is electrically connected to the first power output terminal of the power supply circuit 102, that is, the output terminal of the three-terminal regulator U2.
The high level signal output by the control chip U1 at the 12 th pin is not enough to turn on the drain and source terminals of the MOS transistor T11, but after the pull-up resistor R22 is provided at the gate of the MOS transistor T11, the control chip U1 outputs the high level signal at the 12 th pin to turn on the drain and source terminals of the MOS transistor T11, and the control chip U1 outputs the low level signal at the 12 th pin to turn off the drain and source terminals of the MOS transistor T11.
The MOS transistor T11 is driven by voltage, and the gate current is small, but because a parasitic capacitance exists inside the gate of the MOS transistor T11, when the control chip U1 controls the MOS transistor T11 to be turned on or off, a large instantaneous current is generated, the seventh resistor R7 and the parasitic capacitance may form an RC charging and discharging circuit, so as to reduce the current value of the instantaneous current, and further reduce the possibility that the instantaneous current damages the control chip U1.
As an alternative implementation of this embodiment, referring to fig. 2 and 3, the sampling circuit 104 includes a voltage sampling circuit 1041 and a current sampling circuit 1042. The voltage sampling circuit 1041 comprises an eighth resistor R8 and a ninth resistor R9, one end of the eighth resistor R8 is connected with the positive pole a + of the load interface 103, the other end of the eighth resistor R8 is connected with the ninth resistor R9, and the other end of the ninth resistor R9 is connected with the negative pole a-of the load interface 103; the connection point of the eighth resistor R8 and the ninth resistor R9 is connected with the 5 th pin of the control chip U1, the connection point of the eighth resistor R8 and the ninth resistor R9 is also connected with a tenth capacitor C10, and the other end of the tenth capacitor C10 is connected with the negative pole A-of the load interface 103.
The current sampling circuit 1042 includes a tenth resistor R10 and a thirteenth resistor R13, one end of the tenth resistor R10 is connected to the negative a of the load interface 103, the other end is connected to the analog ground GND, and both ends of the tenth resistor R10 are connected in parallel to an eleventh resistor R11 and a twelfth resistor R12; one end of the thirteenth resistor R13 is connected to the negative pole A-of the load interface 103, and the other end is connected to the 14 th pin of the control chip U1; an eleventh capacitor C11 is connected to a connection point of the thirteenth resistor R13 and the 14 th pin of the control chip U1, and the other end of the eleventh capacitor C11 is connected to the analog ground GND.
The resistors in the voltage sampling circuit 1041 and the current sampling circuit 1042 are high-precision resistors with an error of less than one percent, so that the possibility of wrong sampling by the sampling circuit 104 is reduced when the voltage sampling circuit 1041 and the current sampling circuit 1042 sample the voltage and the current of the load interface 103 accurately; in addition, the tenth capacitor C10 and the eleventh capacitor C11 perform a filtering function, so that the sampled value is more accurate.
In this embodiment, referring to fig. 2, the load interface 103 may be set as a USB interface J1, an auxiliary load R14 may be connected between the positive electrode a + and the negative electrode a-of the USB interface J1, and the auxiliary load R14 makes the 5V voltage output by the USB interface J1 more stable, so as to reduce the possibility of external load damage caused by unstable output voltage of the USB interface J1.
Further, referring to fig. 2, a PTC thermistor is connected in series between the positive electrode a + of the USB interface J1 and the drain of the MOS transistor T11, the PTC thermistor is a protection element, when the current is abnormal, the temperature value rises and exceeds the limit value of the PTC thermistor, the PTC thermistor can be automatically disconnected, and when the current returns to normal, the PTC thermistor can automatically reset, and the PTC thermistor can play a role in overload protection and circuit protection.
For example: when a circuit at the USB interface J1 is in short circuit, the current can be increased after the circuit is in short circuit, the heat generated by the PTC thermistor can be increased after the current is increased, the temperature is increased and exceeds the defined value of the PTC thermistor, and at the moment, the resistance value of the PTC thermistor can be rapidly increased infinitely, so that the current is blocked, and the protection effect is achieved; when the current value returns to normal, the temperature drops, the resistance value of the PTC thermistor returns to normal, and the PTC thermistor automatically resets.
If the sampling circuit 104 and the switch circuit 105 are not arranged, the external load cannot be identified, the power supply circuit 102 is used for charging the external load which can output voltage and current to the outside, the external load is in an overcharged state, potential safety hazards exist, and the external load is easy to explode and the like. However, the detection and control chip U1 of the sampling circuit 104 can automatically control the on/off of the switch circuit 105, intelligently identify the external load and automatically control whether the external load is not charged.
For example: the external load such as the miner lamp is not provided with the charging protection circuit, the voltage and the current can be directly output outwards through the charging interface, the built-in power supply voltage of the miner lamp is low, at the moment, the control chip U1 can detect the voltage and the current existing in the load interface 103 through the sampling circuit 104, the control chip U1 controls the switch circuit 105 to be continuously switched off, the external load which can output the voltage and the current outwards is prevented from being charged, and the possibility of explosion of the external load is reduced. When an external load such as a mobile phone is charged, because a charging protection circuit is arranged in the external load such as the mobile phone, voltage and current cannot be output outwards at a charging interface, the control circuit 101 cannot detect the voltage and the current, and the control circuit 101 controls the switch circuit 105 to be switched on, so that the power supply circuit 102 can charge the external load of which the charging interface cannot output the voltage and the current outwards.
The implementation principle of the intelligent load identification circuit in the embodiment of the application is as follows: a user connects a charging interface of an external load to a load interface 103, a control chip U1 sends a low level signal to a MOS tube T11 to control the disconnection of the MOS tube T11, and further control a power supply circuit 102 to be incapable of being communicated with the load interface 103, meanwhile, the control chip U1 detects the load interface 103 through a sampling circuit 104, when voltage and/or current exist in the load interface 103, the control chip U1 receives the voltage and/or current signal, the control chip U1 continues to control the disconnection of the MOS tube T11, the power supply circuit 102 is not communicated with the load interface 103, and the user cannot charge the external load through the load interface 103; when the load interface 103 does not have voltage and/or current, the control chip U1 cannot detect the voltage and/or current, the control chip U1 outputs a high level signal to the MOS transistor T11 to control the MOS transistor T11 to be turned on, so as to control the power supply circuit 102 to be communicated with the load interface 103, a user can use the load interface 103 to charge an external load, and by automatically controlling whether the load interface 103 is powered on, the power supply circuit 102 is prevented from charging the external load, which outputs the voltage and the current, to the external load through the charging interface, so that the possibility of overcharge is reduced.
The embodiment of the application also discloses a photovoltaic power generation system. Referring to fig. 4, the photovoltaic power generation system includes the intelligent load identification circuit and the photovoltaic power generation module 201 according to the above embodiment.
Photovoltaic power generation module 201 includes solar panel and battery, and solar panel links to each other with the battery, and the battery links to each other with the power input end of the supply circuit 102 among the intelligent load identification circuit.
The solar panel receives sunlight irradiation to generate electricity and charges the storage battery, the storage battery provides electric energy for the intelligent load identification circuit, the intelligent load identification circuit can work, and the external load is charged through the intelligent load identification circuit.
The embodiment of the application also discloses an intelligent load identification method applying the intelligent load identification circuit. Referring to fig. 5, the intelligent load identification method mainly includes the following steps:
in step S301, the control circuit 101 controls the switch circuit 105 to be turned off.
Specifically, the control circuit 101 controls the MOS transistor T11 in the switch circuit 105 to be turned off, and the voltage reduction circuit 1021 is not connected to the load interface 103.
In step S302, the control circuit 101 detects whether the load interface 103 receives the voltage and/or current output by the external load through the sampling circuit 104. If yes, returning to the step S301; if not, the process proceeds to step S303.
Specifically, the control circuit 101 detects whether the load interface 103 receives the voltage and/or the current output by the external load through the sampling circuit 104, and when the load interface 103 has the voltage and the current, the control circuit 101 can detect the voltage and the current, and returns to step S301; when the load interface 103 does not have the voltage or the current, the control circuit 101 cannot detect the voltage or the current, and the process proceeds to step S303.
In step S303, the control circuit 101 controls the switch circuit 105 to be turned on, and the control circuit 101 starts timing and records the current timing value.
Specifically, the control circuit 101 controls the MOS transistor T11 in the switch circuit 105 to be turned on, so that the voltage dropping circuit 1021 can supply power to the outside through the load interface 103, and at the same time, the control circuit 101 starts to count from zero and records the current timing value.
Step S304, judging whether the current timing value is equal to the preset value, if so, returning to the step S301.
Specifically, the preset value may be set to 5 minutes, when the current timing value is equal to 5 minutes, the step S301 is returned to, and if not, the timing is continued.
The foregoing is a preferred embodiment of the present application and is not intended to limit the scope of the application in any way, and any features disclosed in this specification (including the abstract and drawings) may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.

Claims (10)

1. An intelligent load identification circuit, comprising a control circuit (101), a power supply circuit (102) and a load interface (103), wherein the power supply circuit (102) comprises a power input end for receiving electric energy and a first power output end, the first power output end is connected to the control circuit (101), characterized in that a sampling circuit (104) is connected between the control circuit (101) and the load interface (103), and the sampling circuit (104) is used for detecting voltage and/or current output by an external load received by the load interface (103);
the power supply circuit (102) further comprises a second power output end, a switch circuit (105) is connected between the second power output end and the load interface (103), the switch circuit (105) is connected with the control circuit, and the switch circuit (105) is used for controlling the circuit between the power supply circuit (102) and the load interface (103) to be switched on or off.
2. An intelligent load recognition circuit as claimed in claim 1, wherein the switch circuit (105) comprises a MOS transistor T11, the gate of the MOS transistor T11 is connected to the signal output terminal of the control circuit (101), the drain of the MOS transistor T11 is connected to the load interface (103), and the source of the MOS transistor T11 is connected to the second power supply output terminal of the power supply circuit (102).
3. A smart load recognition circuit according to claim 1 or 2, wherein the sampling circuit (104) comprises:
the voltage sampling circuit (1041) is used for detecting whether the load interface (103) receives the voltage output by an external load;
the current sampling circuit (1042) is used for detecting whether the load interface (103) receives the current output by the external load.
4. The intelligent load identification circuit according to claim 1 or 2, wherein the power supply circuit (102) further comprises a voltage reduction circuit (1021), a voltage input terminal of the voltage reduction circuit (1021) is connected to a power input terminal of the power supply circuit (102), and a voltage output terminal of the voltage reduction circuit (1021) is connected to a second power output terminal of the power supply circuit (102).
5. A smart load identification circuit as claimed in claim 4 wherein the buck circuit (1021) comprises a buck chip U3 and a feedback circuit (10211), the voltage input of the buck chip U3 is connected to the power input of the power supply circuit (102), the voltage output of the buck chip U3 is connected to the second power output of the power supply circuit (102);
the voltage reduction chip U3 includes a current feedback terminal, a voltage feedback terminal and a voltage output terminal, and the feedback circuit (10211) is connected to the current feedback terminal, the voltage feedback terminal and the voltage output terminal respectively.
6. An intelligent load identification circuit as claimed in claim 4, wherein a first diode D1 is connected in series between the power input terminal of the power supply circuit (102) and the voltage input terminal of the voltage reduction circuit (1021), the anode terminal of the first diode D1 is connected to the power input terminal of the power supply circuit (102), and the cathode terminal of the first diode D1 is connected to the voltage input terminal of the voltage reduction circuit (1021).
7. A smart load recognition circuit as claimed in claim 6, characterized in that a filter circuit (1022) is connected between the cathode terminal of the first diode D1 and an analog ground GND.
8. An intelligent load identification circuit according to any one of claims 1, 2 and 5 to 7, wherein the power supply circuit (102) further comprises a stabilizing circuit (1023), a voltage input terminal of the stabilizing circuit (1023) is connected to a power input terminal of the power supply circuit (102), and a voltage output terminal of the stabilizing circuit (1023) is connected to a first power output terminal of the power supply circuit (102).
9. A photovoltaic power generation system, characterized by comprising a smart load identification circuit according to any one of claims 1 to 8 and a photovoltaic power generation module (201), a power input of the power supply circuit (102) being connected to the photovoltaic power generation module (201).
10. A smart load recognition method using the smart load recognition circuit according to any one of claims 1 to 8, comprising:
the control circuit (101) controls the switch circuit (105) to be switched off;
after the switch circuit (105) is turned off, the control circuit (101) detects whether the load interface (103) receives the voltage and/or current output by the external load through a sampling circuit (104);
if not, the control circuit (101) controls the switch circuit (105) to be conducted, and meanwhile, the control circuit (101) starts timing and records a current timing value;
and judging whether the current timing value is equal to a preset value or not, if so, returning to the step that the control circuit (101) controls the switch circuit (105) to be switched off.
CN202110464790.9A 2021-04-28 2021-04-28 Intelligent load identification circuit and method and photovoltaic power generation system Pending CN113241813A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110464790.9A CN113241813A (en) 2021-04-28 2021-04-28 Intelligent load identification circuit and method and photovoltaic power generation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110464790.9A CN113241813A (en) 2021-04-28 2021-04-28 Intelligent load identification circuit and method and photovoltaic power generation system

Publications (1)

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CN113241813A true CN113241813A (en) 2021-08-10

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114337311A (en) * 2021-12-31 2022-04-12 深圳市华思旭科技有限公司 Power supply circuit, output method of starting power supply and starting power supply

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114337311A (en) * 2021-12-31 2022-04-12 深圳市华思旭科技有限公司 Power supply circuit, output method of starting power supply and starting power supply

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