CN113241110A - Multi-channel NAND FLASH error control method - Google Patents
Multi-channel NAND FLASH error control method Download PDFInfo
- Publication number
- CN113241110A CN113241110A CN202110509484.2A CN202110509484A CN113241110A CN 113241110 A CN113241110 A CN 113241110A CN 202110509484 A CN202110509484 A CN 202110509484A CN 113241110 A CN113241110 A CN 113241110A
- Authority
- CN
- China
- Prior art keywords
- data
- channel
- groups
- bch
- channel data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000012937 correction Methods 0.000 claims abstract description 14
- 238000000638 solvent extraction Methods 0.000 claims abstract description 4
- 238000013500 data storage Methods 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 abstract description 16
- 238000011084 recovery Methods 0.000 abstract description 5
- 238000013461 design Methods 0.000 abstract description 2
- 230000005764 inhibitory process Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007306 turnover Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013524 data verification Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides a multichannel NAND FLASH error control method based on BCH and RAID-like technology, which comprises the following steps: grouping input data according to the number of channels N and then interleaving the input data; carrying out XOR on the data of the N channels according to the channels to generate check data; forming N +1 groups of channel data by the check data and the N groups of channel data, and respectively carrying out parallel scrambling; performing BCH parallel coding on the N +1 groups of data respectively, partitioning the data according to the page length of FLASH, and storing the data in a storage array after coding, wherein the storage array consists of N +1 FLASH storage chips and corresponds to the N +1 groups of data one by one; reading N +1 groups of numbers in the storage array, respectively carrying out parallel BCH decoding, and giving a decoding success or failure state; respectively descrambling the N +1 group of data in parallel; carrying out fault-tolerant control on the N +1 group of data according to the decoding success state; and performing de-interleaving recovery on the data subjected to error control. The invention adopts design measures from three dimensions of inhibition, error correction and replacement to reduce the error rate of NAND FLASH.
Description
Technical Field
The invention relates to an error control method, in particular to a multichannel NAND FLASH error control method and a multichannel NAND FLASH error control system based on BCH and RAID-like technology.
Background
NAND Flash has the advantages of non-volatility, high reliability, small volume, light weight, low power consumption, strong shock resistance, wide working temperature range, etc., and has been widely used in various fields, especially aerospace. However, NAND FLASH, as the usage and data storage time become longer, the data stored therein is prone to bit flipping and random errors. In addition, as the erasing times of the FLASH block are increased, the oxidation layer is gradually aged, electrons are easier to enter and exit the storage unit, and therefore the charges stored in the storage unit are easy to be abnormal, and the block is invalid.
Currently, the commonly used method adopts error coding control, such as hamming check, BCH, LDPC, etc. The method can meet the requirement that in an application occasion with a low error rate, as the error rate is improved, data error correction cannot be finished after the error correction capability of the algorithm is exceeded; secondly, the stronger the error correction capability of the algorithm, the higher the complexity thereof, and the situation that the high-speed data error correction cannot be satisfied.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a multichannel NAND FLASH error control method based on BCH and RAID-like technology, which adopts design measures from three dimensions of inhibition, error correction and replacement to reduce the bit error rate of NAND FLASH.
The invention provides a multi-channel NAND FLASH error control method, which comprises the following steps:
s1: grouping input data according to the channel number N to generate N groups of channel data, and interweaving the channel data according to the channel number N; n is more than or equal to 2;
s2: carrying out bitwise XOR on the N groups of channel data according to the number of channels to generate check data;
s3: forming N +1 groups of channel data by the check data and the N groups of channel data, and respectively carrying out parallel scrambling;
s4: performing BCH parallel coding on the check data and the N groups of channel data respectively, partitioning according to the page length of a FLASH memory chip, and storing the data in a memory array, wherein the memory array comprises N +1 FLASH memory chips, and the N +1 FLASH memory chips correspond to the N +1 groups of channel data one by one;
s5: reading N +1 groups of channel data in the storage array, respectively performing parallel BCH decoding on the N +1 groups of channel data, and giving a state whether the decoding is successful;
s6: respectively carrying out parallel descrambling on the N +1 groups of channel data;
s7: carrying out fault-tolerant control on the N +1 groups of channel data according to the state of whether the decoding is successful or not;
s8: and de-interleaving and recovering the channel data subjected to the error control.
Preferably, the bit width of each channel data is consistent with the bit width of a FLASH memory chip in the memory array; and the bit width of the check data is consistent with the bit width of the FLASH memory chip.
Preferably, the storage array comprises N +1 sets of channels, wherein N sets of channels are used for data storage and 1 set of channels are used for check information storage.
Preferably, in step S2, parity check is performed on a bit-by-bit basis in units of lanes, generating check data.
Preferably, in step S4, the BCH parallel coding is performed on the N +1 sets of channel data, where the parallel width is consistent with the channel bit width, and the coding block length L is a common divisor of the page length of the FLASH memory chip.
Preferably, in step S7, fault-tolerant control is performed according to the "success status" of the BCH decoding of the N +1 sets of channel data sets, specifically, if the BCH decoding of the N sets of channel data is successful, decoded data is output; if only one BCH decoding of the N groups of channel data fails and the BCH decoding of the check data succeeds, performing XOR on all channel data successfully decoded to generate new data, then automatically replacing the channel data failed in decoding, and marking a FLASH block of the group as a bad block; if more than two BCH decoding failures occur in the N groups of channel data, system error information is given.
Preferably, a multichannel parallel processing technology is adopted when BCH encoding, BCH decoding, scrambling, descrambling, storing or reading data, each channel data corresponds to a storage chip one by one, and the bit width of the channel data is consistent with the bit width of the storage chip.
Preferably, the error correction capability t of the BCH parallel coding must be greater than or equal to the channel bit width.
Preferably, the BCH parallel coding information bit length k is consistent with the block length of scrambling and descrambling coding.
Preferably, in step S3, N +1 groups of channel data are scrambled respectively to complete data randomization; in step S6, the N +1 sets of channel data are descrambled, respectively, to restore the data.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention applies a data randomization mode to fully isolate the 0 and 1 distributions stored in the FLASH chip, thereby reducing the influence generated by the coupling voltage between adjacent units and reducing the turnover probability.
2. The invention adopts BCH error correction coding and decoding, thereby reducing the error rate of a multi-channel NAND FLASH storage system; and by combining with RAID 3-like fault-tolerant technology, recovery of fault channel data is autonomously realized, and the reliability of data storage is improved.
3. The invention improves the speed of data randomization and error correction by data grouping and adopting an FPGA multi-channel parallel data processing technology.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a general flow chart of a multi-channel NAND FLASH error control method based on BCH and RAID-like technology according to an embodiment of the present invention;
FIG. 2 is a schematic block diagram of an FPGA module of a multichannel NAND FLASH error control method based on BCH and RAID-like technologies according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the storage of BCH (4200, 4096, 8) encoded data and check information based on the multi-channel NAND FLASH error control method of BCH and RAID-like technology in the embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications can be made by persons skilled in the art without departing from the spirit of the invention. All falling within the scope of the present invention.
In the embodiment of the present invention, as shown in fig. 1, the multichannel NAND FLASH error control method based on BCH and RAID-like technology provided by the present invention includes the following steps:
s1: grouping input 8-bit parallel data according to a channel number N (N is 8), wherein an interleaving depth I is 8, the bit width of each group of channel data is 8 bits, a FLASH memory chip selected in a memory array is 3DFN128G08VS8308 of 3Dplus company, the bit width is 8 bits, the page length is 4320 bytes, and the blank area comprises 224 bytes;
s2: carrying out bitwise XOR on the N (N is 8) groups of data according to channels to generate 8-bit check data, wherein the bit width of the check data is consistent with that of the FLASH chip;
s3: respectively carrying out parallel scrambling on 9 groups of data of the contained check data;
s4: respectively carrying out BCH parallel coding on 9 groups of data, partitioning the data according to the page length of FLASH without containing a blank area of 4096 bytes, wherein the code length of each block is 512 bytes, namely 4096 bits, and respectively storing the data in a storage array in a one-to-one correspondence manner after coding, wherein the storage array consists of 9 (N +1) FLASH storage chips;
s5: reading 9 (N +1) groups of data (including check data) in the storage array, respectively performing parallel BCH decoding, and giving a decoding success or failure state;
s6: respectively descrambling 9 (N +1) groups of data (including check data) in parallel;
s7: according to the decoding success state, adopting RAID technology fault-tolerant control on 9 groups (N +1) of data (including check data);
s8: and performing de-interleaving recovery on the data subjected to error control.
Further, fig. 2 is a schematic block diagram of an FPGA module of the multichannel NAND FLASH error control method based on BCH and RAID-like technology in the embodiment of the present invention, and as shown in fig. 2, the present invention further includes an FPGA and a storage array.
Furthermore, the storage array is a multi-channel and comprises 9 channels, wherein 8 channels are used for data storage, and 1 channel is specially used for verification information storage.
Further, the data storage and verification of the storage Array are controlled in a fault-tolerant technical mode of a RAID3(Redundant Array of Independent Disks), each FLASH storage chip is used as a disk, and each channel corresponds to one FLASH storage chip.
Further, in step S1, the input data is interleaved, after interleaving, the bit width of each group of channel data is consistent with the bit width of the FLASH memory chip in the memory array, and the bit width B is 8, and then the data is stored in the cache, thereby completing the data conversion.
Further, in step S2, parity is performed on a bit-by-bit basis in units of lanes, and 8-bit check data is generated.
Further, in step S3, the 9 sets of data (including check data) are scrambled in parallel, respectively, and data randomization is completed. The code length is 512 bytes, and the generator polynomial is F (X) or X8+X7+X5+X3+1。
Further, fig. 3 is a schematic diagram illustrating storage of BCH (4200, 4096, 8) encoded data and check information of the multichannel NAND FLASH error control method based on BCH and RAID-like technology provided by the present invention, as shown in fig. 3, in step S4, 9 groups of data (including check data) are respectively subjected to BCH parallel encoding, and the encoding width is 8 bits; the encoding block length is 512 bytes, namely the information length k is 4096; BCH error correction capability t is 8, check bit length is 13 × 8 is 104 bits, and total length n is 4200(525 bytes). The FLASH memory chip has a blank area with the length of 4096 bytes and 224 bytes, and the information codes and the check codes of 8 blocks of BCH (4200, 4096 and 8) are stored in sequence and alternately.
Further, 9 groups of data in the memory array are read and stored in the buffer, and in step S5, the 9 groups of data (including the check data) are respectively subjected to BCH (4200, 4096, 8) parallel decoding at a rate 3 times, and a status of "success or failure" of each decoding group is given.
Further, in step S6, the 9 sets of data (including the check data) are descrambled in parallel, and the data recovery is completed. The code length is 512 bytes, and the generator polynomial is F (X) or X8+X7+X5+X3+1。
Further, in step S7, RAID 3-like fault-tolerant control is performed according to the "success or failure" status of the 9 sets of BCH decoding. If the 8 groups of data BCH decoding are successful, outputting decoding data unchanged; if only one group of BCH decoding fails in the 8 groups of data and the BCH decoding of the check data succeeds, performing XOR on all channel data successfully decoded to generate new data, then replacing the data group failed in decoding, and marking a FLASH block of the channel as a bad block; if more than two BCH decoding failures occur in the 9 groups of data, system error information is given.
Further, in step S8, the data is deinterleaved to restore the output.
Furthermore, the BCH coding, the BCH decoding, the scrambling, the descrambling, the storing or the reading all adopt a multi-channel processing technology, 9 groups of data are processed in parallel, each group of channel data corresponds to a storage chip one by one, and the bit width of the channel data and the bit width of the chip are both 8 bits.
Further, the BCH (4200, 4096, 8) error correction capability t is equal to the channel bit width. The BCH coding block information bit length k is consistent with the block length of scrambling and descrambling coding and is 512 bytes.
In the embodiment of the invention, the 0 and 1 distributions stored in the FLASH chip are fully isolated by using a data randomization mode, so that the influence generated by coupling voltage between adjacent units is reduced, and the turnover probability is reduced; secondly, by adopting BCH error correction coding and decoding, the error rate of a multi-channel NAND FLASH storage system is reduced; and by combining with RAID 3-like fault-tolerant technology, recovery of fault channel data is autonomously realized, and the reliability of data storage is improved. And finally, by data grouping and utilizing an FPGA multi-channel parallel data processing technology, the data randomization and error correction speed is improved.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention.
Claims (10)
1. A multi-channel NAND FLASH error control method, comprising:
s1: grouping input data according to the channel number N to generate N groups of channel data, and interweaving the channel data according to the channel number N;
s2: carrying out bitwise XOR on the N groups of channel data according to the number of channels to generate check data;
s3: forming N +1 groups of channel data by the check data and the N groups of channel data, and respectively carrying out parallel scrambling;
s4: performing BCH parallel coding on the check data and the N groups of channel data respectively, partitioning according to the page length of a FLASH memory chip, and storing the data in a memory array, wherein the memory array comprises N +1 FLASH memory chips, and the N +1 FLASH memory chips correspond to the N +1 groups of channel data one by one;
s5: reading N +1 groups of channel data in the storage array, respectively performing parallel BCH decoding on the N +1 groups of channel data, and giving a state whether the decoding is successful;
s6: respectively carrying out parallel descrambling on the N +1 groups of channel data;
s7: carrying out fault-tolerant control on the N +1 groups of channel data according to the state of whether the decoding is successful or not;
s8: and de-interleaving and recovering the channel data subjected to the error control.
2. The multi-channel NAND FLASH error control method according to claim 1, wherein the bit width of each channel data is consistent with the bit width of a FLASH memory chip in the memory array; and the bit width of the check data is consistent with the bit width of the FLASH memory chip.
3. The multi-lane NAND FLASH error control method of claim 1, wherein the storage array comprises N +1 sets of lanes, wherein N sets of lanes are used for data storage and 1 set of lanes are used for check information storage.
4. The multi-lane NAND FLASH error control method according to claim 1, wherein in step S2, parity checking is performed on a per-lane basis to generate check data.
5. The multi-channel NAND FLASH error control method according to claim 1, wherein in step S4, N +1 sets of channel data are respectively BCH-encoded in parallel, wherein the parallel width is consistent with the channel bit width, and the encoding block length L is a common divisor of the page length of the FLASH memory chip.
6. The multi-channel NAND FLASH error control method according to claim 1, wherein in step S7, performing fault-tolerant control according to "success status" of BCH decoding of N +1 sets of channel data, specifically, outputting decoded data if BCH decoding of N sets of channel data succeeds; if only one BCH decoding of the N groups of channel data fails and the BCH decoding of the check data succeeds, performing XOR on all channel data successfully decoded to generate new data, then automatically replacing the channel data failed in decoding, and marking a FLASH block of the group as a bad block; if more than two BCH decoding failures occur in the N groups of channel data, system error information is given.
7. The multi-channel NAND FLASH error control method according to claim 1, wherein a multi-channel parallel processing technique is adopted in BCH encoding, BCH decoding, scrambling, descrambling, storing or reading data, and each channel data corresponds to a memory chip one by one, and the bit width of the channel data is consistent with the bit width of the memory chip.
8. The multi-channel NAND FLASH error control method according to claim 2, wherein the error correction capability t of the BCH parallel coding must be greater than or equal to the channel bit width.
9. The multi-channel NAND FLASH error control method of claim 1, wherein the BCH parallel coding has an information bit length k consistent with the block length of the scrambling and descrambling codes.
10. The multi-channel NAND FLASH error control method according to claim 1, wherein in step S3, N +1 groups of channel data are scrambled respectively to complete data randomization; in step S6, the N +1 sets of channel data are descrambled, respectively, to restore the data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110509484.2A CN113241110A (en) | 2021-05-10 | 2021-05-10 | Multi-channel NAND FLASH error control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110509484.2A CN113241110A (en) | 2021-05-10 | 2021-05-10 | Multi-channel NAND FLASH error control method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113241110A true CN113241110A (en) | 2021-08-10 |
Family
ID=77133252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110509484.2A Pending CN113241110A (en) | 2021-05-10 | 2021-05-10 | Multi-channel NAND FLASH error control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113241110A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105940626A (en) * | 2014-11-06 | 2016-09-14 | Lg电子株式会社 | Method and apparatus for receiving broadcast signal, and method and apparatus for transmitting broadcast signal |
| CN106502590A (en) * | 2016-10-24 | 2017-03-15 | 郑州云海信息技术有限公司 | A kind of solid-state hard disk SSD storage system and method |
| CN107342772A (en) * | 2010-11-22 | 2017-11-10 | 索尼公司 | Data processing equipment and data processing method |
| CN108958963A (en) * | 2018-06-01 | 2018-12-07 | 杭州电子科技大学 | A kind of NAND FLASH error control method based on LDPC and cyclic redundancy check code |
| CN109935263A (en) * | 2019-03-27 | 2019-06-25 | 翰顺联电子科技(南京)有限公司 | The coding and decoding method and storage system of nonvolatile memory |
| CN111597072A (en) * | 2020-05-07 | 2020-08-28 | 中国科学院微电子研究所 | Error Control Coding (ECC) system and memory device including the same |
-
2021
- 2021-05-10 CN CN202110509484.2A patent/CN113241110A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107342772A (en) * | 2010-11-22 | 2017-11-10 | 索尼公司 | Data processing equipment and data processing method |
| CN105940626A (en) * | 2014-11-06 | 2016-09-14 | Lg电子株式会社 | Method and apparatus for receiving broadcast signal, and method and apparatus for transmitting broadcast signal |
| CN106502590A (en) * | 2016-10-24 | 2017-03-15 | 郑州云海信息技术有限公司 | A kind of solid-state hard disk SSD storage system and method |
| CN108958963A (en) * | 2018-06-01 | 2018-12-07 | 杭州电子科技大学 | A kind of NAND FLASH error control method based on LDPC and cyclic redundancy check code |
| CN109935263A (en) * | 2019-03-27 | 2019-06-25 | 翰顺联电子科技(南京)有限公司 | The coding and decoding method and storage system of nonvolatile memory |
| CN111597072A (en) * | 2020-05-07 | 2020-08-28 | 中国科学院微电子研究所 | Error Control Coding (ECC) system and memory device including the same |
Non-Patent Citations (2)
| Title |
|---|
| 李璐;周海燕;: "一种含BCH编解码器的SLC/MLC NAND FLASH控制器的VLSI设计", 现代电子技术, no. 07, 1 April 2009 (2009-04-01) * |
| 焦新泉;武慧军;单彦虎;秦菲;: "基于Nand Flash的BCH校验方法设计与实现", 电测与仪表, no. 22, 25 November 2017 (2017-11-25) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101635158B (en) | Methods, apparatuses, systems, and architectures for quickly and reliably encoding and/or decoding system data | |
| US8386889B1 (en) | Drive replacement techniques for RAID systems | |
| US10447301B2 (en) | Optimal LDPC bit flip decision | |
| CN101211667A (en) | Error correction circuit and method for reducing miscorrection probability and memory device including the circuit | |
| CN104115126A (en) | Multi-phase ecc encoding using algebraic codes | |
| CN102915768A (en) | Device and method for tolerating faults of storage based on triple modular redundancy of EDAC module | |
| US20120159285A1 (en) | Storage drive with ldpc coding | |
| CN113748414B (en) | Error correction code structure | |
| CN1647392A (en) | Method and apparatus for embedding an additional layer of error correction into an error correcting code | |
| KR101550762B1 (en) | Concatenated error correction device | |
| CN111124741B (en) | Enhanced type checking and error correcting device facing memory characteristics | |
| WO2000073906A9 (en) | Mechanism for decoding linearly-shifted codes to facilitate correection of bit errors due to component failures | |
| CN107402860B (en) | Redundant array of independent disks decoding system for performing built-in self-test | |
| KR101320684B1 (en) | Encoding, decoding, and multi-stage decoding circuits and methods for concatenated bch code, error correct circuit of flash memory device using the same, and flash memory device using the same | |
| US8627183B1 (en) | Systems and methods for storing variable rate product codes | |
| US20160147598A1 (en) | Operating a memory unit | |
| CN113168882B (en) | Encoding method, decoding method and storage controller | |
| CN113241110A (en) | Multi-channel NAND FLASH error control method | |
| KR101355988B1 (en) | Encoding, decoding, and multi-stage decoding circuits and methods for concatenated bch code, error correct circuit of flash memory device using the same, and flash memory device using the same | |
| CN108170554B (en) | NAND data coding method and device | |
| CN202838976U (en) | EDAC (Error Detection And Correction)-module-based fault-tolerant device of triple modular redundancy to storage | |
| JP2021033530A (en) | Memory system | |
| JP2020064350A (en) | Management method of flash memory | |
| KR101355986B1 (en) | Encoding, decoding, and multi-stage decoding circuits and methods for concatenated bch code, error correct circuit of flash memory device using the same, and flash memory device using the same | |
| US11689219B1 (en) | Method and system for error correction in memory devices using irregular error correction code components |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |