CN113238678A - Control device, time sequence control circuit, control method, chip and electronic equipment - Google Patents
Control device, time sequence control circuit, control method, chip and electronic equipment Download PDFInfo
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- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
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Abstract
The disclosure relates to a control device, a time sequence control circuit, a control method, a chip and an electronic device, wherein the device comprises a control module, a storage module and a check module, the storage module is connected with the control module and the check module, and the check module is used for: when the control device is determined to be reset, executing N times of checking operations, wherein the checking operations comprise: after waiting for the time of preset duration, verifying the running program in the storage module to obtain a verification result; the control module is used for: and executing the running program in the storage module under the condition that the verification result of one of the N times of verification operations is correct. The embodiment of the disclosure can avoid legal soft failure due to verification failure caused by communication abnormity or instability of the storage module, improve the success rate of starting, and can perform reset restart of the control device without depending on a flash memory, and the cost is low.
Description
Technical Field
The present disclosure relates to the field of control technologies, and in particular, to a control device, a timing control circuit, a control method, a chip, and an electronic apparatus.
Background
At present, more and more electronic devices are provided with display panels having a touch function. When the touch chip of the display panel is reset without power down, if the firmware in the memory is abnormal due to some reasons (e.g., electrostatic Discharge (ESD), etc.), the touch chip will have Soft Fail (Soft Fail) and cannot operate normally, the related art usually obtains the firmware from the flash memory and loads the firmware into the memory to restart the touch chip, however, when the abnormal situation causes unstable or abnormal communication between the memory and the controller, the touch chip cannot be started normally, and for some circuits or devices that do not include the flash memory, the related art cannot restart the touch chip.
Disclosure of Invention
In view of the above, the present disclosure provides a control device, which includes a control module, a storage module, and a check module, wherein the storage module is connected to the control module and the check module,
the check module is used for: when the control device is determined to be reset, executing N times of checking operations, wherein the checking operations comprise: after waiting for a preset time, verifying the running program in the storage module to obtain a verification result, wherein N is not less than 1 and is an integer;
the control module is used for: and executing the running program in the storage module under the condition that the verification result of one of the N times of verification operations is correct.
In a possible implementation manner, the preset duration corresponding to the execution times of the verification operation being 1 is longer than the preset duration corresponding to the execution times being greater than 1.
In one possible embodiment, the verification module includes:
and the adjusting unit is used for setting the preset time length as a first time length under the condition that the checking module executes the checking operation for the first time.
In a possible embodiment, the adjusting unit is further configured to:
setting the execution times of the checking operation to be M times and setting the preset time length to be a second time length when the checking result of the checking operation executed for the first time is incorrect checking,
wherein M > 1 and is an integer, and the second duration is less than the first duration.
In a possible embodiment, the adjusting unit is further configured to:
setting the execution times of the checking operation as K times and setting the preset time length as a third time length when the checking results of the M times of checking operation are incorrect,
wherein K is greater than M and is an integer, and the third duration is less than the second duration.
In one possible embodiment, the verification module includes:
the checking unit is used for checking the running program;
and the time delay unit is connected with the verification unit and used for delaying the preset time length of the starting time of the verification unit.
In a possible implementation, the verification module further includes:
and the cycle control unit is connected with the delay unit and the verification unit and is used for controlling the delay unit and the verification unit to execute S times of verification operation, wherein S is more than 1 and less than or equal to N.
In a possible implementation, the verification module is further configured to:
and when the verification results of the N times of verification operations are all verified incorrectly, interrupting the starting of the control module.
In a possible embodiment, the apparatus is connected to an external device, and the verification module is further configured to:
and when the verification results of the N times of verification operations are all verified incorrectly, outputting a control signal to enable the external equipment to send the application program file to the storage module.
In one possible embodiment, the storage module includes a static random access memory.
According to another aspect of the present disclosure, a timing control circuit is provided, which is applied in a control device, the control device includes a control module, a storage module, and a check module, the storage module is connected to the control module and the check module, the circuit includes:
and the time delay module is connected with the verification module and used for delaying the starting time of the verification module for a first time length so that the verification module verifies the running program in the storage module after delaying the first time length to obtain a verification result, and the verification module controls the starting of the control module according to the verification result.
In one possible implementation, the circuit further includes:
a cycle control module connected to the delay module and the check module for controlling the check module and the delay module to execute M times of check operations,
wherein the verifying operation comprises: the starting time of the checking module is delayed for a second time, then the running program in the storage module is checked to obtain a checking result, wherein M is more than 1 and is an integer,
wherein the second duration is less than the first duration.
In one possible implementation, the circuit further includes:
an adjusting module connected to the cycle control module for setting the execution times of the check operation to K times and the delay time to a third time when the check results of the M check operations are all incorrect,
wherein K is greater than M and is an integer, and the third duration is less than the second duration.
According to another aspect of the present disclosure, a control method is provided, which is applied to a control device including a control module and a storage module, and includes:
when the control device is determined to be reset, executing N times of checking operations, wherein the checking operations comprise: after waiting for a preset time, verifying the running program in the storage module to obtain a verification result, wherein N is not less than 1 and is an integer;
and executing the running program in the storage module under the condition that the verification result of one of the N times of verification operations is correct.
In a possible implementation manner, the preset duration corresponding to the execution times of the verification operation being 1 is longer than the preset duration corresponding to the execution times being greater than 1.
In one possible embodiment, the method further comprises:
and under the condition of executing the checking operation for the first time, setting the preset time length as a first time length.
In one possible embodiment, the method further comprises:
setting the execution times of the checking operation to be M times and setting the preset time length to be a second time length when the checking result of the checking operation executed for the first time is incorrect checking,
wherein M > 1 and is an integer, and the second duration is less than the first duration.
In one possible embodiment, the method further comprises:
setting the execution times of the checking operation as K times and setting the preset time length as a third time length when the checking results of the M times of checking operation are incorrect,
wherein K is greater than M and is an integer, and the third duration is less than the second duration.
According to another aspect of the present disclosure, a chip is presented, the chip comprising:
the control device; or
The sequential control circuit.
According to another aspect of the present disclosure, an electronic device is provided, which includes the chip.
In one possible implementation, the electronic device comprises a display, a smartphone, or a portable device.
The embodiment of the present disclosure may execute N times of verification operations when it is determined that the control device is reset, where the verification operations include: the method comprises the steps of waiting for a preset time, checking the running program in the storage module to obtain a checking result, and executing the running program in the storage module to enable the control device to start to normally work under the condition that the checking result of one of N times of checking operations is correct, so that legal soft failure caused by checking failure due to communication abnormity or instability of the storage module can be avoided, the starting success rate is improved, in addition, the control device of the embodiment of the disclosure can carry out reset and restart of the control device without depending on a flash memory, and the cost is low.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a block diagram of a control device according to an embodiment of the present disclosure.
Fig. 2 shows a block diagram of a control device according to an embodiment of the present disclosure.
FIG. 3 shows a block diagram of a timing control circuit according to an embodiment of the present disclosure.
FIG. 4 shows a block diagram of a timing control circuit according to an embodiment of the present disclosure.
FIG. 5 shows a flow chart of a control method according to an embodiment of the present disclosure.
FIG. 6 shows a flow chart of a control method according to an embodiment of the present disclosure.
FIG. 7 shows a block diagram of a control device according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
In the description of the present disclosure, it is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings, which is solely for the purpose of facilitating the description and simplifying the description, and does not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and, therefore, should not be taken as limiting the present disclosure.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.
In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Referring to fig. 1, fig. 1 shows a block diagram of a control device according to an embodiment of the present disclosure.
As shown in fig. 1, the apparatus includes a control module 10, a storage module 20, and a verification module 30, wherein the storage module 20 is connected to the control module 10 and the verification module 30, wherein,
the verification module 30 is configured to: when the control device is determined to be reset, executing N times of checking operations, wherein the checking operations comprise: after waiting for a preset time, verifying the running program in the storage module 20 to obtain a verification result, wherein N is not less than 1 and is an integer;
the control module 10 is configured to: and executing the running program in the storage module 20 under the condition that the verification result of one of the N times of verification operations is correct.
The embodiment of the present disclosure may execute N times of verification operations when it is determined that the control device is reset, where the verification operations include: the method comprises the steps of waiting for a preset time, checking the running program in the storage module to obtain a checking result, and executing the running program in the storage module to enable the control device to start to normally work under the condition that the checking result of one of N times of checking operations is correct, so that legal soft failure caused by checking failure due to communication abnormity or instability of the storage module can be avoided, the starting success rate is improved, in addition, the control device of the embodiment of the disclosure can carry out reset and restart of the control device without depending on a flash memory, and the cost is low.
In one example, the control device of the embodiment of the present disclosure may be a touch chip, or a display panel and a terminal provided with the touch chip and having a touch function.
In one example, the display panel may include a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel, a micro light emitting diode display panel, and the like.
In one example, a Terminal, also referred to as a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), etc., is a device that provides voice and/or data connectivity to a User, such as a handheld device with wireless connection capability, a vehicle-mounted device, etc. Currently, some examples of terminals are: a Mobile Phone (Mobile Phone), a tablet computer, a notebook computer, a palm computer, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in Industrial Control (Industrial Control), a wireless terminal in unmanned driving (self driving), a wireless terminal in Remote Surgery (Remote medical Surgery), a wireless terminal in Smart Grid, a wireless terminal in Transportation Safety, a wireless terminal in Smart City (Smart City), a wireless terminal in Smart Home (Smart Home), a wireless terminal in car networking, and the like.
The control module 10 of the disclosed embodiment may include processing components including, but not limited to, a single processor, or discrete components, or a combination of a processor and discrete components. The processor may comprise a controller having functionality to execute instructions in an electronic device, which may be implemented in any suitable manner, e.g., by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components. Within the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, Application Specific Integrated Circuits (ASICs), programmable logic controllers, and embedded microcontrollers.
In one example, when a human body (e.g., a finger) touches a touch area of a display panel or an electronic device, an electrostatic Discharge (ESD) charge may be transmitted to a control device through a line of the touch area, data inaccuracy may be caused by a sudden jump of a data state potential in a storage module (e.g., a Static random access memory) due to a pulse current generated by the ESD, so that an application program in the storage module is inaccurate, and when a duration of an ESD event is long, a verification module fails to verify data due to an abnormal or unstable communication of the storage module during a process of performing a verification of a file, so that the control device cannot successfully restart the control module to achieve self-recovery. And after waiting for a preset time, verifying the running program in the storage module to obtain a verification result, and executing the running program in the storage module when the verification result of one of the N times of verification operations is correct, so that the control device starts to work normally, and the legal soft failure caused by the verification failure due to communication abnormity or instability of the storage module can be avoided.
It should be noted that, the specific implementation manner of determining that the reset occurs is not limited in the embodiments of the present disclosure, and for example, the control device may be determined to have the reset by a system clock, a reset signal generated by a system, or any other manner.
It should be noted that, in the embodiment of the present disclosure, a specific type of the application program is not limited, and the application program may be a driver program for driving each device of the control device, may also include other functional programs, and may also be other programs and instructions that can be executed by the control module to enable the control device to normally operate.
The embodiment of the present disclosure does not limit the checking mode of the checking module for checking the application program, and for example, the application program may be checked through data comparison checking, Parity checking (Parity Check), BCC exclusive-or (block Check code), LRC Longitudinal Redundancy Check (long redundant Check), CRC (Cyclic Redundancy Check) Cyclic Redundancy Check, MD5, SHA, MAC, and other digest algorithms.
The specific number of the execution times of the checking operation is not limited in the embodiment of the disclosure, and a person skilled in the art may set the number according to needs or actual conditions, and it should be understood that, for different execution times, the preset time length for the checking module to wait in each cycle operation is different. .
In a possible implementation manner, the preset duration corresponding to the execution times of the verification operation being 1 is longer than the preset duration corresponding to the execution times being greater than 1.
Referring to fig. 2, fig. 2 is a block diagram of a control device according to an embodiment of the disclosure.
In one possible implementation, as shown in fig. 2, the verification module 30 may include:
an adjusting unit 310, configured to set the preset time length as a first time length when the checking module 30 performs the checking operation for the first time.
In a possible implementation, the adjusting unit 310 may further be configured to:
setting the execution times of the checking operation to be M times and setting the preset time length to be a second time length when the checking result of the checking operation executed for the first time is incorrect checking,
wherein M > 1 and is an integer, and the second duration is less than the first duration.
In a possible implementation, the adjusting unit 310 may further be configured to:
setting the execution times of the checking operation as K times and setting the preset time length as a third time length when the checking results of the M times of checking operation are incorrect,
wherein K is greater than M and is an integer, and the third duration is less than the second duration.
The execution times of the verification operation can be set according to actual conditions to adapt to the reset and restart conditions under different conditions, so that the adaptability of the duration time of communication abnormity or unstable conditions of the storage module caused by different reasons is improved, of course, the specific size of the preset time corresponding to the set corresponding times is not limited in the embodiment of the disclosure, the embodiment of the disclosure can be set according to needs, and when the number of times of the cycle execution is set to be a smaller value, the embodiment of the disclosure can set the preset time to be a larger time; when the number of loop executions is set to a larger value, the disclosed embodiments may set the popular river duration to a smaller duration. Moreover, the embodiment of the disclosure supports real-time adjustment of the execution times and the preset time length, for example, when the verification results of the verification operations executed for M times are all incorrect, the execution times of the verification operations are set to K times, the preset time length is set to a third time length, and the control module can be started as long as a certain time of verification in the execution of the verification operations is correct.
In one possible embodiment, as shown in fig. 2, the verification module 30 includes:
a checking unit 320, configured to check the running program;
the delay unit 330 is connected to the verifying unit 320, and configured to delay the start time of the verifying unit 320 by the preset time length.
The verification unit 320 may be configured to immediately perform the verification operation on the application program of the storage module upon learning that the control device is reset, and the embodiment of the present disclosure may implement the delay of the verification operation on the verification unit 320 through the delay unit 330, so as to avoid legal soft failure due to verification failure caused by communication abnormality or instability of the storage module.
In the embodiment of the present disclosure, the delay unit 330 delays the start time of the verification unit 320 for performing the reference program verification each time when the control device is reset and started, so that the communication abnormality or instability of the storage module can be avoided in the process of waiting for the first time to pass by the verification unit 320, and the storage module is verified only after the communication is stable, thereby avoiding a situation that the data verification fails due to the influence of a sudden ESD. Finally, after the inspection result shows that the inspection is passed, the control module 10 is started to enable the control device to start normal operation.
The embodiment of the present disclosure does not limit the specific implementation manners of the delay unit 330, the verification unit 320, and the adjustment unit 310.
In a possible implementation, as shown in fig. 2, the verification module 30 further includes:
and a cycle control unit 340, connected to the delay unit 330 and the verification unit 320, for controlling the delay unit 330 and the verification unit 320 to perform S times of verification operations, where S is greater than 1 and less than or equal to N.
The embodiment of the present disclosure may control the delay unit 330 and the verification unit 320 through the loop control unit 340, so that the start time of the verification operation of the application program by the verification unit 320 is delayed by a preset time length each time.
When the verification operation is executed circularly, the verification unit may be configured to start the next verification operation when one verification operation is completed, and in the embodiment of the present disclosure, the delay unit 330 may delay the start time of each verification operation of the verification unit 320 by a preset time length, and the circular control unit controls the circular execution of the verification operation, so as to avoid legal soft failure due to verification failure caused by abnormal or unstable communication of the storage module.
In a possible implementation, the verification module 30 may further be configured to:
and when the verification results of the N times of verification operations are all verified incorrectly, interrupting the starting of the control module 10.
In a possible embodiment, the apparatus is connected to an external device, and the verification module 30 is further configured to:
and when the verification results of the N verification operations are all verified incorrectly, outputting a control signal to enable the external device to send the application program file to the storage module 20.
When the cyclic execution coefficient of the set verification parameter reaches the preset number of times, if the verification result of the last verification is still incorrect, the embodiment of the present disclosure may interrupt the starting of the control module 10, or output a control signal, so that the external device sends the application program file to the storage module 20, for example, notify an external host processor through a certain signal communication pin or port of the control module, so that the host processor directly loads at least the executable file of the application program into the storage module, or stores the file into a flash memory of the control device in the case that the control device has a flash memory.
Referring to fig. 3, fig. 3 is a block diagram of a timing control circuit according to an embodiment of the disclosure.
The circuit is applied to a control device, as shown in fig. 3, the control device includes a control module 10, a storage module 20, and a check module 30, the storage module 20 is connected to the control module 10 and the check module 30, and the circuit includes:
the delay module 410 is connected to the verification module 30, and configured to delay the start time of the verification module 30 by a first time length, so that after the verification module 30 delays the first time length, the running program in the storage module 20 is verified to obtain a verification result, and the verification module 30 controls the start of the control module 10 according to the verification result.
The control device of the embodiment of the disclosure delays the starting time of the check module for a first time, so that the check module checks the running program in the storage module after delaying the first time to obtain a check result, and controls the starting of the control module according to the check result, so that the control device starts to work normally, thereby avoiding legal soft failure due to check failure caused by communication abnormity or instability of the storage module, improving the starting success rate, and being independent of a flash memory to reset and restart the control device, and having low cost.
The embodiment of the present disclosure uses the delay module 40 to delay the start time of the check module 30 for executing the reference program check each time when the control device is reset and started, so that the communication abnormality or instability of the storage module can be avoided in the process of the check module 30 waiting for the first time to pass, and the check of the storage module is started after the communication is stable, thereby avoiding the data check failure caused by the influence of the sudden ESD. Finally, after the inspection result shows that the inspection is passed, the control module 10 is started to enable the control device to start normal operation.
In one example, the control device of the embodiment of the present disclosure may be a touch chip, or a display panel and a terminal provided with the touch chip and having a touch function.
Referring to fig. 4, fig. 4 is a block diagram of a timing control circuit according to an embodiment of the disclosure.
In one possible implementation, as shown in fig. 4, the circuit further includes:
a cycle control module 420 connected to the delay module 410 and the check module 30, for controlling the check module 30 and the delay module 410 to execute M check operations,
wherein the verifying operation comprises: after the starting time of the checking module 30 is delayed by the second duration, the running program in the storage module 20 is checked to obtain a checking result, wherein M is greater than 1 and is an integer,
wherein the second duration is less than the first duration.
The embodiment of the present disclosure may control the delay module 410 and the checking module 30 through the loop control module 420, so that the starting time of the checking operation of the checking module 30 to the application program is delayed by a second time length each time.
When the verification operation is executed circularly, the verification module may be configured to start the next verification operation when one verification operation is completed, and the delay module 410 according to the embodiment of the present disclosure may delay the start time of each verification operation of the verification module 30 by a preset time length, and control the verification operation executed circularly, so as to avoid legal soft failure due to verification failure caused by communication abnormality or instability of the storage module.
It should be noted that, in a single verification operation, the longer the first time period is set, the easier it is to avoid the communication abnormality or instability of the storage module, however, setting the first time period too long may give a user a feeling of slow touch response, but setting the first time period too short may not avoid the communication expiration period. For this reason, the embodiment of the present disclosure is configured to cause the verification module 30 to repeatedly perform a plurality of verification operations on the memory module through the loop control module 420.
In one example, the cyclic check is to solve the problem that the setting time of the first duration is too long, the waiting time (i.e., the second duration) is shortened, and the number of cyclic checks is increased, so that if one check passes, the check can be considered to be successful, and the loop is skipped. Therefore, the waiting time can be reduced, and the response speed of the system can be improved.
In one possible implementation, as shown in fig. 4, the circuit further includes:
an adjusting module 430, connected to the loop control module 420, for setting the number of execution times of the check operation to K times and the delay time length to a third time length when all check results of the M check operations are incorrect,
wherein K is greater than M and is an integer, and the third duration is less than the second duration.
The execution times of the verification operation can be set according to actual conditions to adapt to the reset and restart conditions under different conditions, so that the adaptability of the duration time of communication abnormity or unstable conditions of the storage module caused by different reasons is improved, of course, the specific size of the preset time corresponding to the set corresponding times is not limited in the embodiment of the disclosure, the embodiment of the disclosure can be set according to needs, and when the number of times of the cycle execution is set to be a smaller value, the embodiment of the disclosure can set the preset time to be a larger time; when the number of loop executions is set to a larger value, the disclosed embodiments may set the popular river duration to a smaller duration. Moreover, the embodiment of the disclosure supports real-time adjustment of the execution times and the preset time length, for example, when the verification results of the verification operations executed for M times are all incorrect, the execution times of the verification operations are set to K times, the preset time length is set to a third time length, and the control module can be started as long as a certain time of verification in the execution of the verification operations is correct.
It should be understood that the timing control circuit corresponds to the aforementioned control device, and for a specific description, reference is made to the description of the control device before, which is not described herein again.
Referring to fig. 5, fig. 5 is a flowchart illustrating a control method according to an embodiment of the disclosure.
The method is applied to a control device, which may include a control module 10 and a storage module 20, as shown in fig. 5, and includes:
step S11, when it is determined that the control device is reset, performing N verification operations, where the verification operations include: after waiting for a preset time, verifying the running program in the storage module 20 to obtain a verification result, wherein N is not less than 1 and is an integer;
in step S12, when the result of one of the N verification operations is correct, the running program in the storage module 20 is executed.
The embodiment of the present disclosure may execute N times of verification operations when it is determined that the control device is reset, where the verification operations include: the method comprises the steps of waiting for a preset time, checking the running program in the storage module to obtain a checking result, and executing the running program in the storage module to enable the control device to start to normally work under the condition that the checking result of one of N times of checking operations is correct, so that legal soft failure caused by checking failure due to communication abnormity or instability of the storage module can be avoided, the starting success rate is improved, in addition, the control device of the embodiment of the disclosure can carry out reset and restart of the control device without depending on a flash memory, and the cost is low.
In a possible implementation manner, the preset duration corresponding to the execution times of the verification operation being 1 is longer than the preset duration corresponding to the execution times being greater than 1.
Referring to fig. 6, fig. 6 shows a flowchart of a control method according to an embodiment of the disclosure.
In one possible embodiment, as shown in fig. 6, the method further comprises:
step S13, in the case that the checking operation is performed for the first time, setting the preset duration as a first duration.
In one possible embodiment, as shown in fig. 6, the method further comprises:
step S14, in case that the first time the check result of the check operation is incorrect, setting the number of times of the check operation as M times, and setting the preset time length as a second time length,
wherein M > 1 and is an integer, and the second duration is less than the first duration.
In one possible embodiment, as shown in fig. 6, the method further comprises:
step S15, when the verification results of the M verification operations are all incorrect, setting the number of times of the verification operations to be performed to K times, and setting the preset time length to be a third time length,
wherein K is greater than M and is an integer, and the third duration is less than the second duration.
In the related art, for an application without a FLASH memory FLASH, hardware cannot automatically load firmware from FLASH to recover itself, and if an ESD event lasts for a long time and the SRAM communication is not recovered to normal when the content of the firmware (including an application program such as a driver) is verified, the verification fails, and the control module cannot be restarted, so that the self-recovery of the control device fails, and the soft failure occurs in the control device. The embodiment of the present disclosure can solve the problem of too long waiting time through cyclic verification, and can adopt a mode of reducing the waiting time and properly increasing the number of cycles, and can consider that the verification is successful and jump out of the cycle as long as one-time verification passes, so that the waiting time can be reduced, the response speed of the system can be improved, and legal soft failure due to verification failure caused by abnormal or unstable communication of the storage module can be avoided.
Referring to fig. 7, fig. 7 is a block diagram of a control device according to an embodiment of the disclosure.
For example, the apparatus 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.
Referring to fig. 7, the apparatus 800 may include one or more of the following components: processing component 802, memory 804, power component 806, multimedia component 808, audio component 810, input/output (I/O) interface 812, sensor component 814, and communication component 816.
The processing component 802 generally controls overall operation of the device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing components 802 may include one or more processors 820 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.
The memory 804 is configured to store various types of data to support operations at the apparatus 800. Examples of such data include instructions for any application or method operating on device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
The multimedia component 808 includes a screen that provides an output interface between the device 800 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the device 800 is in an operating mode, such as a shooting mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the apparatus 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.
The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.
The sensor assembly 814 includes one or more sensors for providing various aspects of state assessment for the device 800. For example, the sensor assembly 814 may detect the open/closed status of the device 800, the relative positioning of components, such as a display and keypad of the device 800, the sensor assembly 814 may also detect a change in the position of the device 800 or a component of the device 800, the presence or absence of user contact with the device 800, the orientation or acceleration/deceleration of the device 800, and a change in the temperature of the device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 816 is configured to facilitate communications between the apparatus 800 and other devices in a wired or wireless manner. The device 800 may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the apparatus 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.
In an exemplary embodiment, a non-transitory computer-readable storage medium, such as the memory 804, is also provided that includes computer program instructions executable by the processor 820 of the device 800 to perform the above-described methods.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (21)
1. A control device, comprising a control module, a storage module, a verification module, the storage module being connected to the control module and the verification module, wherein,
the check module is used for: when the control device is determined to be reset, executing N times of checking operations, wherein the checking operations comprise: after waiting for a preset time, verifying the running program in the storage module to obtain a verification result, wherein N is not less than 1 and is an integer;
the control module is used for: and executing the running program in the storage module under the condition that the verification result of one of the N times of verification operations is correct.
2. The apparatus according to claim 1, wherein the predetermined duration corresponding to the number of times of execution of the verification operation being 1 is longer than the predetermined duration corresponding to the number of times of execution being greater than 1.
3. The apparatus of claim 1, wherein the verification module comprises:
and the adjusting unit is used for setting the preset time length as a first time length under the condition that the checking module executes the checking operation for the first time.
4. The apparatus of claim 3, wherein the adjustment unit is further configured to:
setting the execution times of the checking operation to be M times and setting the preset time length to be a second time length when the checking result of the checking operation executed for the first time is incorrect checking,
wherein M > 1 and is an integer, and the second duration is less than the first duration.
5. The apparatus of claim 4, wherein the adjustment unit is further configured to:
setting the execution times of the checking operation as K times and setting the preset time length as a third time length when the checking results of the M times of checking operation are incorrect,
wherein K is greater than M and is an integer, and the third duration is less than the second duration.
6. The apparatus of claim 1, wherein the verification module comprises:
the checking unit is used for checking the running program;
and the time delay unit is connected with the verification unit and used for delaying the preset time length of the starting time of the verification unit.
7. The apparatus of claim 6, wherein the verification module further comprises:
and the cycle control unit is connected with the delay unit and the verification unit and is used for controlling the delay unit and the verification unit to execute S times of verification operation, wherein S is more than 1 and less than or equal to N.
8. The apparatus of claim 1, wherein the verification module is further configured to:
and when the verification results of the N times of verification operations are all verified incorrectly, interrupting the starting of the control module.
9. The apparatus of claim 1, wherein the apparatus is connected to an external device, and the verification module is further configured to:
and when the verification results of the N times of verification operations are all verified incorrectly, outputting a control signal to enable the external equipment to send the application program file to the storage module.
10. The apparatus of claim 1, wherein the storage module comprises a static random access memory.
11. A timing control circuit, wherein the timing control circuit is applied to a control device, the control device comprises a control module, a storage module and a check module, the storage module is connected to the control module and the check module, and the circuit comprises:
and the time delay module is connected with the verification module and used for delaying the starting time of the verification module for a first time length so that the verification module verifies the running program in the storage module after delaying the first time length to obtain a verification result, and the verification module controls the starting of the control module according to the verification result.
12. The circuit of claim 11, further comprising:
a cycle control module connected to the delay module and the check module for controlling the check module and the delay module to execute M times of check operations,
wherein the verifying operation comprises: the starting time of the checking module is delayed for a second time, then the running program in the storage module is checked to obtain a checking result, wherein M is more than 1 and is an integer,
wherein the second duration is less than the first duration.
13. The circuit of claim 12, further comprising:
an adjusting module connected to the cycle control module for setting the execution times of the check operation to K times and the delay time to a third time when the check results of the M check operations are all incorrect,
wherein K is greater than M and is an integer, and the third duration is less than the second duration.
14. A control method is applied to a control device, the control device comprises a control module and a storage module, and the method comprises the following steps:
when the control device is determined to be reset, executing N times of checking operations, wherein the checking operations comprise: after waiting for a preset time, verifying the running program in the storage module to obtain a verification result, wherein N is not less than 1 and is an integer;
and executing the running program in the storage module under the condition that the verification result of one of the N times of verification operations is correct.
15. The method according to claim 14, wherein the predetermined duration corresponding to the number of times of execution of the verification operation being 1 is longer than the predetermined duration corresponding to the number of times of execution being greater than 1.
16. The method of claim 14, further comprising:
and under the condition of executing the checking operation for the first time, setting the preset time length as a first time length.
17. The method of claim 16, further comprising:
setting the execution times of the checking operation to be M times and setting the preset time length to be a second time length when the checking result of the checking operation executed for the first time is incorrect checking,
wherein M > 1 and is an integer, and the second duration is less than the first duration.
18. The method of claim 17, further comprising:
setting the execution times of the checking operation as K times and setting the preset time length as a third time length when the checking results of the M times of checking operation are incorrect,
wherein K is greater than M and is an integer, and the third duration is less than the second duration.
19. A chip, wherein the chip comprises:
a control device according to any one of claims 1-10; or
The timing control circuit of any one of claims 11-13.
20. An electronic device, characterized in that the electronic device comprises a chip according to claim 19.
21. The electronic device of claim 20, wherein the electronic device comprises a display, a smartphone, or a portable device.
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