CN113228252A

CN113228252A - Three-dimensional memory device including signal lines and power connection lines extending through dielectric regions and method of fabricating the same

Info

Publication number: CN113228252A
Application number: CN201980086226.9A
Authority: CN
Inventors: 金吉妍; 金光浩; 外山史晃
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2019-05-07
Filing date: 2019-12-30
Publication date: 2021-08-06
Anticipated expiration: 2039-12-30
Also published as: CN113228252B; WO2020226704A1

Abstract

The invention discloses a three-dimensional memory device, comprising: a plurality of alternating stacks of insulating layers and conductive layers, the plurality of alternating stacks located over a substrate; a cluster of memory stack structures extending vertically through a respective one of the alternating stacks; and bit lines electrically connected to upper ends of respective subsets of the vertical semiconductor channels. In one embodiment, the subset of bit lines may include a corresponding multi-level structure. Each multi-level structure includes a bit line level bit line segment and an interconnect line segment located at a different level than the bit line level bit line segment. In another embodiment, alternating stacked groups may be alternatively recessed along a horizontal direction perpendicular to the bitlines to provide portions of dielectric material in laterally recessed regions. The metal line structure connecting the contact via structures may extend parallel to the bit lines to provide electrical connection between the word lines and the underlying field effect transistors.

Description

Three-dimensional memory device including signal lines and power connection lines extending through dielectric regions and method of fabricating the same

RELATED APPLICATIONS

This application claims priority to U.S. non-provisional patent application serial No. 16/404,844 and U.S. non-provisional patent application serial No. 16/404,961 filed on 7.5.2019, which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and in particular to a three-dimensional memory device including routing of bit lines, power supply lines, and connecting lines through dielectric regions and a method of fabricating the same.

Background

Three-dimensional semiconductor devices comprising three-dimensional vertical NAND strings With one bit per Cell are disclosed in an article entitled "Novel Ultra High Density Memory With Stacked Surrounding Gate Transistor (S-SGT) Structured cells," IEDM Proc. (2001)33-36, by t.endoh et al.

Disclosure of Invention

According to an embodiment of the present disclosure, a three-dimensional memory device includes: a first alternating stack of insulating layers and conductive layers, the first alternating stack being located over a substrate; a second alternating stack of insulating layers and conductive layers over the substrate and spaced apart from the first alternating stack; a cluster of memory stack structures extending vertically through the first alternating stack and the second alternating stack, wherein each memory stack structure comprises a memory film and a vertical semiconductor channel; and bit lines electrically connected to upper ends of respective subsets of the vertical semiconductor channels. Each bit line in the first subset of bit lines extends as a continuous line structure over the first and second alternating stacks and is vertically spaced apart from the substrate by a first interconnect level separation distance. Each bit line in the second subset of bit lines includes a respective multi-level structure, each multi-level structure including a bit line level bit line segment spaced apart from the substrate by a first interconnect level separation distance and an interconnect line segment spaced apart from the substrate by a distance different than the first interconnect level separation distance.

According to another embodiment of the present disclosure, a method of forming a three-dimensional memory device includes: forming first and second alternating stacks of insulating and conductive layers over a substrate and a cluster of memory stack structures extending vertically through the first and second alternating stacks, wherein each memory stack structure includes a memory film and a vertical semiconductor channel; and forming bit lines electrically connected to upper ends of respective subsets of the vertical semiconductor channels. Each bit line in the first subset of bit lines extends as a continuous line structure over the first and second alternating stacks and is vertically spaced apart from the substrate by a first interconnect level separation distance. Each bit line in the second subset of bit lines includes a respective multi-level structure, each multi-level structure including a bit line level bit line segment spaced apart from the substrate by a first interconnect level separation distance and an interconnect line segment spaced apart from the substrate by a distance different than the first interconnect level separation distance.

According to still another aspect of the present disclosure, a three-dimensional memory device includes: a peripheral circuit including a field effect transistor over a substrate; a lower level metal interconnect structure embedded in a lower level dielectric material layer overlying the field effect transistor and connected to a node of the field effect transistor; and an alternating stack of insulating layers and conductive layers, the alternating stack including word lines located above a lower level dielectric material layer, each alternating stack extending laterally along a first horizontal direction. The alternating stacked groups include odd groups alternating with even groups along a second horizontal direction perpendicular to the first horizontal direction. The alternately stacked odd groups each include: a first laterally projecting stair section on a first end; and a first retraction area on a second end opposite the first end along the first horizontal direction. The alternately stacked even groups each include: a second laterally projecting stair section on the second end between the two in the first retracted zone; and a second recessed area located between two of the first laterally projecting stair sections on a first end opposite the second end along the first horizontal direction. The device further comprises: a dielectric material portion located in the first recessed region and the second recessed region; a cluster of memory stack structures extending vertically through the alternating stacked groups; a word line contact via structure contacting the conductive layer; word line interconnect metal lines electrically connected to respective ones of the word line contact via structures and extending from over respective ones of the word lines over respective ones of the dielectric material portions along a second horizontal direction; and a through memory level word line connecting via structure electrically connected to a respective one of the word line interconnect metal lines and extending through a respective one of the dielectric material portions and electrically connected to a respective one of the lower level metal interconnect structures.

Drawings

Fig. 1A is a vertical cross-sectional view of a first example structure after forming a semiconductor device, a lower-level dielectric layer, a lower metal interconnect structure, and an in-process source-level material layer on a semiconductor substrate, according to a first embodiment of the present disclosure.

FIG. 1B is a top view of the first exemplary structure of FIG. 1A. The hinge vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 1A.

Fig. 1C is an enlarged view of the in-process source-level material layers taken along the vertical plane C-C of fig. 1B.

Fig. 1D is a top view of the first exemplary structure of fig. 1A-1C over a larger area than that shown in fig. 1B. The region B corresponds to the region shown in fig. 1B. The hinge vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 1A.

Fig. 2 is a vertical cross-sectional view of a first exemplary structure after forming first alternating stacks of first insulating layers and first layers of spacer material according to a first embodiment of the present disclosure.

Fig. 3 is a vertical cross-sectional view of a first example structure after patterning a first level stair well, a first backward stepped dielectric material portion, and an interlayer dielectric layer, according to a first embodiment of the present disclosure.

Fig. 4A is a vertical cross-sectional view of a first example structure after forming a first layer of memory openings and a first layer of support openings, according to a first embodiment of the present disclosure.

Fig. 4B is a horizontal cross-sectional view of the first exemplary structure of fig. 4A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 4A.

Fig. 5 is a vertical cross-sectional view of a first exemplary structure after forming various sacrificial fill structures according to a first embodiment of the present disclosure.

Fig. 6 is a vertical cross-sectional view of the first exemplary structure after forming the second alternating stack of second insulating layers and second spacer material layers, the second stepped surface, and the second backward stepped dielectric material portion, according to the first embodiment of the present disclosure.

Fig. 7A is a vertical cross-sectional view of a first example structure after forming a second-tier memory opening and a second-tier support opening, in accordance with a first embodiment of the present disclosure.

Fig. 7B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of fig. 7A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 7A.

Fig. 8 is a vertical cross-sectional view of a first example structure after forming an interlayer memory opening and an interlayer support opening, according to a first embodiment of the present disclosure.

Fig. 9A-9D illustrate sequential vertical cross-sectional views of a memory opening during formation of a memory opening fill structure, according to a first embodiment of the present disclosure.

Fig. 10A is a vertical cross-sectional view of a first example structure after forming a memory opening fill structure and support pillar structures, according to a first embodiment of the present disclosure.

Fig. 10B is a top view of the first exemplary structure of fig. 10A. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 10A.

Fig. 10C is a top view of the first exemplary structure of fig. 10A and 10B over a larger area than that shown in fig. 10B. The region B corresponds to the region shown in fig. 10B. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 10A.

Fig. 10D is a vertical cross-sectional view of the first exemplary structure taken along the hinge vertical plane D-D' of fig. 10C.

Fig. 11A is a vertical cross-sectional view of a first example structure after forming a first contact level dielectric layer and backside trenches, according to a first embodiment of the present disclosure.

FIG. 11B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of FIG. 11A. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 11A.

Fig. 11C is a top view of the first exemplary structure of fig. 11A and 11B over a larger area than that shown in fig. 11B. The region B corresponds to the region shown in fig. 10B. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 11A.

FIG. 11D is a vertical cross-sectional view of the first exemplary structure taken along the hinge vertical plane D-D' of FIG. 11C.

Fig. 12 is a vertical cross-sectional view of a first exemplary structure after formation of backside trench spacers according to a first embodiment of the present disclosure.

Fig. 13A-13E illustrate sequential vertical cross-sectional views of a memory opening fill structure and backside trenches during formation of a source-level material layer, in accordance with a first embodiment of the present disclosure.

Fig. 14 is a vertical cross-sectional view of a first example structure after forming a source-level material layer, according to a first embodiment of the present disclosure.

Fig. 15 is a vertical cross-sectional view of a first exemplary structure after forming a backside recess according to a first embodiment of the present disclosure.

Fig. 16 is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer according to a first embodiment of the present disclosure.

Fig. 17A is a vertical cross-sectional view of a first example structure after forming a backside trench fill structure in a backside trench, according to a first embodiment of the present disclosure.

Fig. 17B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of fig. 17A. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 17A.

Fig. 17C is a top view of the first exemplary structure of fig. 17A and 17B over a larger area than that shown in fig. 17B. The region B corresponds to the region shown in fig. 17B. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 17A.

Fig. 17D is a vertical cross-sectional view of the first exemplary structure taken along the hinge vertical plane D-D' of fig. 17C.

Fig. 17E is a vertical cross-sectional view of the first exemplary structure taken along vertical plane E-E' of fig. 17B.

Figure 18A is a vertical cross-sectional view of a first example structure after forming a through memory level via structure, according to a first embodiment of the present disclosure.

Fig. 18B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of fig. 18A. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 18A.

Fig. 18C is a top view of the first exemplary structure of fig. 18A and 18B over a larger area than that shown in fig. 18B. The region B corresponds to the region shown in fig. 18B. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 18A.

FIG. 18D is a vertical cross-sectional view of the first exemplary structure taken along the hinge vertical plane D-D' of FIG. 18C.

Fig. 19A is a vertical cross-sectional view of the first example structure after forming a second contact level dielectric layer and contact via cavities according to the first embodiment of the present disclosure.

Fig. 19B is a top view of the first exemplary structure of fig. 19A. The hinge vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 19A.

Fig. 19C is a vertical cross-sectional view of the first exemplary structure taken along the hinge vertical plane C-C of fig. 19B.

Fig. 20A is a vertical cross-sectional view of a first example structure after forming a first line level trench, according to a first embodiment of the present disclosure.

Fig. 20B is a top view of the first exemplary structure of fig. 20A. The hinge vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 20A.

Fig. 20C is a vertical cross-sectional view of the first exemplary structure taken along the hinge vertical plane C-C of fig. 20B.

Fig. 20D is an enlarged view of region D of fig. 20B.

Fig. 21A is a vertical cross-sectional view of a first example structure after forming a contact via structure and a first line level structure, according to a first embodiment of the present disclosure.

Fig. 21B is a top view of the first exemplary structure of fig. 21A. The hinge vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 21A.

Fig. 21C is a vertical cross-sectional view of the first exemplary structure taken along vertical plane C-C of fig. 21B.

Fig. 21D is an enlarged view of region D of fig. 21B.

Fig. 22A is a vertical cross-sectional view of a first example structure after forming a first interconnect-level dielectric layer, a first via-level structure, and a second line-level structure, according to a first embodiment of the present disclosure.

Fig. 22B is a top view of the first exemplary structure of fig. 22A. The hinge vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 22A.

Fig. 22C is a vertical cross-sectional view of the first exemplary structure taken along the hinge vertical plane C-C of fig. 22B.

Fig. 22D is a partial perspective enlarged view of region D of fig. 22B.

FIG. 22E is a schematic vertical cross-sectional view of the bit line taken along the zig-zag vertical cross-sectional plane E-E' of FIG. 22D.

Fig. 23A is a vertical cross-sectional view of a first example structure after forming additional dielectric layers, additional metal interconnect structures, and bond pads, in accordance with a first embodiment of the present disclosure.

Fig. 23B is another vertical cross-section of the first exemplary structure of fig. 23A.

Fig. 23C is another schematic vertical cross-section of the first exemplary structure of fig. 23A and 23B.

Fig. 23D is a vertical cross-sectional view of an alternative configuration of the first exemplary structure.

Fig. 24A is a vertical cross-sectional view of a second exemplary structure after the processing steps of fig. 1A-1D, according to a second embodiment of the present disclosure.

Fig. 24B is a top view of the second exemplary structure of fig. 24A.

Fig. 25A is a vertical cross-sectional view of a second exemplary structure after the processing steps of fig. 10A-10D, according to a second embodiment of the present disclosure.

Fig. 25B is a top view of the second exemplary structure of fig. 25A. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 25A.

FIG. 25C is a top view of the second exemplary structure of FIGS. 25A and 25B over a larger area than that shown in FIG. 25B; the region B corresponds to the region shown in fig. 25B. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 10A.

Fig. 26A is a vertical cross-sectional view of a second example structure after forming backside trenches, according to a second embodiment of the present disclosure.

Fig. 26B is a top view of the second exemplary structure of fig. 25A. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 26A.

Fig. 27 is a vertical cross-sectional view of a second exemplary structure after the processing steps of fig. 17A-17E, according to a second embodiment of the present disclosure.

Fig. 28A is a vertical cross-sectional view of a second example structure after forming a through memory level via structure, according to a second embodiment of the present disclosure.

Fig. 28B is a top view of the second exemplary structure of fig. 28A. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 28A.

Fig. 28C is a top view of the second exemplary structure of fig. 25A and 25B over a larger area than that shown in fig. 28B. The region B corresponds to the region shown in fig. 25B. The hinge vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 10A.

Fig. 28D is a vertical cross-sectional view of the second exemplary structure taken along the hinge vertical plane D-D' of fig. 28C.

Fig. 29A is a vertical cross-sectional view of a second example structure after forming a contact via structure and a first line level structure, according to a second embodiment of the present disclosure.

Fig. 29B is a top view of the second exemplary structure of fig. 29A. The hinge vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 29A.

Fig. 29C is a vertical cross-sectional view of the second exemplary structure taken along the hinge vertical plane C-C of fig. 29B.

Fig. 30A is a vertical cross-sectional view of a second example structure after forming a first interconnect-level dielectric layer, a first via-level structure, and a second line-level structure, according to a second embodiment of the present disclosure.

Fig. 30B is another vertical cross-sectional view of the second exemplary structure of fig. 30A taken along the hinge vertical plane C-C of fig. 29B.

Fig. 31A is a vertical cross-sectional view of a second example structure after forming additional dielectric layers, additional metal interconnect structures, and bond pads, in accordance with a second embodiment of the present disclosure.

Fig. 31B is a perspective view of a region of the second exemplary structure of fig. 31A.

Detailed Description

As discussed above, the present disclosure relates to three-dimensional memory devices including routing of signal and power lines and vias through dielectric regions, such as level-shifted bit line routing and lateral word line connection routing through dielectric regions, and methods of fabricating the same, various embodiments of which are described in detail herein. Embodiments of the present disclosure may be used to form various semiconductor devices, such as three-dimensional monolithic memory array devices including a plurality of NAND memory strings.

In a conventional three-dimensional memory device, openings are etched through the entire word line stack to form via structures that provide signals and power from above the three-dimensional memory device to driver circuits located below the word line stack. The via structure consumes large area and increases processing cost to form an opening through the entire word line stack. Various embodiments are disclosed that form via structures in dielectric-filled bitline break regions located in the middle of a wordline stack. The bit line break region may be a region within the memory array region where word lines and memory opening fill structures (i.e., channels, drains, and memory films) are not present. By providing via structures in the bitline break area and free staircase area at the wordline wiring locations, processing costs can be significantly reduced by simplifying the processing steps. Furthermore, underutilized dielectric fill regions of such via structures may be utilized, which increases device density.

The figures are not drawn to scale. Where a single instance of an element is illustrated, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated to be absent repetition of the element. Ordinal numbers such as "first," "second," and "third" may be used merely to identify similar elements, and different ordinal numbers may be employed throughout the specification and claims of the present disclosure. The same reference numerals indicate the same elements or similar elements. Elements having the same reference numerals are assumed to have the same composition and the same function unless otherwise specified. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. As used herein, a first element that is positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element may be positioned "directly" on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

As used herein, "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of an underlying structure or an overlying structure, or may have an extent that is less than the extent of an underlying structure or an overlying structure. In addition, a layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above and/or below.

As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight in a direction that deviates from vertical by an angle of less than 5 degrees. The vertical plane or substantially vertical plane is straight in the vertical direction or substantially vertical direction and may or may not include a bend in a direction perpendicular to the vertical direction or substantially vertical direction. As used herein, a "memory level" or "memory array level" refers to a level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through stacked" element refers to an element that extends vertically through a memory level.

As used herein, "semiconductor material" is meant to have a chemical composition of 1.0X 10^-5S/m to 1.0X 10⁵A material having an electrical conductivity in the range of S/m. As used herein, "semiconductor material" refers to a material having a molecular weight of 1.0 x 10 in the absence of an electrical dopant therein^-5A material having an electrical conductivity in the range of S/m to 1.0S/m and capable of being produced with appropriate doping of an electrical dopant having a conductivity in the range of 1.0S/m to 1.0 x 10⁷A doping material of a conductivity in the range of S/m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to a valence band within the band structure, or an n-type dopant that adds electrons to a conduction band within the band structure. As used herein, "conductive material" means having a thickness of greater than 1.0 x 10⁵A material of S/m conductivity. As used herein, "insulator material" or "dielectric material" is meant to have a thickness of less than 1.0 x 10^-5A material of S/m conductivity. As used herein, "heavily doped semiconductor material" refers to a material that is doped with an electrical dopant at a sufficiently high atomic concentration to become conductive (i.e., provide greater than 1.0 x 10) when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initial amorphous state)⁵S/m conductivity). ' mixingThe hetero semiconductor material "may be a heavily doped semiconductor material, or may be a material including a hetero semiconductor material provided at 1.0 × 10^-5S/m to 1.0X 10⁷A semiconductor material of electrical dopant (i.e., p-type dopant and/or n-type dopant) at a concentration of conductivity in the range of S/m. "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, the semiconductor material may be semiconducting or conducting, and may be intrinsic or doped semiconductor material. The doped semiconductor material may be semiconducting or conducting, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material including at least one metallic element therein. All conductivity measurements were performed under standard conditions.

A monolithic three dimensional memory array is an array in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, without an intervening substrate. The term "monomer" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. Instead, a two-dimensional array may be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Pat. No. 5,915,167 entitled "Three-dimensional Structure Memory," a non-monolithic stacked Memory is constructed by forming Memory levels on separate substrates and vertically stacking the Memory levels. The substrate may be thinned or removed from the memory levels prior to bonding, but since the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays. The substrate may include integrated circuits fabricated thereon, such as driver circuits for memory devices.

Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices, and may be fabricated employing the various embodiments described herein. The monolithic three-dimensional NAND string is positioned in a monolithic three-dimensional array of NAND strings over a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

Generally, a semiconductor package (or "package") refers to a unitary semiconductor device that may be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "dies") bonded therein, such as by flip-chip bonding or another die-to-die bonding. A package or chip may include a single semiconductor die (or "die") or a plurality of semiconductor dies. The die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip having multiple dies is capable of executing as many external commands as the total number of planes therein at the same time. Each die includes one or more planes. The same concurrent operation may be performed in each plane within the same die, but there may be some limitations. Where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations may be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks") which are the smallest units that can be erased by a single erase operation. Each memory block contains a number of pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

Referring to fig. 1A to 1D, a first exemplary structure according to a first embodiment of the present disclosure is shown. Fig. 1C is an enlarged view of the source-level material layer 10' in the process shown in fig. 1A and 1B. FIG. 1D is a top view of the first exemplary structure at a larger scale than the top view of FIG. 1B. A first exemplary structure may include a substrate 8 and a semiconductor device 710 formed thereon. The substrate 8 may include a substrate semiconductor layer 9 at least at an upper portion thereof. Shallow trench isolation structures 720 may be formed in an upper portion of the substrate semiconductor layer 9 to provide electrical isolation from other semiconductor devices. Semiconductor device 710 may include, for example, field effect transistors that include respective transistor active regions 742 (i.e., source and drain regions), channel regions 746, and gate structures 750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, dielectric gate spacers 756, and a gate capping dielectric 758. The semiconductor device 710 may include any semiconductor circuitry, commonly referred to as driver circuitry, also referred to as peripheral circuitry, to support operation of a memory structure to be subsequently formed. As used herein, peripheral circuitry 712 refers to any, each, or all of word line decoder circuitry, word line switching circuitry, bit line decoder circuitry, bit line sensing and/or switching circuitry, power supply/distribution circuitry, data buffers and/or latches, or any other semiconductor circuitry that may be implemented outside of the memory array structure of the memory device. For example, the semiconductor device 710 may include a word line switching device for electrically biasing a word line of a three-dimensional memory structure to be subsequently formed, and a sense amplifier electrically connected to a bit line to be subsequently formed.

A layer of dielectric material, referred to herein as a lower-level dielectric material layer 760, may be formed over the semiconductor device 710. The lower-level dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and/or applies appropriate stress to underlying structures), a first dielectric material layer 764 overlying the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier layer) 766 overlying the first dielectric material layer 764, and at least one second dielectric layer 768.

A dielectric layer stack, which includes a lower level dielectric material layer 760, may serve as a matrix of lower level metal interconnect structures 780 that provide electrical routing to and from various nodes of landing pads of the semiconductor device 710 and through memory level via structures to be subsequently formed. A lower-level metal interconnect structure 780 may be formed within the dielectric layer stack of the lower-level dielectric material layer 760 and comprise a lower-level metal line structure positioned below and optionally contacting a bottom surface of the silicon nitride layer 766.

For example, a lower-level metal interconnect structure 780 may be included within the first dielectric material layer 764. The first dielectric material layer 764 may be a plurality of dielectric material layers in which the various elements of the lower-level metal interconnect structure 780 are sequentially formed. Each dielectric material layer selected from the first dielectric material layers 764 may include any of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and a dielectric metal oxide, such as aluminum oxide. In one embodiment, the first dielectric material layer 764 may comprise or consist essentially of a layer of dielectric material having a dielectric constant that does not exceed the dielectric constant of 3.9 for undoped silicate glass (silicon oxide). The lower-level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes that contact respective source and drain nodes or gate electrode contacts of the device), an intermediate lower-level metal line structure 784, a lower-level metal via structure 786, and a landing pad level metal line structure 788, which may be configured to serve as a landing pad for a through memory level via structure to be subsequently formed.

A landing pad level metal line structure 788 may be formed within a topmost dielectric material layer of the first dielectric material layer 764 (which may be a plurality of dielectric material layers). Each of the lower-level metal interconnect structures 780 may include a metal nitride liner and a metal fill structure. The top surface of the landing pad level metal line structure 788 and the topmost surface of the first dielectric material layer 764 may be planarized by a planarization process such as chemical mechanical planarization. A silicon nitride layer 766 may be formed directly on the top surface of landing pad level metal line structure 788 and the topmost surface of first dielectric material layer 764.

The at least one second dielectric material layer 768 can include a single dielectric material layer or multiple dielectric material layers. Each dielectric material layer selected from the at least one second dielectric material layer 768 can comprise any of a doped silicate glass, an undoped silicate glass, and an organosilicate glass. In one embodiment, the at least one second layer 768 of dielectric material may include or consist essentially of a layer of dielectric material having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide).

An optional layer of metal material and a layer of semiconductor material may be deposited over at least one second layer of dielectric material 768 or within a patterned recess of the second layer of dielectric material and lithographically patterned to provide an optional conductive plate layer 6 and an in-process source-level material layer 10'.

The optional conductive plate layer 6 (if present) provides a highly conductive conduction path for current flow into or out of the source level material layer 10' during processing. Optionally conductive plate layer 6 comprises a conductive material such as a metal or a heavily doped semiconductor material. The optional conductive plate layer 6 may for example comprise a tungsten layer having a thickness in the range of 3nm to 100nm, although smaller and larger thicknesses may also be used.

A metal nitride layer (not shown) may be provided on top of the conductive plate layer 6 as a diffusion barrier layer. The conductive plate layer 6 may be used as a special source line in the finished device. Further, conductive plate layer 6 may comprise an etch stop layer and may comprise any suitable conductive, semiconductive, or insulating layer.

Optionally, conductive plate layer 6 may comprise a metal compound material such as a conductive metal nitride (e.g., TiN) and/or a metal (e.g., W). The thickness of the optional conductive plate layer 6 may be in the range of 5nm to 100nm, but lesser and greater thicknesses may also be used.

Referring to fig. 1C, the in-process source-level material layer 10' may include various layers that may be subsequently modified to form a source-level material layer. The source-level material layer, when formed, includes a source contact layer that serves as a common source region for vertical field effect transistors of the three-dimensional memory device. In one implementation, the in-process source-level material layers 10' may include, from bottom to top, lower source-level material layers 112, lower sacrificial pads 103, source-level sacrificial layers 104, upper sacrificial pads 105, upper source-level semiconductor layers 116, source-level insulating layers 117, and optional source select-level conductive layers 118.

Lower source-level semiconductor layer 112 and higher source-level semiconductor layer 116 may comprise a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source-level material layer 112 and the higher source-level semiconductor layer 116 may be opposite to the conductivity of a vertical semiconductor channel to be subsequently formed. For example, if the vertical semiconductor channel to be subsequently formed has a doping of a first conductivity type, the lower source-level material layer 112 and the higher source-level semiconductor layer 116 have a doping of a second conductivity type opposite to the first conductivity type. The thickness of each of the lower source-level material layer 112 and the higher source-level semiconductor layer 116 may be in a range of 10nm to 300nm, such as 20nm to 150nm, although lesser and greater thicknesses may also be used.

The source-level sacrificial layer 104 may comprise a sacrificial material that is selectively removable for the lower sacrificial liner 103 and the upper sacrificial liner 105. In one embodiment, source-level sacrificial layer 104 may comprise a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source-level sacrificial layer 104 may be in the range of 30nm to 400nm, such as 60nm to 200nm, although lesser and greater thicknesses may also be used.

The lower sacrificial liner 103 and the upper sacrificial liner 105 comprise materials that may be used as etch stop materials during removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 may comprise silicon oxide, silicon nitride, and/or a dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 may comprise a silicon oxide layer having a thickness in the range of 2nm to 30nm, although lesser and greater thicknesses may also be used.

The source-level insulating layer 117 may comprise a dielectric material, such as silicon oxide. The thickness of the source-level insulating layer 117 may be in the range of 20nm to 400nm, such as 40nm to 200nm, although lesser and greater thicknesses may also be used. Optional source select level conductive layer 118 may comprise a conductive material that may serve as a source select level gate electrode. For example, optional source select level conductive layer 118 may comprise a doped semiconductor material such as doped polysilicon or doped amorphous silicon, which may be subsequently converted to doped polysilicon by an annealing process. The thickness of optional source select level conductive layer 118 may be in the range of 30nm to 200nm, such as 60nm to 100nm, although lesser and greater thicknesses may also be used.

In-process source-level material layer 10' may be formed directly over a subset of semiconductor devices 710 on substrate 8 (e.g., a silicon wafer). As used herein, a first element is positioned "directly above" a second element if the first element is positioned above a horizontal plane that includes the topmost surface of the second element and the area of the first element and the area of the second element has an area overlap in plan view (i.e., along a vertical plane or direction that is perpendicular to the top surface of the substrate 8).

The optional conductive plate layer 6 and the in-process source-level material layer 10' may be patterned to provide openings in areas where through memory-level via structures and through dielectric contact via structures are to be subsequently formed. A patterned portion of the stack of conductive plate layer 6 and in-process source-level material layer 10' is present in each memory array region (also referred to as "memory region") 100 in which a three-dimensional memory stack structure will be subsequently formed. A patterned portion of the stack of conductive plate layer 6 and in-process source-level material layer 10' may be present in each stair region 200 that laterally surrounds a respective one of the memory array regions 100.

The semiconductor device 710 and the combined region of the lower-level dielectric material layer 760 and the lower-level metal interconnect structure 780, which is positioned below the memory-level components to be subsequently formed and includes peripheral devices for the memory-level components, are referred to herein as the underlying supported device region 700. A lower-level metal interconnect structure 780 is formed in the lower-level dielectric material layer 760.

Each memory array region 100 may have a rectangular shape with sides extending along a first horizontal direction hd1 (e.g., a word line direction) and along a second horizontal direction hd2 (e.g., a bit line direction) perpendicular to the first horizontal direction hd 1. The plurality of memory array regions 100 may be laterally spaced apart from one another along the second horizontal direction hd 2. An inter-array connection via region 600 (which is also referred to as a connection via region or a bitline break region) or a bitline landing region 500 (which is also referred to as a bitline lap region for bitline landing) may be provided between each adjacent pair of memory array regions 100 surrounded by a respective one of the stair regions 200. The bit line termination region 500 is a region in which vertical interconnects are subsequently formed between bit lines and bit line peripheral circuitry 712, such as the underlying sense amplifier circuitry and bit line driver circuitry that support the device region 700. The inter-array connection via region 600 is a region in which via structures are to be formed for electrical connection to peripheral circuitry 712 in the underlying supported device region 700 and/or via structures are to be subsequently formed for electrical signal connection between other nodes of the memory stack structure and corresponding supported circuitry of the underlying supported device region 700 is to be subsequently formed. For example, the source power distribution network may include a through memory level via structure to be subsequently formed in the inter-array connecting via region 600.

Peripheral connection region 400 is laterally spaced from memory array region 100 along a first horizontal direction hd1 (e.g., a word line direction). Peripheral connection region 400 may include row decoder circuit connections (such as via structures for providing electrical connections from row decoder circuits to word lines) that include conductive layers within the alternating stack of insulating layers and conductive layers in memory array region 100 and staircase region 200. Word line contact via structures may then be formed in a section of the stair-step region 200 near the peripheral connection region 400 and may be electrically connected to semiconductor devices in the support device region 700 through additional through-memory level via structures to be subsequently formed in the peripheral connection region 400.

The optional conductive plate layer 6 and in-process source-level material layer 10' may be present in the memory array region 100 and stair regions 200, and may not be present in the areas of the bit line wiring regions 500, inter-array connection via regions 600, and peripheral connection regions 400. The memory array region 100, staircase region 200, peripheral connection region 400, bit line wiring region 500, and inter-array connection via region 600 shown in figure 1D may comprise the entire memory plane or a portion of the memory plane. One or more memory planes may be formed on the same substrate 8.

The lower-level metal interconnect structure 780 may be electrically connected to an active node (e.g., a transistor active region 742 or a gate electrode 754) of a semiconductor device 710 (e.g., a CMOS device) and may be positioned at a level of the lower-level dielectric layer 760. A through memory level via structure may then be formed directly on the lower level metal interconnect structure 780 to provide electrical connection to a memory device to be subsequently formed. In one embodiment, the pattern of lower-level metal interconnect structures 780 may be selected such that landing pad-level metal line structures 788 (which are a subset of lower-level metal interconnect structures 780 positioned at a topmost portion of lower-level metal interconnect structures 780) may provide landing pad structures for through memory-level via structures to be subsequently formed.

Referring to fig. 2, an alternating stack of first material layers and second material layers is then formed. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. Where at least one other alternating stack of material layers is subsequently formed over the alternating stack of first and second material layers, the alternating stack is referred to herein as a first layer alternating stack. The level of the first-level alternating stack is referred to herein as the first-level, and the level of the alternating stack to be subsequently formed directly above the first-level is referred to herein as the second-level, and so on.

The first layer alternating stack may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first layer of spacer material may be a layer of sacrificial material that is subsequently replaced by a conductive layer. In another embodiment, the first layer of spacer material may be a conductive layer that is not subsequently replaced by other layers. While the present disclosure is described using an embodiment in which a sacrificial material layer is replaced with a conductive layer, embodiments in which a spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are expressly contemplated herein.

In one embodiment, the first material layer and the second material layer may be the first insulating layer 132 and the first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. Alternating layers of first insulating layers 132 and first sacrificial materials 142 are formed over the source-level material layers 10' in the process. As used herein, "sacrificial material" refers to material that is removed during subsequent processing steps.

As used herein, the alternating stack of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of a first element that is not an end element of the alternating plurality of elements abuts two instances of a second element on both sides, and each instance of a second element that is not an end element of the alternating plurality of elements abuts two instances of the first element on both ends. The first elements may have the same thickness therein, or may have different thicknesses. The second elements may have the same thickness therein, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of a first material layer or an instance of a second material layer and may end with an instance of a first material layer or an instance of a second material layer. In one embodiment, the instances of the first element and the instances of the second element may form a unit that repeats periodically within alternating multiple elements.

The first alternating stack of layers (132,142) can include a first insulating layer 132 composed of a first material, and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively to the first material of the first insulating layer 132. As used herein, the removal of a first material is "selective" for a "second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process for the first material relative to the second material.

The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced with a conductive electrode, which may serve, for example, as a control gate electrode for a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by Chemical Vapor Deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the pair of first insulating layer 132 and first sacrificial material layer 142 can be in the range of 2 to 1,024, and typically in the range of 8 to 256, although more repetitions can also be used. In one embodiment, each first sacrificial material layer 142 in the alternating stack of first layers (132,142) may have a uniform thickness that is substantially constant within each respective first sacrificial material layer 142.

A first insulating cap layer 170 may then be formed over the first alternating layer stack (132, 142). The first insulating cap layer 170 comprises a dielectric material, which may be any dielectric material that may be used for the first insulating layer 132. In one implementation, the first insulating cap layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating cap layer 170 may be in the range of 20nm to 300nm, although lesser and greater thicknesses may also be used.

Referring to fig. 3, the first insulating cap layer 170 and the first alternating stack of layers (132,142) may be patterned to form a first stepped surface in the stair zone 200. Stair zone 200 may include respective first and second stepped regions, in which a first stepped surface may be formed, in which a second stepped surface may be subsequently formed in a second layer structure (which is subsequently formed over the first layer structure) and/or in an additional layer structure. The first stepped surface may be formed, for example, by forming a masking layer (not shown) having an opening therein, etching a cavity within the level of the first insulating cap layer 170 and iteratively expanding the etched region, and vertically recessing the cavity by etching each first insulating layer 132 and first sacrificial material layer 142 pair positioned directly below the bottom surface of the etched cavity within the etched region. In one embodiment, the top surface of the first sacrificial material layer 142 may be physically exposed at the first stepped surface. The cavity overlying the first stepped surface is referred to herein as a first stepped cavity.

Patterned portions of the first insulating cap layer 170 and the alternating stacks of first layers (132,142) may be present within the memory array region 100 and in the stair regions 200 without extending to the inter-array connection via region 600, the bit line connection region 500, or the peripheral connection region 400. The first stepped surface may be located within the outer annular section of each stair zone 200. As used herein, an "annular" element refers to any element having an opening therethrough, and the shape of the opening may be circular, elliptical, polygonal, or any closed curve two-dimensional shape. Thus, a stepped cavity may laterally surround each of the memory array regions 100.

A dielectric fill material, such as undoped silicate glass or doped silicate glass, may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the region of the dielectric fill material filling the overlying first stepped surface constitutes a first rearwardly stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to vertical distance from a top surface of a substrate on which the element is present. The first alternating stack of layers (132,142) and the first retro-stepped dielectric material portion 165 collectively constitute a first layer structure that is an in-process structure that is subsequently modified.

An interlevel dielectric layer 180 may optionally be deposited over the first level structure (132,142,170,165). The interlayer dielectric layer 180 includes a dielectric material such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may comprise a doped silicate glass having a greater etch rate than the material of the first insulating layer 132 (which may comprise undoped silicate glass). For example, the interlayer dielectric layer 180 may include phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30nm to 300nm, but smaller and larger thicknesses may also be used.

Referring to fig. 4A and 4B, various first level openings (149,129) may be formed through the interlayer dielectric layer 180 and the first level structure (132,142,170,165) and into the in-process source-level material layer 10'. A photoresist layer (not shown) may be applied over the interlayer dielectric layer 180 and may be lithographically patterned to form various openings therethrough. The pattern of openings in the photoresist layer may be transferred through the interlayer dielectric layer 180 and the first level structure (132,142,170,165) and into the in-process source-level material layer 10' by a first anisotropic etch process to form various first-level openings (149,129) simultaneously (i.e., during the first isotropic etch process). Various first layer openings (149,129) may include first layer memory opening 149 and first layer support opening 129. The location of the steps S in the first layer alternating stack (132,142) is shown in dashed lines in FIG. 4B.

First-tier memory openings 149 are openings formed in the memory array region 100 through each tier within the first-tier alternating stack (132,142) and are subsequently used to form memory stack structures therein. The first-layer memory openings 149 may be formed as clusters of first-layer memory openings 149 that are laterally spaced apart along the second horizontal direction hd 2. Each cluster of first layer memory openings 149 may be formed as a two-dimensional array of first layer memory openings 149.

The first layer support openings 129 are openings formed in the stair way regions 200 and are subsequently used to form stair way region contact via structures that interconnect respective pairs of underlying lower-level metal interconnect structures 780 (such as landing pad level metal line structures 788) and conductive layers (which may be formed as one of the spacer material layers or may be formed by replacing sacrificial material layers within the conductive layers). A subset of the first layer support openings 129 formed through the first rearwardly stepped dielectric material portion 165 may be formed through respective horizontal surfaces of the first stepped surface. Further, each of the first-level support openings 129 may be formed directly over (i.e., over and with an area overlap with) a respective one of the lower-level metal interconnect structures 780.

In one embodiment, the first anisotropic etch process may include an initial step in which the material of the first alternating stack (132,142) of layers is etched simultaneously with the material of the first backward-stepped dielectric material portion 165. The chemistry of the initial etching steps can be alternated to optimize the etching of the first and second materials in the first layer alternating stack (132,142) while providing an average etch rate comparable to the material of the first backward stepped dielectric material portion 165. The first anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reactive etch process (e.g., CF)₄/O₂/Ar etching). The sidewalls of the various first layer openings (149,129) may be substantially vertical, or may be tapered.

After etching through the alternating stacks (132,142) and the first retro-stepped dielectric material portions 165, the chemistry of the terminal portion of the first anisotropic etch process can be selected to etch one or more dielectric materials through the at least one second dielectric layer 768 at an etch rate higher than the average etch rate of the in-process source-level material layer 10'. For example, the termination portion of the anisotropic etching process can include a step of etching one or more dielectric materials of the at least one second dielectric layer 768 that are selective to semiconductor material within a component layer in the in-process source-level material layer 10'. In one embodiment, a terminal portion of the first anisotropic etch process may etch through the source select level conductive layer 118, the source level insulating layer 117, the upper source level semiconductor layer 116, the upper sacrificial liner 105, the source level sacrificial layer 104, and the lower sacrificial liner 103, and at least partially into the lower source level semiconductor layer 112. The terminal portion of the first anisotropic etch process may include at least one etch chemistry for the various semiconductor materials of the source-level material layer 10' during the etching process. The photoresist layer may then be removed, for example, by ashing.

Optionally, the portions of first layer memory openings 149 and first layer support openings 129 at the level of interlevel dielectric layer 180 may be laterally expanded by isotropic etching. In this case, the interlayer dielectric layer 180 may include a dielectric material (such as borosilicate glass) having a greater etch rate in dilute hydrofluoric acid than the first insulating layer 132 (which may include undoped silicate glass). An isotropic etch, such as a wet etch using HF, may be used to extend the lateral dimensions of the first layer memory opening 149 at the level of the interlayer dielectric layer 180. The portion of the first-level memory opening 149 positioned at a level of the interlevel dielectric layer 180 may optionally be widened to provide a larger landing pad for a second-level memory opening that will subsequently be formed through the second-level alternating stack (subsequently formed prior to forming the second-level memory opening).

Referring to fig. 5, sacrificial first layer opening fill portions (148,128) may be formed in various first layer openings (149,129). For example, a sacrificial first layer of fill material is simultaneously deposited in each of the first layer openings (149,129). The sacrificial first layer fill material may comprise a material that may be subsequently removed selectively to the material of the first insulating layer 132 and the first sacrificial material layer 142.

In one embodiment, the sacrificial first layer fill material may comprise a semiconductor material, such as silicon (e.g., a-Si or polysilicon), a silicon germanium alloy, germanium, a III-V compound semiconductor material, or combinations thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer with a thickness in the range of 1nm to 3 nm) may be used prior to depositing the sacrificial first layer of fill material. The sacrificial first layer of fill material may be formed by a non-conformal deposition or a conformal deposition method.

In another embodiment, the sacrificial first layer fill material may comprise a silicon oxide material having a higher etch rate than the materials of the first insulating layer 132, the first insulating cap layer 170, and the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may comprise borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of dense TEOS oxide (i.e., silicon oxide material formed by decomposing tetraethylorthosilicate glass in a chemical vapor deposition process and then densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1nm to 3 nm) may be used prior to depositing the sacrificial first layer of fill material. The sacrificial first layer of fill material may be formed by a non-conformal deposition or a conformal deposition method.

In yet another embodiment, the sacrificial first layer fill material may comprise amorphous silicon or a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently removed selectively to the material of the first layer alternating stack (132, 142).

Portions of the deposited sacrificial material may be removed from over a topmost layer of the first alternating stack (132,142), such as from over the interlevel dielectric layer 180. For example, the sacrificial first layer of fill material may be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, Chemical Mechanical Planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may serve as an etch stop layer or a planarization stop layer.

The remaining portion of the sacrificial first layer of fill material comprises a sacrificial first layer opening fill portion (148,128). Specifically, each remaining portion of the sacrificial material in the first layer memory openings 149 constitutes a sacrificial first layer memory opening fill portion 148. Each remaining portion of the sacrificial material in the first layer support opening 129 constitutes a sacrificial first layer support opening fill portion 128. Various sacrificial first layer opening fill portions (148,128) are formed simultaneously, i.e., during the same set of processes, including a deposition process that deposits a sacrificial first layer fill material and a planarization process that removes the first layer deposition process from over the alternating first layer stacks (132,142), such as from over the top surface of the interlayer dielectric layer 180. A top surface of the sacrificial first layer opening filling portion (148,128) may be coplanar with a top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening fill portions (148,128) may or may not include a cavity therein.

Referring to fig. 6, a second layer structure may be formed over the first layer structure (132,142,170,148). The second layer structure may comprise additional alternating stacks of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack of layers of material (232,242) may then be formed on the top surface of the first alternating stack of layers (132, 142). The second alternating stack of layers (232,242) may include alternating pluralities of third and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

In one embodiment, the third material layer may be a second insulating layer 232, and the fourth material layer may be a second spacer material layer that provides a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be the second insulating layer 232 and the second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material, which may be removed selectively to the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may serve as a control gate electrode for a vertical NAND device, for example.

In one embodiment, each second insulating layer 232 may comprise a second insulating material, and each second sacrificial material layer 242 may comprise a second sacrificial material. In this case, the second alternating layer stack (232,242) may include alternating second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by Chemical Vapor Deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that can be used for the second insulating layer 232 can be any material that can be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that can be removed selectively to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

The thickness of the second insulating layer 232 and the second sacrificial material layer 242 may be in the range of 20nm to 50nm, although lesser and greater thicknesses may be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the pair of second insulating layer 232 and second sacrificial material layer 242 may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although more repetitions may also be used. In one embodiment, each second sacrificial material layer 242 in the alternating stack of second layers (232,242) may have a uniform thickness that is substantially constant within each respective second sacrificial material layer 242.

The second stepped surface in the second stepped region may be formed in the stair-step region 200 using the same set of processing steps used to form the first stepped surface in the first stepped region, with appropriate adjustments made to the pattern of the at least one mask layer. A second backward stepped dielectric material portion 265 may be formed over a second stepped surface in the stair region 200.

A second insulating cap layer 270 may then be formed over the second alternating stack of layers (232, 242). The second insulating cap layer 270 comprises a dielectric material different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating cap layer 270 may include silicon oxide. In one embodiment, the first and second sacrificial material layers (142,242) may comprise silicon nitride.

Generally, at least one alternating stack of insulating layers (132,232) and spacer material layers, such as sacrificial material layers (142,242), may be formed over the in-process source-level material layers 10', and at least one retro-stepped dielectric material portion (165,265) may be formed over a stair zone on the at least one alternating stack (132,142,232,242).

Optionally, a drain select level isolation structure 72 may be formed through a subset of layers in an upper portion of the alternating stack of second layers (232, 242). The second layer of sacrificial material 242 cut by the drain select level isolation structures 72 corresponds to the level at which the drain select level conductive layers are subsequently formed. The drain select level isolation structure 72 comprises a dielectric material, such as silicon oxide. The drain select level isolation structures 72 may extend laterally along the first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd 1. The combination of the second layer alternating stack (232,242), the second backward stepped dielectric material portion 265, the second insulating cap layer 270, and the optional drain select level isolation structure 72 collectively constitute a second layer structure (232,242,265,270, 72).

Referring to fig. 7A and 7B, various second-level openings (249,229) may be formed through the second-level structures (232,242,265,270, 72). A photoresist layer (not shown) may be applied over the second insulating cap layer 270 and may be lithographically patterned to form various openings therethrough. The pattern of the openings may be the same as the pattern of the various first layer openings (149,129), which are the same as the sacrificial first layer opening filling portions (148,128). Accordingly, the photoresist layer may be patterned using a photolithographic mask used to pattern the first layer openings (149,129).

The pattern of openings in the photoresist layer may be transferred through the second layer structure (232,242,265,270,72) by a second anisotropic etch process to form various second layer openings (249,229) simultaneously (i.e., during the second anisotropic etch process). The various second layer openings (249,229) may include second layer memory openings 249 and second layer support openings 229.

The second-layer memory openings 249 are formed directly on the top surface of a corresponding one of the sacrificial first-layer memory opening filling portions 148. The second-layer support openings 229 are formed directly on the top surface of a corresponding one of the sacrificial first-layer support opening filling portions 128. In addition, each second layer support opening 229 can be formed through horizontal surfaces within second stepped surfaces, including the interfacial surfaces between the alternating stack (232,242) of second layers and the second rearwardly stepped dielectric material portion 265. The location of the steps S in the first layer alternating stack (132,142) and the second layer alternating stack (232,242) is shown in dashed lines in FIG. 7B.

The second anisotropic etch process may include an etch step in which the material of the second alternating stack of layers (232,242) is etched simultaneously with the material of the second backward-stepped dielectric material portion 265. The chemistry of the etching steps can be alternated to optimize etching of material in the second alternating stack of layers (232,242) while providing an average etch rate comparable to the material of the second backward stepped dielectric material portion 265. The second anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reactive etch process (e.g., CF)₄/O₂/Ar etching). The sidewalls of the various second tier openings (249,229) may be substantially vertical, or may be tapered. The bottom perimeter of each second layer opening (249,229) may be laterally offset, and/or a sacrificial first layer opening fill may be positioned completely underneathWithin the perimeter of the top surface of the portion (148,128). The photoresist layer may then be removed, for example, by ashing.

Referring to fig. 8, the sacrificial first layer fill material of the sacrificial first layer opening fill portion (148,128) may be removed using an etch process that etches the sacrificial first layer fill material selectively to the materials of the first and second insulating layers (132,232), the first and second sacrificial material layers (142,242), the first and second insulating cap layers (170,270), and the interlayer dielectric layer 180. A memory opening 49 (also referred to as an interlayer memory opening 49) is formed in each combination of the second-layer memory opening 249 and the volume from which the sacrificial first-layer memory opening filling portion 148 is removed. A support opening 19 (also referred to as an interlayer support opening 19) is formed in each combination of the second layer support opening 229 and the volume from which the sacrificial first layer support opening filling portion 128 is removed.

Fig. 9A-9D provide sequential cross-sectional views of a memory opening 49 during the formation of a memory opening fill structure. In one implementation, the same structural changes occur in each of the reservoir opening 49 and the support opening 19. In an alternative embodiment, the support openings 19 may be filled with dielectric support pillars without forming semiconductor channel material in the support openings 19.

Referring to fig. 9A, a memory opening 49 in the first exemplary device structure of fig. 8 is shown. The memory opening 49 may extend through the first layer structure and the second layer structure.

Referring to fig. 9B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may comprise a single layer of dielectric material or a stack of multiple layers of dielectric material. In one embodiment, the blocking dielectric layer may comprise a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material that includes at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one non-metallic element, such as nitrogen. In one embodiment, the blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, although lesser and greater thicknesses may also be used. Subsequently, the dielectric metal oxide layer may serve as a dielectric material portion that blocks stored charge from leaking to the control gate electrode. In one embodiment, the barrier dielectric layer 52 comprises aluminum oxide. Alternatively or in addition, the blocking dielectric layer 52 may comprise a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of charge trapping material including a dielectric charge trapping material (which may be silicon nitride, for example). Alternatively, the charge storage layer 54 may comprise a continuous layer or patterned discrete portions of conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a layer of sacrificial material (142,242) within the lateral recesses. In one embodiment, charge storage layer 54 comprises a silicon nitride layer. In one embodiment, the sacrificial material layer (142,242) and the insulating layer (132,232) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layer (142,242) may be recessed laterally relative to the sidewalls of the insulating layer (132,232), and the charge storage layer 54 may be formed as a plurality of vertically spaced apart memory material portions using a combination of a deposition process and an anisotropic etching process. The thickness of charge storage layer 54 may be in the range of 2nm to 20nm, although lesser and greater thicknesses may also be used.

The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling may be performed by hot carrier injection or by fowler-nordheim tunneling induced charge transfer, depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, although lesser and greater thicknesses may also be used. The stack of blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 constitutes a memory film 50 that stores the memory bits.

The semiconductor channel material layer 60L comprises a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have a uniform doping. In one embodiment, semiconductor channel material layer 60L has a p-type doping, wherein the p-type dopant (such as boron atoms) is at 1.0 x 10¹²/cm³To 1.0X 10¹⁸/cm³Such as 1.0 x 10¹⁴/cm³To 1.0X 10¹⁷/cm³Atomic concentrations within the range are present. In one embodiment, the semiconductor channel material layer 60L includes and/or consists essentially of boron doped amorphous silicon or boron doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has an n-type doping, wherein the n-type dopant (such as phosphorus atoms or arsenic atoms) is at 1.0 x 10¹⁵/cm³To 1.0X 10¹⁹/cm³Such as 1.0 x 10¹⁶/cm³To 1.0X 10¹⁸/cm³Atomic concentrations within the range are present. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may beIn the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. A cavity 49' is formed in the volume of each reservoir opening 49 that is not filled with a deposited material layer (52,54,56, 60L).

Referring to fig. 9C, in the event that the cavity 49' in each memory opening is not completely filled by the semiconductor channel material layer 60L, a dielectric core layer may be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method, such as Low Pressure Chemical Vapor Deposition (LPCVD), or by a self-planarizing deposition process, such as spin-on coating. The horizontal portion of the dielectric core layer overlying the second insulating cap layer 270 may be removed, for example, by a recess etch. The recess etch continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

Referring to fig. 9D, a doped semiconductor material may be deposited in the cavity overlying the dielectric core 62. The doped semiconductor material has a doping of the opposite conductivity type of the doping of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has an n-type doping. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and blocking dielectric layer 52 overlying the horizontal plane including the top surface of second insulating cap layer 270 may be removed by a planarization process, such as a Chemical Mechanical Planarization (CMP) process.

Each remaining portion of n-doped semiconductor material constitutes a drain region 63. The dopant concentration in the drain region 63 may be 5.0 × 10¹⁹/cm³To 2.0X 10²¹/cm³But smaller and larger dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60 through which current may flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 collectively comprise a memory film 50 that can store charge with macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and may be subsequently formed after the backside recess is formed. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a persistent memory device, such as a retention time in excess of 24 hours.

Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the memory opening 49 may constitute a memory stack structure 55. Memory stack structure 55 is a combination of a vertical semiconductor channel 60, a tunneling dielectric layer 56, a plurality of memory elements including portions of charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of memory stack structure 55, dielectric core 62, and drain region 63 within memory opening 49 may constitute a memory opening fill structure 58. The in-process source-level material layer 10', the first layer structure (132,142,170,165), the second layer structure (232,242,270,265,72), the interlayer dielectric layer 180, and the memory opening fill structure 58 collectively comprise a memory-level assembly.

Referring to fig. 10A-10D, a first exemplary structure is shown after formation of a memory opening fill structure 58. The support pillar structures 20 are formed in the support openings 19 at the same time as the memory opening filling structures 58 are formed. Each support post structure 20 may have the same set of components as the reservoir opening fill structure 58. The retro-stepped dielectric material portions (165,265) may cover the entire area of the inter-array connection via region 600, the bit line connection region 500, and the peripheral connection region 400, and overlie and contact stepped surfaces within each of the stair regions 200.

Referring to fig. 11A-11D, a first contact level dielectric layer 280 may be formed over the second level structure (232,242,270,265, 72). The first contact level dielectric layer 280 comprises a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the first contact level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100nm to 600nm, although lesser and greater thicknesses may also be used.

A photoresist layer may be applied over first contact level dielectric layer 280 and may be lithographically patterned to form elongated openings extending between clusters of memory opening fill structures 58 along first horizontal direction hd 1. The backside trench 79 may be formed by transferring a pattern in a photoresist layer (not shown) through the first contact level dielectric layer 280, the second layer structure (232,242,270,265,72) and the first layer structure (132,142,170,165) and into the in-process source level material layer 10'. The first contact level dielectric layer 280, the second layer structures (232,242,270,265,72), the first layer structure (132,142,170,165), and portions of the in-process source level material layer 10' underlying the openings in the photoresist layer may be removed to form the backside trench 79. In one embodiment, backside trenches 79 may be formed between clusters of memory stack structures 55. The clusters of memory stack structures 55 may be laterally spaced apart along the second horizontal direction hd2 by backside trenches 79. Although it is desirable for the backside trench 79 to be formed with perfectly straight sidewalls, the backside trench 79 is typically formed with local width variations with non-straight surfaces due to various effects, including: local variations in process parameters (such as local variations in gas flow, pressure, electric field, etc.); and charge density variations within the first exemplary structure due to local layout variations of the conductive features within the first exemplary structure.

Each alternating stack of insulating layers (132,232) and sacrificial material layers (142,242) is divided into alternating stacked sets of insulating layers (132,232) and sacrificial material layers (142,242) in each contiguous combination of the memory array region 100 and stair regions 200. Two adjacent alternating stacked sets of insulating layers (132,232) and sacrificial material layers (142,242) may be laterally spaced from each other along a second horizontal direction hd2 by a respective one of the inter-array connection via regions 600 or a respective one of the bit line termination regions 500.

Referring to fig. 12 and 13A, backside trench spacers 74 may be formed on sidewalls of each backside trench 79. For example, a conformal layer of spacer material may be deposited in the backside trench 79 and over the first contact level dielectric layer 280, and may be anisotropically etched to form the backside trench spacers 74. The backside trench spacers 74 comprise a material different from the material of the source-level sacrificial layer 104. For example, backside trench spacers 74 may comprise silicon nitride.

Referring to fig. 13B, an etchant that etches the material of the source-level sacrificial layer 104 selective to the material of the first-layer alternating stack (132,142), the second-layer alternating stack (232,242), the first and second insulating cap layers (170,270), the first contact-level dielectric layer 280, the upper sacrificial liner 105, and the lower sacrificial liner 103 may be introduced into the backside trenches in an isotropic etching process. For example, if the source-level sacrificial layer 104 comprises undoped amorphous silicon or undoped amorphous silicon germanium alloy, the backside trench spacers 74 comprise silicon nitride, and the upper and lower sacrificial pads (105,103) comprise silicon oxide, a wet etch process using thermal trimethyl-2-hydroxyethylammonium hydroxide ("thermal TMY") or tetramethylammonium hydroxide (TMAH) may be used to remove the source-level sacrificial layer 104 selective to the backside trench spacers 74 and the upper and lower sacrificial pads (105,103). Source cavities 109 are formed in the volume from which source-level sacrificial layer 104 is removed.

The wet etch chemistries, such as thermal TMY and TMAH, are selective to the doped semiconductor material (p-doped semiconductor material and/or n-doped semiconductor material, such as the higher source level semiconductor layer 116 and the lower source level semiconductor layer 112). Thus, the use of selective wet etch chemistries such as thermal TMY and TMAH in the wet etch process that forms the source cavity 109 provides a larger process window that resists etch depth variations during the formation of the backside trench 79. In particular, when forming the source cavities 109 and/or the backside trench spacers 74, incidental etching of the higher source-level semiconductor layer 116 and/or the lower source-level semiconductor layer 112 is minimal even if the sidewalls of the higher source-level semiconductor layer 116 are physically exposed or even if the surface of the lower source-level semiconductor layer 112 is physically exposed, and structural changes to the first exemplary structure caused by accidental physical exposure of the surface of the higher source-level semiconductor layer 116 and/or the lower source-level semiconductor layer 112 during the fabrication steps do not lead to device failure. Each of the memory opening fill structures 58 is physically exposed to the source cavity 109. Specifically, each of the memory opening fill structures 58 includes a sidewall and a bottom surface that are physically exposed to the source cavity 109.

Referring to fig. 13C, a sequence of isotropic etchants (such as wet etchants) may be applied to the physically exposed portions of the memory film 50 to sequentially etch the various component layers of the memory film 50 from the outside to the inside and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper and lower sacrificial liners may be etched incidentally during the removal of the portions of memory film 50 located at the level of source cavity 109 (105,103). The volume of the source cavity 109 may be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower sacrificial pads (105,103). A top surface of lower source-level semiconductor layer 112 and a bottom surface of higher source-level semiconductor layer 116 may be physically exposed to source cavity 109. The source cavities 109 are formed by isotropically etching the source-level sacrificial layer 104 and a bottom portion of each memory film 50 selective to at least one source-level semiconductor layer, such as the lower source-level semiconductor layer 112 and the higher source-level semiconductor layer 116, and the vertical semiconductor channels 60.

Referring to fig. 13D, an n-doped semiconductor material may be deposited on the physically exposed semiconductor surface around the source cavity 109. The physically exposed semiconductor surfaces include bottom portions of outer sidewalls of the vertical semiconductor channels 60 and boron doped horizontal surfaces of the at least one source level semiconductor layer (such as a bottom surface of the higher source level semiconductor layer 116 and/or a top surface of the lower source level semiconductor layer 112). For example, the physically exposed semiconductor surfaces may include a bottom portion of the outer sidewalls of the vertical semiconductor channels 60, a top horizontal surface of the lower source-level semiconductor layer 112, and a bottom surface of the higher source-level semiconductor layer 116.

In one embodiment, an n-doped semiconductor material may be deposited on the physically exposed semiconductor surface around the source cavity 109 by a selective semiconductor deposition process. During a selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and an n-type dopant precursor gas may be simultaneously flowed into a process chamber including the first exemplary structure. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and an n-type dopant precursor gas such as phosphine, arsine, or stibine. In this case, the selective semiconductor deposition process grows n-doped semiconductor material from the physically exposed semiconductor surface around the source cavity 109. The deposited n-doped semiconductor material forms a source contact layer 114 that may contact the sidewalls of the vertical semiconductor channel 60. The atomic concentration of the n-type dopant in the deposited semiconductor material may be 1.0 x 10²⁰/cm³To 2.0X 10²¹/cm³Within a range of, such as 2.0 x 10²⁰/cm³To 8.0X 10²⁰/cm³. The initially formed source contact layer 114 may consist essentially of semiconductor atoms and n-type dopant atoms. Alternatively, the source contact layer 114 may be formed using at least one non-selective n-doped semiconductor material deposition process. Optionally, one or more etch-back processes may be used in conjunction with a plurality of selective or non-selective deposition processes to provide a seamless and/or void-free source contact layer 114.

The duration of the selective semiconductor deposition process may be selected such that the source cavity 109 is filled with the source contact layer 114 and the source contact layer 114 contacts the bottom end portion of the inner sidewalls of the backside trench spacers 74. In one embodiment, the source contact layer 114 may be formed by selectively depositing an n-doped semiconductor material from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material may comprise doped polysilicon. Therefore, the source-level sacrificial layer 104 may be replaced with the source contact layer 114.

The layer stack comprising the lower source-level semiconductor layer 112, the source contact layer 114 and the higher source-level semiconductor layer 116 constitutes a buried source layer (112,114, 116). A p-n junction exists between source contact layer 114 and higher source-level semiconductor layer 116. The layer set comprising the buried source layer (112,114,116), the source-level insulating layer 117 and the source-select-level conductive layer 118 constitutes the source-level material layer 10, which replaces the source-level material layer 10' in the process.

Referring to fig. 13E and 14, an isotropic etch process may be used to remove the backside trench spacers 74 selective to the insulating layer (132,232), the first and second insulating cap layers (170,270), the first contact level dielectric layer 280, and the source contact layer 114. For example, if the backside trench spacers 74 comprise silicon nitride, a wet etch process using hot phosphoric acid may be performed to remove the backside trench spacers 74. In one embodiment, the isotropic etch process to remove the backside trench spacers 74 may be combined with a subsequent isotropic etch process that selectively etches the sacrificial material layers (142,242) for the insulating layers (132,232), the first and second insulating cap layers (170,270), the first contact level dielectric layer 280, and the source contact layer 114.

An oxidation process may be performed to convert the physically exposed surface portions of the semiconductor material into dielectric semiconductor oxide portions. For example, surface portions of the source contact layer 114 and the higher source-level semiconductor layer 116 may be converted into a dielectric semiconductor oxide plate 122, and surface portions of the source selection-level conductive layer 118 may be converted into annular dielectric semiconductor oxide spacers 124.

Referring to fig. 15, the sacrificial material layer (142,242) may be removed selectively to the insulating layer (132,232), the first and second insulating cap layers (170,270), the first contact level dielectric layer 280, and the source contact layer 114, the dielectric semiconductor oxide plate 122, and the annular dielectric semiconductor oxide spacers 124. For example, an etchant that selectively etches the material of the sacrificial material layers (142,242) relative to the material of the insulating layers (132,232), the first and second insulating cap layers (170,270), the backward-stepped dielectric material portions (165,265), and the material of the outermost layer of the memory film 50 may be introduced into the backside trenches 79, e.g., using an isotropic etch process. For example, the sacrificial material layer (142,242) may comprise silicon nitride, and the materials of the insulating layer (132,232), the first and second insulating cap layers (170,270), the retro-stepped dielectric material portion (165,265), and the outermost layer of the memory film 50 may comprise silicon oxide materials.

The isotropic etching process may be a wet etching process using a wet etching solution, or may be a gas phase (dry) etching process in which an etchant is introduced into the backside trench 79 in a gas phase. For example, if the sacrificial material layer (142,242) comprises silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etch bath comprising phosphoric acid, which etches silicon nitride selectively to silicon oxide, silicon, and various other materials used in the art.

Backside recesses (143,243) are formed in the volume from which the sacrificial material layers (142,242) are removed. The backside recesses (143,243) include a first backside recess 143 formed in the volume from which the first sacrificial material layer 142 was removed and a second backside recess 243 formed in the volume from which the second sacrificial material layer 242 was removed. Each of the backside recesses (143,243) may be a laterally extending cavity having a lateral dimension greater than a vertical extent of the cavity. In other words, a lateral dimension of each of the backside recesses (143,243) may be greater than a height of the respective backside recess (143,243). A plurality of backside recesses (143,243) may be formed in a volume of material from which the layer of sacrificial material (142,242) is removed. Each of the backside recesses (143,243) may extend substantially parallel to the top surface of the substrate semiconductor layer 9. The backside recess (143,243) may be vertically bounded by a top surface of the underlying insulating layer (132,232) and a bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143,243) may have a uniform height throughout.

Referring to fig. 16, a backside blocking dielectric layer (not shown) may optionally be deposited in the backside recesses (143,243) and backside trenches 79 and over the first contact level dielectric layer 280. The backside blocking dielectric layer comprises a dielectric material, such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the backside blocking dielectric layer may comprise aluminum oxide. The backside blocking dielectric layer may be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the backside blocking dielectric layer may be in the range of 1nm to 20nm, such as 2nm to 10nm, although lesser and greater thicknesses may also be used.

At least one conductive material may be deposited in the plurality of backside recesses (243), on the sidewalls of the backside trenches 79, and over the first contact level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may comprise an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductively doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

In one embodiment, the at least one conductive material may comprise at least one metallic material, i.e. a conductive material comprising at least one metallic element. Non-limiting exemplary metal materials that may be deposited in the backside recesses (143,243) include tungsten, tungsten nitride, titanium nitride, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or combinations thereof, and a conductive fill material such as W, Co, Ru, Mo, Cu, or combinations thereof. In one embodiment, the at least one conductive material used to fill the backside recesses (143,243) may be a combination of a titanium nitride layer and a tungsten fill material.

A conductive layer (146,246) may be formed by depositing at least one conductive material in the backside recesses (143,243). A plurality of first conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous layer of metallic material (not shown) may be formed on the sidewalls of each backside trench 79 and over the first contact level dielectric layer 280. Each of the first and second

conductive layers

146 and 246 may include a respective conductive metal nitride liner and a respective conductive fill material. Thus, the first and second sacrificial material layers (142,242) may be replaced with first and second conductive layers (146,246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of a backside barrier dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of a backside barrier dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with a continuous layer of metallic material.

The remaining conductive material may be removed from within backside trench 79. In particular, the deposited metallic material of the continuous metallic material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metallic material in the first backside recesses constitutes a first conductive layer 146. Each remaining portion of the deposited metallic material in the second backside recesses constitutes a second conductive layer 246. Sidewalls of the first conductive material layer 146 and the second conductive layer may be physically exposed to the respective backside trenches 79. The backside trench may have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a non-linear width variation along the vertical direction.

Each conductive layer (146,246) may be a conductive sheet including openings therein. A first subset of openings through each conductive layer (146,246) may be filled with memory opening fill structures 58. A second subset of the openings through each conductive layer (146,246) may be filled with support post structures 20. Due to the first stepped surface and the second stepped surface, each conductive layer (146,246) may have a smaller area than any underlying conductive layer (146,246). Due to the first stepped surface and the second stepped surface, each conductive layer (146,246) may have a larger area than any overlying conductive layer (146,246).

In some implementations, a drain select level isolation structure 72 may be disposed at a topmost level of the second conductive layer 246. A subset of the second conductive layers 246 positioned at levels of the drain select level isolation structures 72 constitute drain select gate electrodes. A subset of the conductive layer (146,246) positioned below the drain select gate electrode may serve as a combination of control gates and word lines positioned at the same level. The control gate electrode within each conductive layer (146,246) is a control gate electrode for a vertical memory device that includes memory stack structure 55.

Each of memory stack structures 55 includes a vertical stack of memory elements positioned at each level of a conductive layer (146,246). A subset of the conductive layers (146,246) may include word lines for memory elements. The semiconductor devices in the underlying supported device region 700 may include word line switching devices configured to control a bias voltage to a corresponding word line. Memory level components are positioned above a substrate semiconductor layer 9. The memory hierarchy assembly includes at least one alternating stack (132,146,232,246) and a memory stack structure 55 extending vertically through the at least one alternating stack (132,146,232,246).

An alternating stack of insulating layers (132,232) and conductive layers (146,246) is formed between each adjacent pair of backside trenches 79. Two alternating stacked sets of insulating layers (132,232) and conductive layers (146,246) { (132,146), (232,246) } may be formed over substrate 8, and a cluster of memory stack structures 55 may extend vertically through a respective one of the alternating stacks { (132,146), (232,246) }. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. Adjacent pairs of two alternate stacked sets { (132,146), (232,246) } are laterally spaced from each other by respective backside trenches 79 extending laterally along the first horizontal direction hd 1.

Referring to fig. 17A-17E, a dielectric wall structure 76 may be formed within each backside trench 79, for example, by depositing a dielectric material such as silicon oxide in the backside trench 79. Excess portions of the dielectric material may be removed from above a horizontal plane including the top surface of the first contact level dielectric layer 280. Each remaining portion of the dielectric material in the respective backside trench 79 constitutes a dielectric wall structure 76. Each dielectric wall structure 76 may have a uniform width that does not vary with translation along the first horizontal direction hd 1.

Referring to fig. 18A-18D, through memory level via cavities may be formed through the first contact level dielectric layer 280, the second and first backward stepped dielectric material portions (265,165), and the second layer of dielectric material 768 to top surfaces of the first subset of lower-level metal interconnect structures 780 in the periphery connection region 400, the inter-array connection via regions 600, and the bit line termination regions 500. The through memory level via cavities extend to a top surface of a respective one of the lower level metal interconnect structures 780. At least one conductive material may be deposited in the through memory level via cavity. Excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the first contact level dielectric layer 280. Each remaining portion of the at least one conductive material in the through memory level via cavity constitutes a through memory level via structure (488,588). The through memory level via structure (488,588) includes: a peripheral connection via structure 488 formed in the peripheral connection region 400; an inter-array connection via structure 588 formed in the inter-array connection via region 600; and a bit line connection via structure (not explicitly shown) formed in the bit line connection region 500. The general location of the through memory level via structure (488,588) is shown in FIG. 18C. However, the relative size of the through memory level via structures (488,588) has increased to show their general location, and these structures are not drawn to scale.

The through memory level via structure (488,588) provides an electrical connection that extends vertically through all layers at the memory level, i.e., the set of all layers between the horizontal plane that includes the optional conductive plate layer 6 (or the source level material layer 10 if the optional conductive plate layer 6 is not present) and the second insulating cap layer 270. A through memory level via structure (488,588) extends vertically from beneath a second layer 768 of dielectric material located beneath a source-level material layer 10 to a top surface of a first contact-level dielectric layer 280 overlying a memory stack structure 55. Each inter-array connecting via structure 588 extends through a dielectric region located between two adjacent alternating stacked sets { (132,146), (232,246) } that are laterally spaced apart along the second horizontal direction hd 2. Accordingly, etching of dedicated openings through the inter-array connection via structure 588 of alternating stacked layers may be avoided to simplify the manufacturing process.

Referring to fig. 19A-19C, a second contact level dielectric layer 282 may be formed over the first contact level dielectric layer 280. The second contact level dielectric layer 282 comprises a dielectric material, such as silicon oxide. The thickness of the second contact level dielectric layer 282 may be in the range of 200nm to 1,000nm, although lesser and greater thicknesses may also be used.

A contact level photoresist layer (not shown) may be applied over the second contact level dielectric layer 282 and lithographically patterned to form an opening where a contact via structure is to be subsequently formed. The pattern in the contact level photoresist layer is transferred through the second contact level dielectric layer 282, the first contact level dielectric layer 280, the second retro-stepped dielectric material portion 265, the interlayer dielectric layer 180, and the first retro-stepped dielectric material portion 165 to form a contact via cavity. The contact via cavity may include: a word line contact via cavity 81 extending to a respective one of the first and second conductive layers (146,246); a drain contact via cavity 87 extending to a respective one of the first and second conductive layers (146,246); peripheral contact via cavities 489 extending to respective ones of the peripheral connection via structures 488; and inter-array region contact via cavities 589 that extend to respective ones of inter-array connection via structures 588. The contact level photoresist layer may then be removed, for example, by ashing.

Referring to fig. 20A-20D, a first line level photoresist layer may be applied over the second contact level dielectric layer 282 and may be lithographically patterned to form a line pattern. The line patterns include a first subset of line patterns overlying a respective one of the contact via cavities (81,87,489,589) and a second subset of line patterns not overlying any of the contact via cavities (81,87,489,589) formed between two alternating stacked sets { (132,146), (232,246) } across a respective inter-array connecting via region 600 between pairs of adjacent stair regions 200.

The line pattern is transferred into the upper region of the second contact level dielectric layer 282 by an anisotropic etch process. A first line level trench is formed below the opening in the first line level photoresist layer. A first subset of the first line level trenches may be adjoined to underlying contact via trenches to provide integrated line and via cavities (85,591,491). For example, an integrated line and via cavity (85,591,491) may include: an integrated word line connection cavity 85 comprising a word line via cavity 81 and a respective one of the first line level cavities above; an inter-integrated-array cavity 591 comprising an inter-array region contact via cavity 589 and a respective one of the first line level cavities above; and an integrated peripheral cavity 491 comprising a peripheral contact via cavity 489 and a respective one of the first line-level cavities above.

According to one embodiment of the present disclosure shown in fig. 20C and 20D, the first line-level trench includes an interconnect line trench 183 that is a second subset of the line pattern that does not overlie any of the contact via cavities (81,87,489,589) formed between two alternating stacked sets { (132,146), (232,246) } across the respective inter-array connection via regions 600 between adjacent stair zone 200 pairs. In one embodiment, interconnect trenches 183 may be formed around the integrated inter-array cavity 591 such that each interconnect trench 183 provides a circuitous path between a point overlying a first stair zone around a first alternating layer set { (132,146), (232,246) } to another point overlying a second stair zone 200 around a second alternating layer set { (132,146), (232,246) }. The bottom surface of the interconnect line trench 183 may be between the top surface of the second contact level dielectric layer 282 and the bottom surface of the second contact level dielectric layer 282. The layout of the interconnect trench 183 may be configured such that the interconnect trench 183 is formed entirely between adjacent pairs of the memory array regions 100. In one embodiment, the interconnect line trench 183 does not overlie an area of the memory stack structure 55 to avoid overlapping the drain contact via cavity 87.

Referring to fig. 21A-21D, at least one conductive material is deposited within the drain contact via cavity 87, the integrated word line connection cavity 85, the integrated inter-array cavity 591, and the integrated peripheral cavity 491. Excess portions of the at least one conductive material overlying the top surface of the second contact level dielectric layer 282 may be removed, for example, by a planarization process. Each remaining portion of the at least one conductive material in the drain contact via cavity 87 constitutes a drain contact via structure 88. Each drain contact via structure 88 may be formed on a top surface of a respective one of the drain regions 63. The remaining portion of the at least one conductive material in the integrated word line connection cavity 85 includes the word line contact via structure 86 and the first word line interconnect metal line 186. The remaining portion of the at least one conductive material in the integrated inter-array cavity 591 includes the inter-array region contact via structure 596 and the first inter-array region metal pad 598. The remaining portion of the at least one conductive material in the integrated peripheral cavity 491 comprises a peripheral region contact via structure 496 and a first peripheral region metal pad 498. With the integrated word line connection cavity 85 connected to the integrated peripheral cavity 491, the word line interconnect metal lines 186 may be connected to the first peripheral region metal pads 498. The first inter-array region metal pad 598 and the first peripheral region metal pad 498 are interconnect metal pads and are collectively referred to herein as first interconnect metal pads (598,498).

According to one embodiment of the present disclosure shown in fig. 20C and 20D, the respective remaining portions of the at least one conductive material in the interconnect line trench 183 constitute interconnect line segments 184. Interconnect line segment 184 may be formed over a portion of the retro-stepped dielectric material portions (165,265) that extend along the first horizontal direction hd1 in the inter-array connection via region 600 between the two memory regions 100. The set of interconnect line segments 184 may laterally surround an area of the at least one first inter-array region metal pad 598. Each group of interconnect line segments 184 may include a subset of first interconnect line segments 184 located on one side of the at least one first inter-array region metal pad 598 and a subset of second interconnect line segments 184 located on the other side of the at least one first inter-array region metal pad 598. The bottom surface of the interconnect line segment 184 may be located between the top surface of the second contact level dielectric layer 282 and the bottom surface of the second contact level dielectric layer 282. For clarity and due to the relative proportions of the elements, the interconnect line segments 184, the first word line interconnect metal lines 186, and the first inter-array region metal pads (498,598) are not shown in fig. 21B.

As shown in fig. 21D, each interconnect line segment 184 may include: a linear portion 184L extending along a second horizontal direction (e.g., bit line direction) hd2 and laterally offset from a most proximal one of the first inter-array region metal pads 598; and a pair of lateral projecting portions 184J extending along the first horizontal direction (e.g., word line direction) hd1 and adjoining end regions of the linear portions 184L. In one embodiment, the interconnect line segments 184 may be located in areas of the area surrounding the respective subsets of the first inter-array region metal pads 598.

Referring to fig. 22A-22E, a first interconnect level dielectric layer 290 may be formed over the second contact level dielectric layer 282. Various integrated line and via cavities can be formed by a combination of two photolithographic patterning processes and two anisotropic etching processes. For example, a via cavity may be formed by applying and patterning a first via level photoresist layer and an anisotropic etch that forms a first via cavity in the first interconnect level dielectric layer 290. The line cavities may be formed by applying and patterning a second line level photoresist layer and anisotropic etching that forms second line cavities that overlap upper portions of respective ones of the first via cavities. The formation of the line cavity may be performed after or before the formation of the via cavity. Each combination of the at least one first via cavity and the line cavity constitutes an integrated line and via cavity.

A dual damascene process may be used to form integrated line and via structures including respective sets of metal lines and at least one via structure. At least one conductive material may be deposited in the integrated line and via cavities. Excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the first interconnect-level dielectric layer 290. Each remaining portion of the at least one conductive material in the integrated line and via cavity constitutes an integrated line and via structure comprising a combination of the second line level structure and the at least one first via level structure.

Alternatively, via level dielectric layers and line level dielectric layers may be formed instead of the first interconnect level dielectric layer 290. In this case, a via structure may be formed in the via-level dielectric layer using a first single damascene process, and a metal line may be formed in the line-level dielectric layer in a second single damascene process.

In general, the via structures in the first interconnect-level dielectric layer 290 may be provided as separate via structures or as a lower portion of an integrated line and via structure. The via structures in the first interconnect-level dielectric layer 290 may be performed simultaneously by depositing the same set of at least one conductive material. The via structures in the first interconnect-level dielectric layer 290 may include a drain connection via structure 308, a first peripheral via structure 404, a first inter-array region via structure 504, and a bit line interconnect via structure 302. The drain connection via structure 308 contacts a top surface of a respective one of the drain contact via structures 88. First peripheral via structure 404 contacts a top surface of a respective one of first peripheral region metal pads 498. The first inter-array region via structures 504 contact a top surface of a respective one of the first inter-array region metal pads 598. A bit line interconnect via structure 302 is formed at an end of each lateral ledge 184J of each interconnect line segment 184.

The metal lines in the first interconnect-level dielectric layer 290 may be provided as separate metal lines or as an upper portion of an integrated line and via structure. The metal lines in the first interconnect-level dielectric layer 290 may be formed in an upper portion of the first interconnect-level dielectric layer 290 after the via structures are formed, or may be formed simultaneously with the formation of the via structures as part of an integrated line and via structure. The metal lines in the first interconnect-level dielectric layer 290 may be simultaneously deposited by depositing the same set of at least one conductive material.

The metal lines in the first interconnect-level dielectric layer 290 may include bit line-level bit line segments 318, second peripheral region metal pads 414, and second inter-array region metal pads 514. For clarity and due to the relative proportions of the elements,

elements

318, 414 and 514 are not shown in fig. 21B.

The first subset of bit line level bit line segments 318 may include a complete set of bit lines, where each bit line level bit line segment 318 in the first subset includes an entire bit line. A first subset of bit line level bit line segments 318 may extend straight across both memory array regions 100 and the intervening inter-array connecting via region 600 along a second horizontal direction (e.g., bit line direction) hd 2. Thus, a first subset of bit line level bit line segments 318 may run straight along a second horizontal hd2 above a first alternating stacked group { (132,146), (232,246) } split by a first back-side trench 79 and located in the first memory array region 100, above a first stair region 200 surrounding the first alternating stacked group { (132,146), (232,246) }, above a section of rearward stepped dielectric material portions (165,265) located in the inter-array connecting via region 600, above a second alternating stacked group { (132,146), (232,246) } split by a second back-side trench 79 and located in the second memory array region 100, and above a second stair region 200 surrounding the second alternating stacked group { (132,146), (232,246) } and abutting the inter-array connecting via region 600.

A second subset of bit line level bit line segments 318 may be formed on a respective subset of bit line interconnect via structures 302 and may extend straight across one memory array region 100 and the adjoining stair region 200 along a second horizontal direction hd 2. The second subset of bit line level bit line segments 318 may or may not extend into the contiguous inter-array connecting via region 600. Thus, the second subset of bit line level bit line segments 318 may extend straight along the second level hd2 above an alternating stacked group { (132,146), (232,246) } that is split by the back side trench 79 and located in the memory array region 100 and above the stair region 200 surrounding the alternating stacked group { (132,146), (232,246) }. Thus, each of the bit line level bit line segments 318 in the second subset comprises a portion of an entire bit line.

The bit line-level bit line segments 318 are electrically connected to the upper ends of respective subsets of the vertical semiconductor channels 60 through the respective drain regions 63 and the

conductive elements

88 and 308. A bit line is provided that includes a bit line level bit line segment 318. The bit lines include a first subset of bit lines 318A (which is referred to herein as first bit lines) and a second subset of bit lines 318B (which is referred to herein as second bit lines), as shown in FIG. 22D. Each first bit line in the first subset of bit lines 318A consists of a single one of the bit line level bit line segments 318. Each first bit line extends over two alternating stacked groups { (132,146), (232,246) } as a continuous line structure having a straight edge running therethrough (i.e., from one end to the other end) and is vertically spaced apart from the substrate by a first interconnect level separation distance sd1 (as shown in fig. 23A and 23B). Each second bit line in the second subset of bit lines 318B includes a respective multi-level structure. Each multi-level structure includes: a bit line level bit line segment 318 spaced apart from the substrate 8 by a first interconnect level separation distance; interconnect line segment 184 spaced apart from the substrate by a distance different than the first interconnect level separation distance; and at least two bit line interconnect via structures 302, as shown in FIG. 22E. The bit line (318,184,302) does not overlie any region of the through memory level via structure (488,588).

Second peripheral region metal pad 414 and second inter-array region metal pad 514 are formed concurrently with the formation of bit line level bit line segments 318 of first subset of bit lines 318A (each bit line in the subset consisting of a respective one of bit line level bit line segments 318) and second subset of bit lines 318B using the same metal material deposition step and the same patterning step. The bit line interconnect via structure 302 connects each lateral overhang 184J of a respective one of the interconnect line segments 184 to a respective one of the bit line level bit line segments 318 of the second subset of bit lines 318B. Interconnect line segments 184 of the multilevel structure (318,302,184) may be located in an area surrounding an area of through memory array via structure 588. In one embodiment, the interconnect via structures 302 may overlie respective dielectric wall structures 76.

Referring to fig. 23A-23C, an additional dielectric layer 310, an additional metal interconnect structure 328, and a bond pad 338 may be formed over the first interconnect-level dielectric layer 290. The additional dielectric layers 310 may include at least one additional interconnect-level dielectric layer, such as a second interconnect-level dielectric layer, a third interconnect-level dielectric layer, and so forth. The additional metal interconnect structures 328 may include various interconnect via structures and/or interconnect metal lines. Bond pad 338 may be formed on the topmost subset of metal interconnect structures 328.

Fig. 23D shows an alternative configuration of the first exemplary structure of the first embodiment. In this embodiment, rather than forming the inter-array connecting via region 600 in the back-stepped dielectric regions (165,265) shown in fig. 23 and located between two stair regions 200, an alternating stack of inter-array connecting via regions 600 is formed through the insulating layers (132,232) and dielectric spacer layers (142, 242). In this alternative method, rather than forming the stair well region 200 as shown in fig. 3, a portion of the first and second layers of dielectric spacer material (142,242) are not replaced with respective conductive layers (146,246) in the inter-array connection via region 600. First and second layers of dielectric spacer material (142,242), such as silicon nitride layers, remain as dielectric spacer layers in the inter-array connection via regions 600, and alternating stacks of insulating layers (132,232) and dielectric spacer layers (142,242) { (132,142), (232,242) } are formed between the first and second alternating stacks of insulating layers and conductive layers { (132,146), (232,246) }. A through memory array via structure 588 extends through the alternating stack of insulating layers (132,232) and dielectric spacer layers (142,242) in the inter-array connection via region 600 { (132,142), (232,242) }. Additional layers are then formed over the first contact level dielectric layer 280 as shown in fig. 23A and 23B.

In another alternative configuration of the first exemplary structure of the first embodiment shown in fig. 23D, rather than forming the dielectric wall structure 76 in each of the backside trenches 79, a dielectric spacer 74 and a source contact via 77 (e.g., a source electrode or a local interconnect) are formed in each of the backside trenches 79. Source regions 61 may be formed by implanting ions into semiconductor material layer 10 through backside trenches 79, and then forming source contact vias 77 in electrical contact with source regions 76. In this embodiment, an optional epitaxial semiconductor pedestal 11 may be formed on the layer of semiconductor material 10 in contact with the bottom portion of the vertical semiconductor channel 60. The pedestal 11 forms a channel of a source select transistor located under the word line.

Referring collectively to fig. 1A through 23D and according to a first embodiment of the present disclosure, there is provided a three-dimensional memory device including: first and second alternating stacks of insulating layers (132,232) and conductive layers (146,246), the alternating stacks being located above the substrate 8 and spaced apart from each other; a cluster of memory stack structures 55 extending vertically through the first and second alternating stacks { (132,146), (232,246) }, wherein each memory stack structure 55 comprises a memory film 50 and a vertical semiconductor channel 60; and a bit line (318,302,184) electrically connected to the upper ends of the respective subsets of vertical semiconductor channels 60. Each bit line 318 in the first subset of bit lines 318A extends as a continuous line structure (including a single bit line level bit line segment 318) over the first and second alternating stacks and is vertically spaced apart from the substrate 8 by a first interconnect level separation distance sd. Each bit line (318,302,184) in the second subset of bit lines 318B includes a respective multi-level structure (318,302,184), each multi-level structure (318,302,184) including a bit line level bit line segment 318 spaced apart from the substrate 8 by a first interconnect level separation distance sd1 and an interconnect line segment 184 spaced apart from the substrate 8 by a separation distance sd2 that is different from (e.g., less than) the first interconnect level separation distance sd 1. Each set of memory stack structures 55 can extend vertically through a respective one of the alternating stacks { (132,146), (232,246) }.

In one embodiment shown in FIG. 23D, the first and second alternating stacks { (132,146), (232,246) } are laterally spaced apart from each other by the alternating stacks of insulating layers and dielectric spacer layers { (132,142), (232,242) } in the second horizontal direction (e.g., bit line direction) hd 2.

In another embodiment shown in fig. 23B, the first and second alternating stacks { (132,146), (232,246) } are laterally spaced from each other in the second horizontal direction (e.g., bit line direction) hd2 by backward stepped dielectric material portions (165,265) that extend laterally along the first horizontal direction (e.g., word line direction) hd1 over the stepped surfaces of the first and second alternating stacks. In one embodiment, the bit line level bit line segment 318 of each multilevel structure (318,302,184) extends laterally along a second horizontal direction hd1 that is perpendicular to the first horizontal direction hd 1; and the interconnect line segment 184 of each multilevel structure includes at least one portion (such as a lateral projection 184J) extending laterally along a different horizontal direction than the second horizontal direction hd 2.

In one embodiment, the bit line level bit line segments of each multi-level structure include: a first bit line layer level bit line segment 318 overlying the first alternating stack { (132,146), (232,246) }; and a second bit line layer bit line segment 318 overlying the second alternating stack { (132,146), (232,246) }, wherein longitudinal sidewalls of the first bit line layer bit line segment and longitudinal sidewalls of the second bit line layer bit line segment lie within a pair of two-dimensional euclidean planes (i.e., two vertical planes perpendicular to the first horizontal direction hd 1).

In one embodiment, the interconnect line segment 184 of each multi-level structure (318,302,184) includes: a linear portion 184L extending along the second horizontal direction hd2 and laterally offset from the bit line level bit line segment 318 of the corresponding multilevel structure (318,302,184); and a pair of lateral projections 184J extending along the first horizontal direction hd1 and abutting end regions of the linear portions.

In one embodiment, the pair of lateral projections 184J are connected to the first bit line level bit line segment 318 and the second bit line level bit line segment 318 by a pair of bit line interconnect via structures 302 that contact a respective one of the first bit line level bit line segment 318 and the second bit line level bit line segment 318. In one embodiment, a three-dimensional memory device includes: a drain region 63 contacting an upper end of a corresponding one of the vertical semiconductor channels 60; a drain contact via structure 88 contacting a top surface of a respective one of the drain regions 63; and a drain connection via structure 308 contacting a top surface of a respective one of the drain contact via structures 88 and vertically spaced apart from the substrate 8 by the same vertical separation distance as the bit line interconnect via structure 302 is spaced apart from the substrate 8. In one embodiment, the top surface of the drain contact via structure 88 lies in the same horizontal plane as the top surface of the interconnect line segment 184.

In one embodiment, the interconnect line segment 184 underlies the first subset of bit lines 318A and has an area overlap with the first subset of bit lines 318A along a direction perpendicular to the top surface of the substrate 8 in plan view (such as the view of fig. 22E). In one embodiment, the interconnect line segment 184 of each multi-level structure (318,302,184) is closer to the substrate 8 than the bit line level bit line segment 318 of each multi-level structure (318,302,184) is to the substrate 8.

In one implementation, a three-dimensional memory device includes a through memory level via structure (such as through memory array via structure 588) comprised of at least one metal material and extending vertically through a retro-stepped dielectric material portion (165, 265). The bit lines do not overlie the area of the through memory level via structure, and the interconnect line segments 184 of the multilevel structure (318,302,184) are located in an area surrounding the area of the through memory level via structure.

In one embodiment, a three-dimensional memory device may include an interconnect metal pad (such as second interconnect metal pad 514) located within a region of and electrically connected to a through memory level via structure and vertically spaced apart from substrate 8 by a first interconnect level separation distance sd 1. In one embodiment, a three-dimensional memory device may include: a field effect transistor located above the top surface of the substrate 8 under the alternating stack; and a lower-level metal interconnect structure 780 embedded in the lower-level dielectric material layer 760 and located between the field effect transistor and the retro-stepped dielectric material portion (165,265), wherein the through memory-level via structure contacts one of the lower-level metal interconnect structures 780.

In one embodiment, the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device, the conductive layer (146,246) comprises or is electrically connected to a respective word line of the monolithic three-dimensional NAND memory device, the substrate 8 comprises a silicon substrate, the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings above the silicon substrate, and at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is positioned above another memory cell in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate may comprise an integrated circuit including driver circuitry for memory devices located thereon, the conductive layer (146,246) comprising a plurality of control gate electrodes having a stripe shape extending substantially parallel to the top surface of the substrate 8, the plurality of control gate electrodes comprising at least a first control gate electrode positioned in a first device level and a second control gate electrode positioned in a second device level. The monolithic three dimensional NAND string array includes a plurality of semiconductor channels 60, wherein at least one end of each of the plurality of semiconductor channels 60 extends substantially perpendicular to the top surface of the substrate 8, and one of the plurality of semiconductor channels including a vertical semiconductor channel 60. The monolithic three dimensional NAND string array includes a plurality of charge storage elements (including portions of the memory film 50), each charge storage element being positioned adjacent a respective one of the plurality of semiconductor channels 60.

In various implementations, the multi-level structure (318,302,184) of the second subset of bit lines may be used to provide a region for providing electrical connections to the through memory array via structures 588 without reducing the bit line density. The bit lines may be formed in the entire area of each memory array region 100 without a gap. A subset of bit lines extending toward the through memory array via structures 588 may be routed over the through memory array via structures 588 using a multi-level structure (318,302,184), enabling high density bit line routing.

Referring to fig. 24A and 24B, a second example structure according to a second embodiment of the present disclosure may be derived from the first example structure of the first embodiment by modifying the shape of each stair section 200. In other words, the layout of the first example structure of fig. 1A to 1D may be modified without modifying the structure of each component of the first example structure of fig. 1A to 1D. Thus, peripheral circuitry 712 including semiconductor devices (such as field effect transistors 710) is formed on substrate 8, and lower-level metal interconnect structures 780 embedded in lower-level dielectric material layer 760 are formed over the field effect transistors. Optionally, the conductive plate layer 6 and the in-process source-level material layer 10 'may be patterned in different shapes such that the outer edges of the conductive plate layer 6 and the in-process source-level material layer 10' coincide with the outer edges of each stair-step region 200 that laterally surrounds the respective memory array region 100.

Specifically, the area of stair section 200 may be modified to include a pair of indented lateral boundaries including a set of indented regions around a corresponding peripheral connection region 400 that includes row decoder circuit connections (e.g., wordline connection regions). In one embodiment, the stair zone 200 may include a pair of straight edges extending laterally along the first horizontal direction hd1 and a pair of periodic indented edges extending generally along the second horizontal direction hd2 perpendicular to the first horizontal direction hd 1. Each periodically indented edge of stair section 200 comprises a laterally alternating sequence of laterally protruding stair steps 200P separated along a second horizontal direction (e.g., bitline direction hd2) by respective peripheral attachment regions 400. The laterally protruding stair sections 200P may be discrete or may be connected to each other by an optional laterally recessed section 200R. The laterally projecting stair sections 200P can have a width w. Each of the laterally protruding stair sections and each of the laterally recessed sections may extend along the second horizontal direction hd 2. Stair-step region 200 may be formed by an iteration of an anisotropic etch step and a mask trim step that isotropically trims the trimmable mask layer. Peripheral attachment zones 400 may be formed between pairs of adjacent laterally projecting stair sections 200P.

Referring to fig. 25A to 25C, the process steps of the first embodiment may be performed to the process steps of fig. 10A to 10D. The memory stack structure 55 may be formed in the same manner as in the first embodiment. Each of the memory stack structures 55 includes a vertical semiconductor channel 60 and a memory film 50. Drain regions 63 may be formed on respective ones of the vertical semiconductor channels 60 to form the memory opening fill structures 58. In the stair section 200 facing the

sections

500 and 600 described above, the steps S may be stepped down in only one direction. In contrast, in the laterally protruding stair section 200P of the stair zone 200, the steps S can be stepped down in two different directions (i.e., in a first horizontal direction (e.g., a word line direction) hd1 and in a vertical second horizontal direction (e.g., a bit line direction) hd2) into a recessed region (e.g., a peripheral connection region) 400, as shown in fig. 25B. This is more clearly shown in the perspective view of fig. 31B, which will be described in more detail below.

Referring to fig. 26A-26B, the processing steps of fig. 11A and 11D may be performed to form backside trenches 79. Backside trenches 79 divide each alternating stack of insulating layers (132,232) and sacrificial material layers (142,242) { (132,142), (232,242) } into a plurality of alternating stacks. Alternating stacks of insulating layers (132,232) and sacrificial material layers (142,242) groups (G1-G6) of (132,142), (232,242) } and clusters of memory stack structures 55 may be formed over the lower-level dielectric material layer 760 and the in-process source-level material layer 10'. While a configuration comprising six sets (G1-G6) of alternately stacked { (132,142), (232,242) } is shown to describe one embodiment of the present disclosure, other embodiments are expressly contemplated herein in which any number of sets of alternately stacked { (132,142), (232,242) } are employed. The total number of groups (G1-G6) of alternating stacks { (132,142), (232,242) } in memory array region 100 may be in the range of 2 to 256, such as 4 to 64. Each alternate stack between two adjacent backside trenches 79 that includes a memory stack structure 55 may include a memory block. Each memory array region 100 may include a portion of a memory page or an entire memory page.

Each of the backside trenches 79 may extend laterally along a first horizontal direction (e.g., word line direction) hd 1. In one embodiment, each separate alternating stack of insulating layers (132,232) and sacrificial material layers (142,242) { (132,142), (232,242) } can have a rectangular strip shape extending laterally along the first horizontal direction hd 1. In one implementation, each cluster of memory stack structures 55 may extend vertically through a respective alternate stack { (132,142), (232,242) } of the alternate stacked groups (G1-G6).

In one embodiment, each group (G1-G6) of alternating stacks { (132,142), (232,242) } comprises a respective group of at least four alternating stacks { (132,142), (232,242) }, such as, for example, eight alternating stacks. Alternating stacks { (132,142), (232,242) } within the same group (G1-G6) of alternating stacks { (132,142), (232,242) } may be laterally spaced from each other by a line trench (such as a backside trench 79) that extends vertically through each level of the alternating stacks { (132,142), (232,242) } and laterally along the first horizontal direction hd1 with a respective pair of straight sidewalls that extend from one end of the respective line trench to the other end of the respective line trench. Each line trench (i.e., each back side trench 79) may extend from one outer edge of stair region 200 (e.g., the outer edge of segment 200P) to another outer edge of memory array region 100 on the opposite side.

In one embodiment, the groups (G1-G6) of alternately stacked { (132,142), (232,242) } include odd groups (G1, G3, G5) that alternate with even groups (G2, G4, G6), as numbered from one end to the other along the second horizontal direction hd 2. The alternate stacking of groups (G1-G6) { (132,142), (232,242) } begins with the group labeled first group G1. The alternately stacked groups (G1-G6) have lateral indents along the first horizontal direction hd1 to provide lateral indented regions (e.g., peripheral attachment regions) 400. The adjacent laterally projecting stair sections 200P of each alternate stacked set of stair sections include a step S in the layer of sacrificial material (142,242) that steps down in two directions, including extending into the peripheral attachment area 400 in the second horizontal direction hd 2. The remaining space in the peripheral connection region 400 is filled with portions (165,265) of dielectric material. Each alternate stack { (132,142), (232,242) } within the group (G1-G6) of alternate stacks { (132,142), (232,242) } is formed with a stepped surface S.

The alternately stacked odd arrays (G1, G3, G5) each include: a first laterally protruding stair section 200PA on a first end (e.g., on the right side of fig. 26B); and a first indented area (e.g., a peripheral connection area) 400A on a second end opposite the first end along the first horizontal direction hd1 (e.g., on the left side of fig. 26B). The alternately stacked even groups (G2, G4, G6) each include: a second laterally projecting stair section 200PB located on a second end (e.g., on the left side of fig. 26B) between the two first setback regions 400A; and a second indented area 400B located between the two first laterally protruding stair sections 200PA at a first end opposite the second end along the first horizontal direction hd1 (e.g., on the right side of fig. 26B).

Dielectric material portions, such as backward-stepped dielectric material portions (165,265), overlie the stepped surface S. The dielectric material portion has a lateral extent that increases stepwise according to the vertical distance from the substrate 8 along the first horizontal direction hd1 and along the second horizontal direction hd2 above each stepped surface (i.e., increases stepwise in both the first horizontal direction and the second horizontal direction). In one embodiment, each of the rearwardly-stepped dielectric material portions (165,265) includes a first set of stepped surfaces including vertical surfaces laterally spaced apart along the first horizontal direction hd1 and a second set of stepped surfaces including vertical surfaces laterally spaced apart along the second horizontal direction hd 2. In one embodiment, the first set of stepped surfaces and the second set of stepped surfaces contact sidewalls of an alternating stack present in the same set (G1-G6) of the alternating stack { (132,142), (232,242) }. A peripheral attachment area 400 may be present between two adjacent lateral protruding segments 200P of the stair area 200. It should be noted that fig. 26 is a schematic diagram, and the number of "left" and "right" stacks/blocks is preferably the same. For example, if a block is connected by the left side, the right side may be opened and used as the peripheral connection region 400, and vice versa.

Referring to fig. 27, the subsequent process steps of the first embodiment may be performed to the process steps of fig. 17A to 17E. As in the first embodiment, the in-process source-level material layer 10' is replaced with a source-level material layer 10. Each cluster of memory stack structures 55 extends vertically through a respective alternate stack of (483) (132,146), (232,246) of the set of alternate stacks of { (132,146), (232,246) } (G1-G6) } between a layer of semiconductor material, such as a buried source layer (112,114,116) within the source-level material layer 10, and the set of alternate stacks of { (132,146), (232,246) } of insulating layers (132,232) and conductive layers (146,246).

Referring to fig. 28A-28D, as in the first implementation, through memory level via cavities may be formed through the first contact level dielectric layer 280, the second and first backward stepped dielectric material portions (265,165), and the second layer of dielectric material 768, to the top surfaces of the first subset of lower level metal interconnect structures 780 in the peripheral connection regions 400 and optionally in the inter-array connection via regions and in the bit line termination regions. The through memory level via cavities extend to a top surface of a respective one of the lower level metal interconnect structures 780. At least one conductive material may be deposited in the through memory level via cavity. Excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the first contact level dielectric layer 280. Each remaining portion of the at least one conductive material in the through memory level via cavity constitutes a through memory level via structure. The through memory level via structures include a peripheral connecting via structure 488 formed in a peripheral connection region 400, and optionally an inter-array connecting via structure formed in an inter-array connecting via region, and a bit line connecting via structure formed in a bit line wiring region, as in the first embodiment.

The peripheral connecting via structure 488 provides an electrical connection that extends vertically through all layers at the memory level, i.e., the set of all layers between the horizontal plane that includes the optional conductive plate layer 6 (or the source-level material layer 10 if the optional conductive plate layer 6 is not present) and the second insulating cap layer 270. A peripheral connecting via structure 488 extends vertically from beneath the second layer 768 of dielectric material that is beneath the source-level material layer 10 to the top surface of the first contact-level dielectric layer 280 that overlies the memory stack structure 55.

The peripheral connecting via structures 488 may include a through memory level word line connecting via structure 488A and a through memory level transistor connecting via structure 488B. Each of the through memory level word line connecting via structures 488A and the through memory level transistor connecting via structures 488B may contact a respective one of the lower-level metal interconnect structures 780. In one implementation, a pair of through memory level transistor connecting via structures 488B and through memory level word line connecting via structures 488A may be connected to the same word line control transistor 710T shown in fig. 28A and may pass through the same subset of dielectric material portions (such as the vertical stack of first and second retro-stepped dielectric material portions 165, 265).

Referring to fig. 29A-29C, the processing steps of fig. 19A-19C, 20A-20D, and 21A-21D may be performed to form a second contact level dielectric layer 282, various conductive via structures (88,86,496), and various first line level structures (186,498) over the first contact level dielectric layer 280. The various conductive via structures (88,86,496) may include a drain contact via structure 88, a word line contact via structure 86, a peripheral region contact via structure 496, and additional conductive via structures described in the first embodiment. The first line level structure (186,498) includes word line interconnect metal lines 186, first peripheral region metal pads 498 and additional first line level structures described in the first embodiment.

Each drain contact via structure 88 may be formed on a top surface of a respective one of the drain regions 63. Word line contact via structures 86 may be formed on respective ones of the conductive layers 146,246. Each of the first word line interconnect metal lines 186 may be formed over a respective one of the word line contact via structures 86 and a respective one of the first set of peripheral region contact via structures 496. Each of the peripheral region contact via structures 496 can be formed on a respective one of the peripheral connection via structures 488. Each of first peripheral region metal pads 498 may be formed over a respective one of the second set of peripheral region contact via structures 496. In one embodiment, word line interconnect metal line 186 and first peripheral area metal pad 498 may be formed as a unitary structure employing a dual damascene process. Likewise, first peripheral region metal pad 498 and peripheral region contact via structure 496 may be formed as a unitary structure.

In one implementation, word line interconnect metal lines 186 may be electrically connected to respective ones of the word line contact via structures 86 and respective ones of the through memory level word line connection via structures 488A through respective peripheral region contact via structures 496 and may extend laterally along respective longitudinal directions parallel to the second horizontal direction hd2, as shown in fig. 29B (and shown in fig. 31B as described below). In one implementation, word line interconnect metal lines 186 may extend laterally along second horizontal direction hd2 from above a respective one of the word lines (including conductive layer (146,246)) to which the respective word line interconnect metal line 186 is electrically connected into a region overlying a respective one of the dielectric material portions, such as first and second retro-stepped dielectric material portions (165,265) located within peripheral connection region 400. Each of the through memory level word line connection via structures 488A may be electrically connected to a respective one of the word line interconnect metal lines 186, extend through a respective one of the dielectric material portions, and contact a respective one of the lower level metal interconnect structures 780.

Each of the word line contact via structures 86 and the through memory level word line connection via structures 488A may be formed by the same subset of retro-stepped dielectric material portions, such as a vertical stack of first and second retro-stepped

dielectric material portions

165, 265. The through memory level transistor connection via structures 488A may be electrically connected to respective transistors 710T supporting the word line control transistors 710 in the device region 700.

The through memory level transistor connection via structure 488B may be electrically connected to a word line control transistor 710 (e.g., 710T). The through memory level transistor connection via structures 488B may extend through respective subsets of dielectric material portions (such as a vertical stack of first and second retro-stepped dielectric material portions 165, 265). In one implementation, a pair of through memory level transistor connection via structures 488B and through memory level word line connection via structures 488A connected to the same word line control transistor 710T may pass through the same set of dielectric material portions (such as a vertical stack of first and second retro-stepped dielectric material portions 165, 265).

Referring to fig. 30A-30B, the processing steps of fig. 22A-22E may be performed as in the first embodiment to form a first interconnect-level dielectric layer 290 and to form a via structure and a second line-level structure. The via structures in the first interconnect-level dielectric layer 290 may include a drain connecting via structure 308, a first peripheral via structure 404, and optional additional via structures described in the first embodiment. The drain connection via structure 308 contacts a top surface of a respective one of the drain contact via structures 88. First peripheral via structure 404 contacts a top surface of a respective one of first peripheral region metal pads 498.

The second line level structure formed in the first interconnect-level dielectric layer 290 may include the bit lines 408, the second peripheral region metal pads 414, and the optional additional second line level structure described in the first embodiment. The bit lines 408 are electrically connected to the respective sets of drain contact via structures 88 and extend straight laterally along the second horizontal direction hd 2. Optionally, a portion of the bit line 408 may have the configuration of the first implementation shown in fig. 22A-23B.

In one implementation, the word line interconnect metal lines 186 may extend laterally along the second horizontal direction (e.g., bit line direction) hd2, and thus may be parallel to the bit lines 408. Bit lines 408 are formed at a level above the level of word line interconnect metal lines 186. Thus, word line interconnect metal line 186 may be vertically spaced from substrate 8 by a vertical separation distance that is less than the vertical separation distance by which bit line 408 is spaced from substrate 8.

Referring to fig. 31A and 31B, an additional dielectric layer 310, an additional metal interconnect structure 328, and a bond pad 338 may be formed over the first interconnect level dielectric layer 290. The additional dielectric layers 310 may include at least one additional interconnect-level dielectric layer, such as a second interconnect-level dielectric layer, a third interconnect-level dielectric layer, and so forth. The additional metal interconnect structures 328 may include various interconnect via structures and/or interconnect metal lines. Bond pad 338 may be formed on the topmost subset of metal interconnect structures 328.

Referring to fig. 24A to 31B and according to a second embodiment of the present disclosure, a three-dimensional memory device includes: peripheral circuitry 712 including field effect transistors 710 located over substrate 8; a lower-level metal interconnect structure 780 embedded in a lower-level dielectric material layer 760 overlying field effect transistor 710 and connected to a node of field effect transistor 710; and a group (G1-G6) of alternating stacks of insulating layers (132,232) and conductive layers (146,246) over the lower-level dielectric material layer 760, each alternating stack { (132,246), (232,246) } extending laterally along the first horizontal direction hd 1.

The groups (G1-G6) alternately stacked { (132,246), (232,246) } include odd groups (G1, G3, G5) which alternate with even groups (G2, G4, G6) along the second horizontal direction hd2 perpendicular to the first horizontal direction hd 1.

The alternately stacked odd arrays (G1, G3, G5) each include: a first laterally protruding stair section 200PA on a first end (e.g., on the right side of fig. 26B); and a first indented area (e.g., a peripheral connection area) 400A on a second end opposite the first end along the first horizontal direction hd1 (e.g., on the left side of fig. 26B).

The alternately stacked even groups (G2, G4, G6) each include: a second laterally projecting stair section 200PB located on a second end (e.g., on the left side of fig. 26B) between two of the first indented areas 400A; and a second recessed area 400B located between two of the first laterally protruding stair sections 200PA at a first end opposite the second end along the first horizontal direction hd1 (e.g., on the right side of fig. 26B).

The device further comprises: a dielectric material portion (165,265) located in the first and second indented regions (400A, 400B); a cluster of memory stack structures 55 extending vertically through the alternating stacked groups; a word line contact via structure 86 that contacts a conductive layer (e.g., a word line) (146,246); word line interconnect metal lines 186 electrically connected (e.g., directly contacting or indirectly contacting through one or more intermediate conductors) to respective ones of the word line contact via structures 86 and extending from over respective ones of the word lines (146,246) over respective ones of the dielectric material portions (165,265) along the second horizontal direction hd 2; and a through memory level word line connecting via structure 488A electrically connected to and extending through a respective one of the word line interconnect metal lines (165,265) and electrically connected (e.g., directly or indirectly contacting) a respective one of the lower level metal interconnect structures 780.

In one embodiment, the steps S in the first and second laterally projecting stair sections (200PA,200PB) are stepped down in both the first horizontal direction hd1 and the second horizontal direction hd 2. For example, the steps S in the first lateral projecting stair section 200PA are stepped down in the second horizontal direction hd2 into the second recessed area 400B, while the steps S in the second lateral projecting stair section 200PB are stepped down in the second horizontal direction hd1 into the first recessed area 400A.

In one embodiment, the dielectric material portions (165,265) comprise backward-stepped dielectric material portions having a lateral extent that increases stepwise according to a vertical distance from the substrate 8 along the first horizontal direction and along the second horizontal direction. In one embodiment, each of the rearwardly stepped dielectric material portions includes a first set of stepped surfaces including vertical surfaces laterally spaced apart along a first horizontal direction and a second set of stepped surfaces including vertical surfaces laterally spaced apart along a second horizontal direction. The first and second sets of stepped surfaces contact the steps S of the first and second laterally projecting stair sections (200PA,200 PB).

In one embodiment, alternating stacks present within the same alternating stack group are laterally spaced from each other by a line trench 79 extending vertically through each level of the alternating stacks and laterally along the first horizontal direction hd 1.

In one implementation, the through memory level word line connection via structures 488A are electrically connected to respective word line control transistors 710T of the field effect transistors 710. The through memory level transistor connection via structures 488B are electrically connected to the word line control transistors 710 and extend through respective subsets of the dielectric material portions (165, 265). A pair of through memory level transistor connecting via

structures

488A and 488B electrically connected to the same word line control transistor 710T pass through the same subset of dielectric material portions (165, 265).

The lateral setback of stair section 200 extends around peripheral attachment region 400 at a location laterally offset from laterally protruding stair run 200P of stair section 200 along the bitline direction. A set of word line contact via structures 86, through memory level word line connection via structures 488A, through memory level transistor connection via structures 488B, and word line control transistors 710T located below the word lines (146,246) may be formed adjacent to each other, thereby minimizing signal transmission length and reducing the area of the three-dimensional memory device while utilizing dielectric fill regions 400 that may remain unused in prior art devices. The bond pad 338 connected to the word line control transistor 710T may be formed directly above the through memory level transistor connecting via structure 488B connected to the word line control transistor 710T, thereby minimizing the length of the signal path between the word line control transistor and the bond pad 338.

While specific embodiments have been mentioned above, it should be understood that the disclosure is not so limited. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the word "comprise" or "includes" contemplates all embodiments in which the word "consists essentially of, or the word" consists of, replaces the word "comprises" or "includes. Embodiments using specific structures and/or configurations are shown in the present disclosure, it being understood that the present disclosure may be practiced in any other compatible structures and/or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered to be impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising:

a first alternating stack of insulating layers and conductive layers, the first alternating stack being located over a substrate;

a second alternating stack of insulating layers and conductive layers over the substrate and spaced apart from the first alternating stack;

a cluster of memory stack structures extending vertically through the first alternating stack and the second alternating stack, wherein each memory stack structure comprises a memory film and a vertical semiconductor channel; and

bit lines electrically connected to upper ends of respective subsets of the vertical semiconductor channels,

wherein:

each bit line in the first subset of bit lines extends as a continuous line structure over the first and second alternating stacks and is vertically spaced apart from the substrate by a first interconnect level separation distance; and is

Each bit line in the second subset of bit lines includes a respective multi-level structure, each multi-level structure including a bit line level bit line segment spaced apart from the substrate by the first interconnect level separation distance and an interconnect line segment spaced apart from the substrate by a distance different than the first interconnect level separation distance.

2. The three-dimensional memory device of claim 1, wherein the first and second alternating stacks are laterally spaced from each other in a second horizontal direction by a backward stepped dielectric material portion extending laterally along a first horizontal direction over stepped surfaces of the first and second alternating stacks.

3. The three-dimensional memory device of claim 2, wherein:

the bit line level bit line segments of each multi-level structure extend laterally along the second horizontal direction perpendicular to the first horizontal direction; and is

The interconnect line segment of each multilevel structure includes at least one portion extending laterally along a horizontal direction different from the second horizontal direction.

4. The three-dimensional memory device of claim 3, wherein the bit line level bit line segments of each multi-level structure comprise:

a first bit line layer level bit line segment overlying the first alternating stack; and

a second bit line layer level bit line segment overlying the second alternating stack, wherein longitudinal sidewalls of the first bit line layer level bit line segment and longitudinal sidewalls of the second bit line layer level bit line segment lie within a pair of two-dimensional Euclidean planes.

5. The three-dimensional memory device of claim 4, wherein the interconnect line segments of each multi-level structure comprise:

a linear portion extending along the second horizontal direction and laterally offset from the first and second bit line level bit line segments; and

a pair of lateral projections extending along the first horizontal direction and abutting end regions of the linear portion.

6. The three-dimensional memory device of claim 5, wherein the pair of lateral projections are connected to the first and second bit line level bit line segments by a pair of bit line interconnect via structures that contact a respective one of the first and second bit line level bit line segments.

7. The three-dimensional memory device of claim 6, further comprising:

a drain region contacting an upper end of a respective one of the vertical semiconductor channels;

a drain contact via structure contacting a top surface of a respective one of the drain regions; and

a drain connection via structure contacting a top surface of a respective one of the drain contact via structures and vertically spaced apart from the substrate by a same vertical separation distance as each of the pair of bit line interconnect via structures is spaced apart from the substrate.

8. The three-dimensional memory device of claim 7, wherein a top surface of the drain contact via structure lies in a same horizontal plane as a top surface of the interconnect line segment of each multi-level structure.

9. The three-dimensional memory device of claim 5, wherein the interconnect line segment is located under the first subset of the bit lines and has an area overlap with the first subset of the bit lines in a direction perpendicular to a top surface of the substrate in plan view.

10. The three-dimensional memory device of claim 3, wherein the interconnect line segments of each multi-level structure are closer to the substrate than the bit line level bit line segments of each multi-level structure.

11. The three-dimensional memory device of claim 3, further comprising a through memory level via structure including at least one metal material and extending vertically through the backward-stepped dielectric material portion, wherein:

the bit lines do not overlie regions of the through memory level via structures; and is

The interconnect line segments of the multi-level structure are located in an area surrounding the area of the through memory level via structure.

12. The three-dimensional memory device of claim 11, further comprising an interconnect metal pad located within the region of the through memory level via structure and electrically connected to the through memory level via structure, and vertically spaced apart from the substrate by the first interconnect level separation distance.

13. The three-dimensional memory device of claim 11, further comprising:

a field effect transistor located above a top surface of the substrate below the first and second alternating stacks; and

a lower-level metal interconnect structure embedded in a lower-level layer of dielectric material and located between the field effect transistor and the backward-stepped dielectric material portion, wherein the through memory-level via structure contacts one of the lower-level metal interconnect structures.

14. The three-dimensional memory device of claim 1, wherein the first and second alternating stacks are laterally spaced from each other in a second horizontal direction by the alternating stacks of insulating layers and dielectric spacer layers.

15. A method of forming a three-dimensional memory device, comprising:

forming first and second alternating stacks of insulating and conductive layers over a substrate and a cluster of memory stack structures extending vertically through the first and second alternating stacks, wherein each memory stack structure includes a memory film and a vertical semiconductor channel; and

forming bit lines electrically connected to upper ends of respective subsets of the vertical semiconductor channels,

wherein:

16. The method of claim 15, further comprising forming a backward stepped dielectric material portion between and over stepped surfaces of the first and second alternating stacks, wherein the first subset of the bit lines and the second subset of the bit lines extend over the backward stepped dielectric material portion.

17. The method of claim 15, wherein the interconnect line segments of each multi-level structure comprise:

a linear portion extending along a second horizontal direction and laterally offset from the bit line level bit line segments, an

A pair of lateral projections extending along a first horizontal direction and abutting end regions of the linear portions; and is

The method also includes forming a bit line interconnect via structure connecting each lateral projection to a respective one of the bit line level bit line segments.

18. The method of claim 17, further comprising:

a drain region formed on an upper end of a respective one of the vertical semiconductor channels;

a drain contact via structure formed on a top surface of a respective one of the drain regions; and

a drain connection via structure formed on a top surface of a respective one of the drain contact via structures concurrently with the formation of the bit line interconnect via structures.

19. The method of claim 16, further comprising:

a through memory level via structure comprising at least one metal material formed between two sets of alternating stacks, wherein:

The interconnect line segments of the multi-level structure are located in an area surrounding the area of the through memory level via structure; and is

An interconnect metal pad formed within a region of the through memory level via structure and electrically connected to the through memory level via structure, wherein the interconnect metal pad is formed at the same time as the bit line level bit line segments of the first and second subsets of the bit lines using the same metal material deposition step and the same patterning step.

20. The method of claim 19, wherein the through memory level via structures are formed through the backward stepped dielectric material portions.

21. A three-dimensional memory device, comprising:

a peripheral circuit comprising a field effect transistor located over a substrate;

a lower level metal interconnect structure embedded in a lower level dielectric material layer overlying the field effect transistor and connected to a node of the field effect transistor;

an alternating stack of insulating layers and conductive layers, the alternating stack comprising word lines located above the lower-level dielectric material layer, each alternating stack extending laterally along a first horizontal direction, wherein:

the alternating stacked groups comprise odd groups alternating with even groups along a second horizontal direction perpendicular to the first horizontal direction;

the alternately stacked odd groups each include: a first laterally projecting stair section on a first end; and a first setback region on a second end opposite the first end along the first horizontal direction;

the alternately stacked even groups each include: a second laterally projecting stair section on a second end between two of the first retracted zones; and a second recessed area between two of the first laterally projecting stair sections on a first end opposite the second end along the first horizontal direction;

a dielectric material portion located in the first and second setback regions;

a cluster of memory stack structures extending vertically through the alternating stacked groups;

a word line contact via structure contacting the conductive layer;

word line interconnect metal lines electrically connected to respective ones of the word line contact via structures and extending from over the respective ones of the word lines along the second horizontal direction over respective ones of the dielectric material portions; and

a through memory level word line connecting via structure electrically connected to a respective one of the word line interconnect metal lines and extending through a respective one of the dielectric material portions and electrically connected to a respective one of the lower level metal interconnect structures.

22. The three-dimensional memory device of claim 21, wherein the steps in the first and second laterally protruding stair sections are stepped down in both the first and second horizontal directions.

23. The three-dimensional memory device of claim 22, wherein:

said steps in said first laterally projecting stair section are stepped down in said second horizontal direction into said second recessed area; and is

The steps in the second laterally projecting stair section are stepped down in the second horizontal direction into the first retracted zone.

24. The three-dimensional memory device of claim 23, wherein the dielectric material portion comprises a backward-stepped dielectric material portion having a lateral extent that gradually increases according to a vertical distance from the substrate along the first horizontal direction and along the second horizontal direction.

25. The three-dimensional memory device of claim 24, wherein each of the backward-stepped dielectric material portions comprises:

a first set of stepped surfaces comprising vertical surfaces spaced laterally along the first horizontal direction; and

a second set of stepped surfaces comprising vertical surfaces spaced laterally along the second horizontal direction.

26. The three-dimensional memory device of claim 25, wherein the first and second sets of stepped surfaces contact the steps of the first and second laterally protruding stair sections.

27. The three-dimensional memory device of claim 21, wherein each of the memory stack structures comprises a vertical semiconductor channel and a memory film.

28. The three-dimensional memory device of claim 27, further comprising a drain region contacting a respective one of the vertical semiconductor channels.

29. The three-dimensional memory device of claim 28, further comprising a drain contact via structure contacting a respective one of the drain regions.

30. The three-dimensional memory device of claim 29, further comprising bit lines electrically connected to respective sets of drain contact via structures and extending laterally at least partially along the second horizontal direction.

31. The three-dimensional memory device of claim 30, wherein the word line interconnect metal lines are vertically spaced from the substrate by a vertical separation distance that is less than a vertical separation distance by which the bit lines are spaced from the substrate.

32. The three-dimensional memory device of claim 30, further comprising a layer of semiconductor material located between the lower-level layer of dielectric material and the alternating stack group and extending continuously under each of the alternating stacks.

33. The three-dimensional memory device of claim 32, wherein each bottom end of a vertical semiconductor channel is electrically connected to the layer of semiconductor material.

34. The three-dimensional memory device of claim 30, wherein each bit line in the first subset of bit lines extends entirely along the second horizontal direction as a continuous line structure and is vertically spaced apart from the substrate by a first interconnect level separation distance.

35. The three-dimensional memory device of claim 34, wherein each bit line in the second subset of bit lines comprises a respective multi-level structure, each multi-level structure comprising a bit line level bit line segment spaced apart from the substrate by the first interconnect level separation distance and an interconnect line segment spaced apart from the substrate by a distance different than the first interconnect level separation distance.

36. The three-dimensional memory device of claim 21, wherein the through memory level word line connection via structures are electrically connected to respective word line control transistors of the field effect transistors.

37. The three-dimensional memory device of claim 36, further comprising through memory level transistor connection via structures electrically connected to the word line control transistors and extending through respective subsets of the dielectric material portions.

38. The three-dimensional memory device of claim 37, wherein a pair of through memory level transistor connecting via structures and through memory level word line connecting via structures electrically connected to a same word line control transistor pass through a same subset of dielectric material portions.

39. The three-dimensional memory device of claim 21, wherein each alternate stack group comprises at least four alternate stacks of the respective group.

40. The three-dimensional memory device of claim 39, wherein alternating stacks present within the same set of alternating stacks are laterally spaced from each other by line trenches extending vertically through each level of the alternating stacks and laterally along the first horizontal direction.