CN113225074B - Universal frequency modulator and frequency modulation method and device - Google Patents
Universal frequency modulator and frequency modulation method and device Download PDFInfo
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- CN113225074B CN113225074B CN202110262312.XA CN202110262312A CN113225074B CN 113225074 B CN113225074 B CN 113225074B CN 202110262312 A CN202110262312 A CN 202110262312A CN 113225074 B CN113225074 B CN 113225074B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The embodiment of the disclosure provides a universal frequency modulator, a frequency modulation method and a device. Wherein the universal frequency modulator comprises: a configurable all-digital phase-locked loop, the all-digital phase-locked loop comprising two loops: loop a and loop b; the loop A comprises: binary phase detector, digital loop filter, digital controlled oscillator, dual-mode frequency divider, differential integral modulator, digital time converter and integer frequency divider; the loop B comprises other parts except a numerical control oscillator in the loop A; the output end of the digital loop filter in the loop A is connected with the input end of the numerical control oscillator; the output signals of the numerical control oscillator are respectively input into a dual-mode frequency divider in a loop A and a loop B; the output end of the digital loop filter in the loop B is connected with the input end of the differential integral modulator in the loop A.
Description
Technical Field
The present disclosure relates to, but not limited to, the field of radio frequency integrated circuits, and in particular, to a universal frequency modulator based on a reconfigurable all-digital phase-locked loop, and a frequency modulation method and apparatus.
Background
At present, the phase-locked loop is widely applied to wireless communication or wired communication application due to the characteristics of simple structure, excellent performance and the like, and is used for recovering and spreading clock data in a wired communication system, synthesizing frequencies in the wireless communication application and the like. The digitized phase-locked loop is not affected by the problems of serious matching precision or leakage current and the like the analog phase-locked loop, so that the process transplanting and expansion of the digitized phase-locked loop are easier, and the process compatibility is better. Meanwhile, the realization of digitalization enables low power supply voltage to be possible, high integration level and low power consumption can be realized, and a good foundation is provided for the application of the digital phase-locked loop in the field of radio frequency communication.
With the development of CMOS (Complementary Metal-Oxide-Semiconductor) technology, the all-digital phase-locked loop can provide low-cost stable frequency generation and modulation through digital calibration, and the binary all-digital phase-locked loop with the phase detection function further reduces the complexity of design. But in the case of fractional mode, binary all-digital phase-locked loops often require high resolution digital time converters to avoid significant reduction of in-band noise. Although frequency modulator architectures based on binary all-digital phase locked loops without high resolution digital time converters have been recently proposed for wired and wireless systems, they are mostly difficult to achieve both wideband and narrowband frequency modulation in the same modulator.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The disclosed embodiments provide a generic frequency modulator that proposes a generic frequency modulator architecture based on a reconfigurable all-digital phase-locked loop to perform wideband and narrowband frequency modulation, respectively, in the same modulator. The embodiment of the disclosure also provides a method for outputting a modulation signal according to the requirement based on the frequency modulator.
The disclosed embodiments provide a universal frequency modulator, comprising:
a configurable all-digital phase-locked loop, the all-digital phase-locked loop comprising two loops: loop a and loop b;
the loop A comprises: a first binary phase detector, a first digital loop filter, a digital controlled oscillator, a first dual-mode frequency divider, a first differential integral modulator, a first digital time converter, a first integer frequency divider; the loop B comprises: a second binary phase detector, a second digital loop filter, a second double-mode frequency divider, a second differential integral modulator, a second digital time converter, a second integer frequency divider;
the output end of the first digital loop filter of the loop A is connected with the input end of the numerical control oscillator; the output signals of the numerical control oscillator are respectively input into the first double-mode frequency divider and the second double-mode frequency divider;
The output end of the second digital loop filter of the loop B is connected with the input end of the first differential integral modulator of the loop A.
The embodiment of the disclosure also provides a frequency modulation method, which comprises the following steps:
according to bandwidth modulation requirements, controlling the working states of a loop A and a loop B in the universal frequency modulator to realize different configurations of the topological structure of the all-digital phase-locked loop, and outputting corresponding frequency modulation signals from the numerical control oscillator;
wherein the bandwidth modulation requirement comprises: broadband modulation and narrowband modulation.
The disclosed embodiments also provide an electronic device comprising a memory, a processor, the memory having stored therein a computer program for frequency modulation, the processor being arranged to read and run the computer program for frequency modulation to perform the frequency modulation method as described above.
The embodiment of the disclosure provides the proposed universal frequency modulator without a complex and high-power-consumption background digital calibration module to overcome nonlinearity of key modules in a circuit, and only needs to perform initial calibration and pre-tuning aiming at process deviation and frequency requirements of different channels, thereby greatly simplifying the design of the circuit and reducing the power consumption of the circuit.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.
Drawings
FIG. 1 is a schematic diagram of a general frequency modulator according to an embodiment of the disclosure;
FIG. 2 is a topology of the universal frequency modulator under narrowband signal modulation in an embodiment of the present disclosure;
fig. 3 is a topology of the universal frequency modulator under wideband signal modulation in an embodiment of the present disclosure.
Detailed Description
The present invention will be described in further detail with reference to the drawings and the embodiments, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.
Example 1
Embodiments of the present disclosure provide a universal frequency modulator, comprising,
a configurable all-digital phase-locked loop, the all-digital phase-locked loop comprising two loops: loop a and loop b;
The loop A comprises: a first binary phase detector, a first digital loop filter, a digital controlled oscillator, a first dual-mode frequency divider, a first differential integral modulator, a first digital time converter, a first integer frequency divider; the loop B comprises: a second binary phase detector, a second digital loop filter, a second double-mode frequency divider, a second differential integral modulator, a second digital time converter, a second integer frequency divider;
the output end of the first digital loop filter of the loop A is connected with the input end of the numerical control oscillator; the output signals of the numerical control oscillator are respectively input into the first double-mode frequency divider and the second double-mode frequency divider;
the output end of the second digital loop filter of the loop B is connected with the input end of the first differential integral modulator of the loop A.
In some exemplary embodiments, the first binary phase detector is configured to compare phase information of the reference clock signal and the feedback clock signal from the first integer divider;
the first digital loop filter is used for performing digital domain filtering on the signal output by the first binary phase discriminator to generate a first control signal;
The digital control oscillator is used for generating an output modulation signal according to a first control signal output by the first digital loop filter;
the first dual-mode frequency divider is used for generating two frequency dividing modes according to a second control signal from the first differential integral modulator so as to realize fractional frequency division;
the first differential integral modulator is used for generating a second control signal to control the first dual-mode frequency divider to realize fractional frequency division;
the first digital time converter is used for delaying the clock signal output by the first dual-mode frequency divider;
the first integer frequency divider is used for integer frequency division of the clock signal output by the first digital time converter;
the second binary phase detector is used for comparing the phase information of the reference clock signal and the feedback clock signal from the second integer frequency divider;
the second digital loop filter is used for performing digital domain filtering on the signal output by the second binary phase discriminator to generate a third control signal;
the second double-mode frequency divider is used for generating two frequency division modes according to a fourth control signal from the second differential integral modulator so as to realize fractional frequency division;
The second differential integral modulator is used for generating a fourth control signal to control the second double-mode frequency divider to realize fractional frequency division;
the second digital time converter is used for delaying the clock signal output by the second double-mode frequency divider;
the second integer frequency divider is used for integer frequency division of the clock signal output by the second digital time converter.
In some exemplary embodiments, the first binary phase detector and the second binary phase detector are each a 1-bit output phase detector, and the two input terminals respectively input an external reference clock signal and a divided feedback clock signal output by a first integer divider or a second integer divider, and the output signals of the first/second binary phase detector represent lead/lag information of the reference clock signal and the feedback clock signal.
In some exemplary embodiments, the first digital loop filter and the second digital loop filter each include a proportional path and an integral path; the proportional path realizes phase tracking, and the integral path realizes frequency tracking;
a first control signal output by a first digital loop filter in the loop A is connected with the numerical control oscillator to perform frequency tuning;
And a third control signal output by the second digital loop filter in the loop B is connected with the first differential integral modulator of the loop A to adjust the fractional frequency division coefficient of the loop A.
In some exemplary embodiments, the digitally controlled oscillator is based on a ring oscillation structural design, and the first control signal from the first digital loop filter controls the current magnitude injected into the digitally controlled oscillator by the PMOS array to realize frequency tuning of the digitally controlled oscillator;
the digitally controlled oscillator further includes a finite impulse response filter.
In some exemplary embodiments, the finite impulse response filter is turned on when the frequency modulator outputs a narrowband modulated signal to achieve quantization noise reduction.
In some exemplary embodiments, the first dual-mode frequency divider and the second dual-mode frequency divider are each a divide by 4/5 frequency divider designed based on a current-mode frequency divider, and can divide an input high-frequency clock signal by 4 or 5 under selection of the second control signal or the fourth control signal to achieve fractional frequency division. In some exemplary embodiments, the overall stability and noise performance of the overall circuit using divide-by-4/5 frequency dividers is better. In some exemplary embodiments, one skilled in the art may also adjust the divider using other parameters.
In some exemplary embodiments, the first differential integral modulator is a third-order single-loop structure configured to generate the second control signal according to an input fractional division control word to control the first dual-mode frequency divider to achieve fractional division; the second control signal is a random output sequence.
The second differential integral modulator is of a third-order single-loop structure and is arranged to generate the fourth control signal according to an input fractional frequency division control word so as to control the second double-mode frequency divider to realize fractional frequency division; the fourth control signal is a random output sequence.
The fractional frequency division control word input into the first differential integral modulator in the loop A is determined by a third control signal output by a second digital loop filter of the loop B and an external input; the fractional division control word input to the second differential integral modulator in the loop b is determined by an external input.
The external inputs include: a narrow-band low-pass modulation signal, a wide-band high-pass modulation signal or a wide-band low-pass modulation signal in the modulation signal to be output.
In some exemplary embodiments, the first differential integral modulator and the second differential integral modulator are both operated at a high frequency below 1GHz, and quantization noise generated by the first differential integral modulator and the second differential integral modulator can be further pushed to a higher frequency to be effectively filtered, so that the overall noise performance of the modulator is improved. In some exemplary embodiments, the first differential integral modulator and the second differential integral modulator operate in a frequency range of 500MHz-650MHz or 500MHz-700 MHz.
In some exemplary embodiments, the first digital time converter and the second digital time converter are each composed of 16 delay units, and the delay time of each delay unit is one eighth of the period of the output clock signal of the numerically controlled oscillator;
the first digital-to-time converter is configured to control a delay of an output signal of the first digital-to-time converter according to an input fractional frequency division control word (fifth control signal) of the first differential integral modulator and a second control signal output by the first differential integral modulator to reduce deterministic jitter generated due to two frequency division modes of the first dual-mode frequency divider and improve performance. That is, the fractional frequency division control word (fifth control signal) inputted to the first differential integral modulator and the second control signal outputted from the first differential integral modulator are inputted to the first digital time converter, and the control word control delay chain (delay chain constituted by delay units) is generated by the digital section in the first digital time converter.
The second digital-to-time converter is configured to control a delay of the output signal of the second digital-to-time converter based on the input fractional frequency division control word (sixth control signal) of the second differential integral modulator and the fourth control signal output by the second differential integral modulator to reduce deterministic jitter due to the two frequency division modes of the second dual-mode frequency divider and to improve performance. That is, the fractional frequency division control word (sixth control signal) input to the second differential integral modulator and the fourth control signal output from the second differential integral modulator are both input to the second digital time converter, and a control word control delay chain (delay chain constituted by delay units) is generated by the digital part in the second digital time converter.
In some exemplary embodiments, the first integer divider is an all-digital circuit based on a digital gate design, and the seventh control signal controls the input clock signal to be divided correspondingly. In some exemplary embodiments, the seventh control signal is a 5-bit control signal.
In some exemplary embodiments, the second integer divider is an all-digital circuit based on a digital gate design, and the eighth control signal controls the input clock signal to be divided correspondingly. In some exemplary embodiments, the eighth control signal is a 5-bit control signal.
In some exemplary embodiments, loop b in the universal frequency modulator is turned on when wideband modulation is performed; the loop A is also opened when broadband modulation is performed; and the numerical control oscillator of the loop A outputs a broadband modulation signal. Namely, when broadband modulation is carried out, a loop B in the universal frequency modulator is opened; the loop A is opened; the numerical control oscillator of the loop A outputs a broadband modulation signal;
or alternatively, the process may be performed,
loop B in the general frequency modulator is closed when narrow-band modulation is carried out; the loop A is opened when narrow-band modulation is carried out; the numerical control oscillator of the loop A outputs a narrow-band modulation signal; the high-pass modulation part of the required narrow-band modulation signal is input into the numerically controlled oscillator when narrow-band modulation is performed. That is, loop b in the universal frequency modulator is closed when narrowband modulation is performed; the loop A is opened; and a narrow-band high-pass modulation signal in the signal to be modulated is input into the numerical control oscillator, and the numerical control oscillator of the loop A outputs the narrow-band modulation signal.
In some exemplary embodiments, loop b in the universal frequency modulator is closed when narrowband modulation is performed; the loop A is started when the narrow-band modulation is carried out, the digital control oscillator also inputs a narrow-band high-pass modulation signal, and a finite impulse response filter in the digital control oscillator is started; the high-pass modulation part of the required narrow-band modulation signal is input into the numerical control oscillator when narrow-band modulation is carried out; the numerical control oscillator of the loop A outputs a narrow-band modulation signal. That is, loop b in the universal frequency modulator is closed when narrowband modulation is performed; the loop A is opened; the finite impulse response filter in the numerical control oscillator is started; a narrow-band high-pass modulation signal in the signal to be modulated is input into the numerical control oscillator; the numerical control oscillator of the loop A outputs a narrow-band modulation signal.
The universal frequency modulator based on the reconfigurable all-digital phase-locked loop of the embodiment of the disclosure has the capability of respectively performing wideband and narrowband frequency modulation in the same modulator. The universal modulator is based on an all-digital binary phase-locked loop design, and is simpler in circuit and easy to realize. Meanwhile, the reconfigurable structure can realize good modulation linearity according to requirements, a complex and high-power-consumption background digital calibration module is not needed to overcome nonlinearity of key modules in a circuit, the design of a general modulator is further simplified, and the power consumption is reduced.
Example two
The embodiment of the disclosure also provides a universal frequency modulator, which is based on a reconfigurable all-digital phase-locked loop, as shown in fig. 1. And reconfiguring the internal all-digital phase-locked loop to form two topological structures corresponding to the modulation signals according to the narrowband modulation signals or the broadband modulation signals of the required output modulation signals, and finally completing frequency modulation of the signals by adopting a two-point modulation technology. The configurable all-digital phase-locked loop used comprises two loops: loop a and loop b. Only the loop A works when the narrow-band modulation signal is output, and the finite impulse response filter of the digital controlled oscillator in the loop A is in an on state; loop b is also turned on at the same time when the wideband modulation signal is output, and loop a is combined into a new frequency modulator (topology) to accommodate the wideband modulation requirement, but the fir filter in loop a is turned off at this time.
As shown in fig. 1, the loop b of the configurable all-digital phase-locked loop includes other components in the loop a except for not including the digitally controlled oscillator; that is, the constituent elements included in the loop a and the loop b are the same except for the digitally controlled oscillator. As shown in fig. 1, loop a includes: binary phase discriminator, digital loop filter, digital controlled oscillator, dual-mode frequency divider, differential integral modulator, digital time converter, integer frequency divider; loop b includes: binary phase detector, digital loop filter, dual-mode frequency divider, differential integral modulator, digital time converter, integer frequency divider.
In some exemplary embodiments, the binary phase detector gives a 1-bit output signal based on lead/lag information of the phase between an externally given reference clock signal and the divided feedback clock signal; the digital loop filter comprises a proportional path and an integral path which are respectively used for realizing phase tracking and frequency tracking, and generates corresponding digital control signals according to output phase signals of the corresponding binary phase detectors and records the corresponding digital control signals as first control signals. In loop a, the first control signal output by the digital loop filter is used to control the digitally controlled oscillator, and in loop b, the third control signal output by the digital loop filter is used to control the differential integral modulator of loop a. The numerical control oscillator is designed based on a ring oscillation structure and comprises a finite impulse response filter to reduce quantization noise during narrow-band modulation; controlling the current magnitude of a PMOS (P-channel Metal-Oxide-Semiconductor) array injected into the oscillator by a digital control signal (first control signal) to realize frequency tuning of the oscillator; in the loop A, the dual-mode frequency divider is a divide-by-4/5 frequency divider designed based on a current-mode frequency divider, and the input high-frequency clock signal is divided by 4 or 5 under the selection of a control signal (a second control signal) output by a differential integral modulator in the loop A, so that fractional frequency division is realized; in the loop A, the differential integral modulator is of a third-order single-loop structure, and generates a random output sequence according to a given fractional frequency division control word (marked as a fifth control signal) to control the dual-mode frequency divider to realize fractional frequency division, wherein the random output sequence is the second control signal. In the loop B, the dual-mode frequency divider is a divide-by-4/5 frequency divider designed based on a current-mode frequency divider, and the input high-frequency clock signal is divided by 4 or 5 under the selection of a control signal (fourth control signal) output by a differential integral modulator in the loop B, so that fractional frequency division is realized; in the loop II, the differential integral modulator is of a third-order single-loop structure, and generates a random output sequence according to a given fractional frequency division control word (marked as a sixth control signal) to control the dual-mode frequency divider to realize fractional frequency division, wherein the random output sequence is the fourth control signal.
In loop a the fractional-division control word (fifth control signal) is determined jointly by the third control signal output by the digital loop filter of loop b and the external input, while in loop b the fractional-division control word (sixth control signal) is determined by the external input. In loop a, the frequency division control word (fifth control signal) is determined by adding the third control signal and a wideband high-pass modulation signal or a narrowband low-pass modulation signal in the signal to be modulated inputted from outside. In loop b, the frequency division control word (sixth control signal) is determined by the wideband low-pass modulation signal and the fractional frequency division coefficient in the externally input signal to be modulated.
In loop a and loop b, the digital-to-time converter is composed of a preset number (e.g., 16) of delay units, reducing deterministic jitter due to the two frequency division modes of the dual-mode frequency divider. The number of delay cells can be adjusted as required by a person skilled in the art, and is not limited to the 16 delay cells defined in the present embodiment.
In the loop A and the loop B, the integer frequency divider is an all-digital circuit based on digital gate circuit design, and is controlled by a control signal (the loop A is marked as a seventh control signal, the loop B is marked as an eighth control signal, and the integer frequency divider is not shown in the current drawing) to realize corresponding frequency division on an input clock signal. For example, in some exemplary embodiments, the seventh control signal and the eighth control signal are each 5-bit control signals.
In some exemplary embodiments, the topology of the universal frequency modulator in the case of narrowband modulation and wideband modulation is shown in fig. 2 and 3, respectively, denoted as a first topology and a second topology. Fig. 2 shows the topology (first topology) of the modulator in operation in the case of a narrow-band frequency modulation with a modulation index smaller than 1, the low-frequency part and the high-frequency part of the signal to be modulated being connected to the differential integrating modulator and the digitally controlled oscillator of the loop a, respectively. Only the loop A in the circuit is in a working state, and the loop B is in a closing state. The fractional division control word (fifth control signal) of the differential integral modulator in loop a is now given by the low frequency part of the signal to be modulated. Meanwhile, in order to restrain the quantization noise of the high-pass branch, the finite impulse response filter of the digital oscillator in the loop A is in an on state.
As shown in fig. 2, loop b is closed, the binary phase detector in loop a inputs the reference frequency signal and the feedback clock signal fed back by the integer divider, and outputs a 1-bit output signal representing the advance/retard information of the phase between the reference clock signal and the divided feedback clock signal; the digital loop filter inputs a 1-bit signal output by the binary phase discriminator and outputs a first control signal; the digital control oscillator inputs a first control signal and a narrow-band high-pass modulation signal and outputs the narrow-band modulation signal; the dual-mode frequency divider inputs a narrow-band modulation signal from the numerical control oscillator and a second control signal from the differential integral modulator and outputs a fractional frequency-divided signal; the differential integral modulator inputs the fractional frequency division signal from the dual-mode frequency divider and the fractional frequency division control word (fifth control signal) and outputs a second control signal; the digital time converter inputs the fractional frequency divided signal from the dual-mode frequency divider and outputs the delayed signal to the integer frequency divider.
It can be seen that in fig. 2 loop b is closed (grey part closed is not working) the fractional division control word (fifth control signal) of the differential integral modulator input to loop a is determined by the narrowband low pass modulation signal.
The narrow-band high-pass modulation signal is a high-pass modulation part of a required narrow-band modulation signal, namely a high-pass modulation part in a signal to be modulated; the narrowband low-pass modulated signal is the low-pass modulated portion of the desired narrowband modulated signal, i.e., the low-pass modulated portion of the signal to be modulated.
Fig. 3 shows the topology (second topology) of the modulator in operation in case of wideband frequency modulation with a modulation index much larger than 1, the low frequency part and the high frequency part of the signal to be modulated being connected to the differential integral modulator of loop b and the differential integral modulator of loop a, respectively. Because the linearity of the oscillator is a key factor of circuit performance under the broadband modulation condition, the loop A and the loop B are simultaneously started to work, wherein the loop A works as a nested numerical control oscillator of the loop B, and a numerical control oscillator with good linearity is provided for the loop B.
As shown in fig. 3, both loop b and loop a are open. The binary phase discriminator in the loop A inputs a reference frequency signal and a feedback clock signal fed back by the integer frequency divider, and outputs a 1-bit output signal representing the advance/retard information of the phase between the reference clock signal and the feedback clock signal after frequency division; the digital loop filter inputs a 1-bit signal output by the binary phase discriminator and outputs a first control signal; the digital control oscillator inputs a first control signal and outputs a broadband modulation signal; the dual-mode frequency divider inputs a broadband modulation signal from the numerical control oscillator and a second control signal from the differential integral modulator and outputs a fractional frequency-divided signal; the differential integral modulator inputs the fractional frequency division signal from the dual-mode frequency divider and the fractional frequency division control word (fifth control signal) and outputs a second control signal; the digital time converter inputs the fractional frequency divided signal from the dual-mode frequency divider and outputs the delayed signal to the integer frequency divider.
The binary phase discriminator in the loop B inputs a reference frequency signal and a feedback clock signal fed back by the integer frequency divider, and outputs a 1-bit output signal representing the advance/retard information of the phase between the reference clock signal and the feedback clock signal after frequency division; the digital loop filter inputs the 1-bit signal output by the binary phase discriminator and outputs a third control signal; the third control signal output by the digital loop filter is input into the differential integral modulator of the loop A; the dual-mode frequency divider inputs a broadband modulation signal from the numerical control oscillator of the loop A and a fourth control signal from the self differential integral modulator and outputs a fractional frequency divided signal; the differential integral modulator inputs the fractional frequency division signal from the dual-mode frequency divider and the fractional frequency division control word (sixth control signal) and outputs a fourth control signal; the digital time converter inputs the fractional frequency divided signal from the dual-mode frequency divider and outputs the delayed signal to the integer frequency divider.
It can be seen that loop b in fig. 3 is open; the fractional division control word (fifth control signal) of the differential integral modulator input to loop a is set by the wideband high-pass modulation signal and the third control signal from loop b; the fractional division control word (sixth control signal) of the differential integral modulator input to loop b is determined by the wideband low-pass modulation signal and the fractional division coefficient.
The broadband high-pass modulation signal is a high-pass modulation part of a required broadband modulation signal, namely a high-pass modulation part in a signal to be modulated; the wideband low-pass modulated signal is the low-pass modulated portion of the desired wideband modulated signal, i.e., the low-pass modulated portion of the signal to be modulated.
It can be seen that the digital time converter adopted in the loop A and the loop B can cope with the noise aliasing problem generated after the cascade connection of the dual-mode frequency divider and the integer frequency divider; the cascade mode of the dual-mode frequency divider, the digital time converter and the integer frequency divider can be used for remarkably optimizing noise of the whole circuit.
The input/output of each module/component shown in fig. 1-3 is a related data flow schematic, and does not represent the entire input/output of each module/component, and those skilled in the art will be able to recognize other aspects in combination with the basic functions and features of each module/component.
The universal frequency modulator of the embodiment of the disclosure reconfigures the structure of the internal all-digital phase-locked loop according to the required output modulation signal, and realizes good modulation performance while eliminating a complex background nonlinear calibration circuit. The universal frequency modulator is based on a reconfigurable fractional all-digital phase-locked loop design, and adopts two-point modulation to realize frequency modulation of signals. The universal frequency modulator is reconfigured aiming at two loops contained in the all-digital phase-locked loop under different requirements of outputting broadband modulation signals or narrowband modulation signals, so that the universal frequency modulator can adapt to the requirements of different signal modulations and linearity without a complex and high-power-consumption real-time linear calibration circuit, and has the advantages of simple structure, easiness in integration and lower power consumption.
Example III
The embodiment of the disclosure also provides a frequency modulation method, which comprises the following steps:
according to bandwidth modulation requirements, controlling the working states of a loop A and a loop B in the universal frequency modulator to realize different configurations of the topological structure of the all-digital phase-locked loop, and obtaining corresponding frequency modulation signals from the output end of the numerical control oscillator;
wherein the bandwidth modulation requirement comprises: broadband modulation and narrowband modulation.
In some exemplary embodiments, according to bandwidth modulation requirements, controlling the working states of the loop a and the loop b in the universal frequency modulator to implement different configurations of the topology structure of the all-digital phase-locked loop includes:
when the bandwidth modulation requirement is narrow-band modulation, the loop B is controlled to be closed, the loop A is opened, and the all-digital phase-locked loop is configured into a first topological structure;
and when the modulation requirement is broadband modulation, controlling the loop B to be opened, opening the loop A, and configuring the all-digital phase-locked loop into a second topological structure.
In some exemplary embodiments, the digitally controlled oscillator further comprises a finite impulse response filter;
according to bandwidth modulation requirements, controlling working states of a loop A and a loop B in the universal frequency modulator to realize different configurations of topological structures of the all-digital phase-locked loop, wherein the method comprises the following steps:
When the bandwidth modulation requirement is narrow-band modulation, the loop B is controlled to be closed, the loop A is opened, and a finite impulse response filter in the numerical control oscillator is opened; controlling a narrow-band high-pass modulation signal in a signal to be modulated to be input into the numerical control oscillator; controlling a narrow-band low-pass modulation signal in a signal to be modulated to be input into the first differential integral modulator so as to determine the first topological structure of the all-digital phase-locked loop; the digitally controlled oscillator outputs a narrowband modulation signal when the universal frequency modulator configuration is operating in the first topology.
When the modulation requirement is broadband modulation, controlling the loop B to be opened, and controlling the loop A to be opened; controlling a broadband high-pass modulation signal in a signal to be modulated to be input into the first differential integral modulator; controlling a broadband low-pass modulation signal in a signal to be modulated to be input into the second differential integral modulator so as to determine the second topological structure of the all-digital phase-locked loop; the digitally controlled oscillator outputs a wideband modulation signal when the universal frequency modulator configuration is operating in the second topology.
Example IV
The embodiment of the present disclosure further provides a frequency modulation method, which uses the universal frequency modulator according to the above embodiment to perform frequency modulation, including:
Acquiring a bandwidth modulation requirement, closing a loop B in the universal frequency modulator and opening a loop A when the bandwidth modulation requirement is narrowband modulation; acquiring a narrow-band modulation signal output by a numerical control oscillator of the loop A;
when the bandwidth adjustment requirement is broadband modulation, opening a loop B and a loop A in the universal frequency modulator; and obtaining a broadband modulation signal output by the numerical control oscillator of the loop A.
The disclosed embodiments also provide an electronic device comprising a memory, a processor, the memory storing a computer program for frequency modulation, the processor being arranged to read and run the computer program for frequency modulation to perform the method according to any of the embodiments above.
The disclosed embodiments also provide an electronic device comprising a memory, a processor and a general-purpose frequency modulator as described in any of the above, the memory storing a computer program for frequency modulation, the processor being arranged to read and run the computer program for frequency modulation to perform the method as described in any of the embodiments above to control the general-purpose frequency modulator to obtain a corresponding frequency modulated signal.
It can be seen that the frequency modulator scheme provided by the embodiments of the present disclosure has the following technical characteristics and beneficial effects:
1. the narrowband modulation and the broadband modulation can be realized in the same frequency modulator at the same time, and the method is suitable for wired communication and wireless communication.
2. The universal frequency modulator is based on an all-digital phase-locked loop design, and the realization of digitalization enables the universal frequency modulator to have good process portability and compatibility, and meanwhile, the digital realization has a compact structure and a better chip area.
3. The all-digital phase-locked loop structure is reconfigurable, and can be configured into the most suitable topological structure under narrow-band modulation and wide-band modulation to meet the requirements of circuit linearity under two different modulation modes. A complex and high-power-consumption background digital calibration module is not needed to overcome nonlinearity of key modules in the circuit, and only initial calibration and pre-tuning are needed for process deviation and frequency requirements of different channels, so that the design of the circuit is greatly simplified, and the power consumption of the circuit is reduced.
In describing embodiments of the present disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," etc. are directional or positional relationships indicated based on the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the presently disclosed embodiments, unless expressly stated and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intermediary. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (8)
1. A universal frequency modulator, comprising:
a configurable all-digital phase-locked loop, the all-digital phase-locked loop comprising two loops: loop a and loop b;
the loop A comprises: a first binary phase detector, a first digital loop filter, a digital controlled oscillator, a first dual-mode frequency divider, a first differential integral modulator, a first digital time converter, a first integer frequency divider; the loop B comprises: a second binary phase detector, a second digital loop filter, a second double-mode frequency divider, a second differential integral modulator, a second digital time converter, a second integer frequency divider;
the output end of the first digital loop filter of the loop A is connected with the input end of the numerical control oscillator; the output signals of the numerical control oscillator are respectively input into the first double-mode frequency divider and the second double-mode frequency divider;
the output end of the second digital loop filter of the loop B is connected with the input end of the first differential integral modulator of the loop A;
the first binary phase discriminator is used for comparing the phase information of the reference clock signal and the feedback clock signal from the first integer frequency divider;
The first digital loop filter is used for performing digital domain filtering on the signal output by the first binary phase discriminator to generate a first control signal;
the digital control oscillator is used for generating an output modulation signal according to a first control signal output by the first digital loop filter;
the first dual-mode frequency divider is used for generating two frequency dividing modes according to a second control signal from the first differential integral modulator so as to realize fractional frequency division;
the first differential integral modulator is used for generating a second control signal to control the first dual-mode frequency divider to realize fractional frequency division;
the first digital time converter is used for delaying the clock signal output by the first dual-mode frequency divider;
the first integer frequency divider is used for integer frequency division of the clock signal output by the first digital time converter;
the second binary phase detector is used for comparing the phase information of the reference clock signal and the feedback clock signal from the second integer frequency divider;
the second digital loop filter is used for performing digital domain filtering on the signal output by the second binary phase discriminator to generate a third control signal;
The second double-mode frequency divider is used for generating two frequency division modes according to a fourth control signal from the second differential integral modulator so as to realize fractional frequency division;
the second differential integral modulator is used for generating a fourth control signal to control the second double-mode frequency divider to realize fractional frequency division;
the second digital time converter is used for delaying the clock signal output by the second double-mode frequency divider;
the second integer frequency divider is used for performing integer frequency division on the clock signal output by the second digital time converter;
the first differential integral modulator is of a third-order single-loop structure and is arranged to generate the second control signal according to an input fractional frequency division control word so as to control the first dual-mode frequency divider to realize fractional frequency division;
the second differential integral modulator is of a third-order single-loop structure and is arranged to generate the fourth control signal according to an input fractional frequency division control word so as to control the second double-mode frequency divider to realize fractional frequency division;
the fractional frequency division control word input into the first differential integral modulator in the loop A is determined by a third control signal output by a second digital loop filter of the loop B and an external input; the fractional frequency division control word input into the second differential integral modulator in the loop B is determined by an external input;
The external inputs include: a narrowband low-pass modulation signal, a wideband high-pass modulation signal or a wideband low-pass modulation signal in the signal to be modulated.
2. The universal frequency modulator of claim 1, wherein,
the first digital loop filter and the second digital loop filter each include a proportional path and an integral path; the proportional path realizes phase tracking, and the integral path realizes frequency tracking;
a first control signal output by a first digital loop filter in the loop A is connected with the numerical control oscillator to perform frequency tuning;
and a third control signal output by the second digital loop filter in the loop B is connected with the first differential integral modulator of the loop A to adjust the fractional frequency division coefficient of the loop A.
3. The universal frequency modulator of claim 1, wherein,
the numerical control oscillator is based on a ring oscillation structure design, and a first control signal from a first digital loop filter controls the current of the PMOS array injected into the numerical control oscillator so as to realize frequency tuning of the numerical control oscillator;
the digitally controlled oscillator further includes a finite impulse response filter.
4. A universal frequency modulator according to any of claims 1-3, characterized in that,
when broadband modulation is carried out, a loop B in the universal frequency modulator is started, a loop A is started, and a digital control oscillator of the loop A outputs a broadband modulation signal;
or alternatively, the process may be performed,
and when narrowband modulation is carried out, a loop B in the universal frequency modulator is closed, a loop A is opened, a narrowband high-pass modulation signal in a signal to be modulated is input into the numerical control oscillator, and the numerical control oscillator of the loop A outputs a narrowband modulation signal.
5. A universal frequency modulator according to claim 3, characterized in that,
when narrowband modulation is carried out, a loop B in the universal frequency modulator is closed, a loop A is opened, a finite impulse response filter in the numerical control oscillator is opened, a narrowband high-pass modulation signal in a signal to be modulated is input into the numerical control oscillator, and the numerical control oscillator of the loop A outputs a narrowband modulation signal.
6. A method of frequency modulation, comprising:
according to bandwidth modulation requirements, controlling the working states of a loop A and a loop B in the universal frequency modulator according to any one of claims 1-5 to realize different configurations of the topological structure of the all-digital phase-locked loop, and outputting corresponding frequency modulation signals from the numerical control oscillator;
Wherein the bandwidth modulation requirement comprises: broadband modulation and narrowband modulation.
7. The method of claim 6, wherein the step of providing the first layer comprises,
the numerically controlled oscillator further comprises a finite impulse response filter;
according to bandwidth modulation requirements, controlling working states of a loop A and a loop B in the universal frequency modulator to realize different configurations of topological structures of the all-digital phase-locked loop, wherein the method comprises the following steps:
when the bandwidth modulation requirement is narrow-band modulation, the loop B is controlled to be closed, the loop A is opened, and a finite impulse response filter in the numerical control oscillator is opened; controlling a narrow-band high-pass modulation signal in a signal to be modulated to be input into the numerical control oscillator; controlling a narrow-band low-pass modulation signal in a signal to be modulated to be input into the first differential integral modulator so as to determine a first topological structure of the all-digital phase-locked loop;
when the modulation requirement is broadband modulation, controlling the loop B to be opened, and controlling the loop A to be opened; controlling a broadband high-pass modulation signal in a signal to be modulated to be input into the first differential integral modulator; and controlling a broadband low-pass modulation signal in the signal to be modulated to be input into the second differential integral modulator so as to determine a second topological structure of the all-digital phase-locked loop.
8. An electronic device comprising a memory, a processor, characterized in that the memory has stored therein a computer program for frequency modulation, the processor being arranged to read and run the computer program for frequency modulation to perform the method according to claim 6 or 7.
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| GB8729996D0 (en) * | 1987-12-23 | 1988-02-03 | Marconi Instruments Ltd | Frequency/phase modulation |
| US7015738B1 (en) * | 2003-06-18 | 2006-03-21 | Weixun Cao | Direct modulation of a voltage-controlled oscillator (VCO) with adaptive gain control |
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| CA2281522C (en) * | 1999-09-10 | 2004-12-07 | Philsar Electronics Inc. | Delta-sigma based two-point angle modulation scheme |
| US8193866B2 (en) * | 2007-10-16 | 2012-06-05 | Mediatek Inc. | All-digital phase-locked loop |
| US8634512B2 (en) * | 2011-02-08 | 2014-01-21 | Qualcomm Incorporated | Two point modulation digital phase locked loop |
| US9035682B2 (en) * | 2012-12-29 | 2015-05-19 | Motorola Solutions, Inc. | Method and apparatus for single port modulation using a fractional-N modulator |
| CN110365333B (en) * | 2019-05-30 | 2022-11-18 | 芯创智（北京）微电子有限公司 | Differential integration half-digital phase-locked loop |
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| GB8729996D0 (en) * | 1987-12-23 | 1988-02-03 | Marconi Instruments Ltd | Frequency/phase modulation |
| US7015738B1 (en) * | 2003-06-18 | 2006-03-21 | Weixun Cao | Direct modulation of a voltage-controlled oscillator (VCO) with adaptive gain control |
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