CN113206654B - Differential bus driver - Google Patents
Differential bus driver Download PDFInfo
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- CN113206654B CN113206654B CN202110347046.0A CN202110347046A CN113206654B CN 113206654 B CN113206654 B CN 113206654B CN 202110347046 A CN202110347046 A CN 202110347046A CN 113206654 B CN113206654 B CN 113206654B
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- 239000003990 capacitor Substances 0.000 claims description 10
- 230000000630 rising effect Effects 0.000 claims description 9
- 238000007599 discharging Methods 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000004891 communication Methods 0.000 abstract description 6
- 230000005670 electromagnetic radiation Effects 0.000 abstract description 4
- 230000008054 signal transmission Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Abstract
In an embodiment of the present disclosure, there is provided a differential bus driver including: a high-side first-stage driving circuit and a high-side second-stage driving circuit which are sequentially connected to the high-side bus terminal; a low-side first-stage driving circuit and a low-side second-stage driving circuit connected in sequence at the low-side bus terminal; the high side first stage drive circuit and the low side first stage drive circuit are configured to isolate a negative high voltage of the bus terminal, and the high side second stage drive circuit and the low side second stage drive circuit are configured to isolate a positive high voltage of the bus terminal. The invention can be used for vehicle-mounted or industrial data communication, the bus end can bear higher positive pressure and negative pressure, and simultaneously, the swing rate of bus signals can be controlled, and the swing rate of bus driving is adjustable so as to reduce electromagnetic radiation during signal transmission.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a differential bus driver.
Background
In industrial control and in-vehicle networks, a pair of differential buses is often used to transmit signals, with high reliability and versatility. During long distance transmission, the bus is required to withstand high voltage of +/-70V without damage due to larger parasitic inductance or other inductive load on the cable. Meanwhile, when data is transmitted, rising edges and falling edges of the bus are required to be controllable in slew rate and high in symmetry, so that electromagnetic radiation is reduced, and normal communication of other devices is interfered. In the prior art, the bus is driven by the switch control current, so that the problem that the swing rate of the bus end is uncontrollable and the output symmetry is poor exists.
Disclosure of Invention
Accordingly, embodiments of the present disclosure provide a differential bus driver that may be used for vehicle-mounted or industrial data communications, such as CAN bus and RS485 bus, where the bus terminals may be subjected to high positive and negative pressures (+/-70V), while the slew rate of the bus signals may be controlled, with the slew rate of the bus driving being adjustable to reduce electromagnetic emissions during signal transmission.
In order to achieve the above object, the present invention provides the following technical solutions:
a differential bus driver comprising:
A high-side first-stage driving circuit and a high-side second-stage driving circuit which are sequentially connected to the high-side bus terminal;
a low-side first-stage driving circuit and a low-side second-stage driving circuit connected in sequence at the low-side bus terminal;
The high side first stage drive circuit and the low side first stage drive circuit are configured to isolate a negative high voltage of the bus terminal, and the high side second stage drive circuit and the low side second stage drive circuit are configured to isolate a positive high voltage of the bus terminal.
Further, the differential bus driving circuit further comprises a high-side third-stage driving circuit connected to the output end of the high-side second-stage driving circuit and a low-side third-stage driving circuit connected to the output end of the low-side second-stage driving circuit, and the Gao Cedi third-stage driving circuit and the low-side third-stage driving circuit are configured to control rising edge and falling edge slew rates of the differential bus.
Further, the high-side first-stage driving circuit and the low-side first-stage driving circuit adopt high-voltage PMOS tubes to isolate negative high voltage of the bus terminal.
Further, the high-side first-stage driving circuit and the low-side first-stage driving circuit further comprise a zener diode, wherein the zener diode is used for maintaining the gate-source voltage difference of the high-voltage PMOS tube in a low-voltage range.
Further, the high-side second-stage driving circuit and the low-side second-stage driving circuit isolate positive high voltage of the bus terminal by adopting a high-voltage NMOS tube.
Further, the low-side third-stage driving circuit comprises a first low-voltage NMOS tube, a second low-voltage NMOS tube and a first capacitor; the drain electrode of the first low-voltage NMOS tube is connected with the output of the low-side second-stage driving circuit, the first capacitor is connected with the grid electrodes of the first low-voltage NMOS tube and the second low-voltage NMOS tube, the drain electrode of the first low-voltage NMOS tube, and the low-voltage NMOS device further comprises a first current source and a first resistor which are connected with the drain electrode of the second low-voltage NMOS tube and used for charging and discharging the first low-voltage NMOS tube and the second low-voltage NMOS tube.
Further, the low-voltage NMOS transistor further comprises a first switch and a second switch which are connected between the second low-voltage NMOS transistor and the first current source and the first resistor.
Further, the Gao Cedi-stage driving circuit comprises a first low-voltage PMOS tube, a second low-voltage PMOS tube and a second capacitor; the drain electrode of the first low-voltage PMOS tube is connected with the output of the high-side second-stage driving circuit, the second capacitor is connected with the grid electrodes of the first low-voltage PMOS tube and the second low-voltage PMOS tube, the drain electrode of the first low-voltage PMOS tube, and the second low-voltage PMOS tube further comprises a second current source and a second resistor which are connected with the drain electrode of the second low-voltage PMOS tube and are used for charging and discharging the first low-voltage PMOS tube and the second low-voltage PMOS tube.
Further, the low-voltage PMOS transistor further comprises a third switch and a fourth switch which are connected between the second low-voltage PMOS transistor and the second current source and the second resistor.
Further, the first low-voltage NMOS tube and the second low-voltage NMOS tube, and the first low-voltage PMOS tube and the second low-voltage PMOS tube drive the bus in a current mirror mode.
The differential bus driver has the beneficial effects that the invention provides a novel differential bus driver structure which can bear high positive pressure and negative pressure on the bus side, can control the slew rate of bus signals during transmission, has good symmetry and reduces electromagnetic radiation.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a conventional differential bus driver architecture;
FIG. 2 is a typical communication waveform of a differential bus (CAN);
FIG. 3 is a diagram illustrating a slew rate adjustable differential bus driving architecture according to the present invention;
FIG. 4 is a schematic diagram of a first stage and a second stage architecture implementation of the present invention;
FIG. 5 is a diagram of a low-side bus third-level slew rate drive implementation of the present invention;
FIG. 6 is a third-stage slew rate drive implementation of the high-side bus of the present invention.
Detailed Description
Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
Referring to fig. 1, a conventional differential bus driver architecture is shown in fig. 1. The PMOS transistor 10 and the diode 11 are connected to the power supply and the high-side bus, and the NMOS transistor 13 and the diode 12 are connected to the ground and the low-side bus. The PMOS transistor 10 and the NMOS transistor 13 are directly controlled by a switch or a current source, and lack slew rate control. In order to bear positive and negative high voltages, the PMOS transistor 10 and the NMOS transistor 13 must be high voltage transistors, and the symmetry of bus driving is poor due to poor matching of the high voltage transistors.
Referring to fig. 2, a typical waveform for differential bus (CAN) communications is shown in fig. 2. In the recessive state (logic 1 is input), the high-side bus and the low-side bus voltages are Vcc/2; in the dominant state (input logic 0), the high side bus is pulled high and the low side bus is pulled low. Due to the influence of driving capability and parasitic capacitance, the differential bus is often not symmetrically pulled up or pulled down, so that the common mode point potential ((high-side bus+low-side bus)/2) of the differential bus can shake, electromagnetic radiation is generated, and communication of other devices is affected.
Next, the slew rate adjustable differential bus driver of the present invention is described with reference to fig. 3-6.
Referring to fig. 3, a novel differential bus driver architecture of the present invention is shown in fig. 3. Comprising the following steps: the high-side first-stage driving circuit, the high-side third-stage driving circuit and the high-side second-stage driving circuit are sequentially connected to the high-side bus terminal; the low-side first-stage driving circuit, the low-side second-stage driving circuit and the low-side third-stage driving circuit are sequentially connected to the low-side bus terminal; the high-side first-stage driving circuit and the low-side first-stage driving circuit are configured to isolate a negative high voltage of a bus terminal, and the high-side second-stage driving circuit and the low-side second-stage driving circuit are configured to isolate a positive high voltage of the bus terminal; the Gao Cedi-level and low-side third-level drive circuits are configured to control rising and falling edge slew rates of the differential bus.
The high-side bus is connected to the power supply through the first, second and third stages, respectively, and the low-side bus is also connected to ground through the first, second and third stages. The two-sided buses all employ a symmetrical three stage architecture, wherein the first stage is configured to withstand negative high voltages, while positive high voltages pass through it, and the second stage is configured to withstand positive high voltages, such that neither positive nor negative high voltages enter the third stage. The third stage is a low slew rate drive stage for controlling the rising and falling edge slopes of the bus, requiring high consistency and symmetry.
Referring to fig. 4, a detailed implementation of the first and second stages on the high and low sides is shown in fig. 4. The high-side and low-side buses enter the high-voltage NMOS transistor 41 in the second stage through the high-voltage PMOS transistor 40 in the first stage, respectively, and the output (source) of the NMOS transistor 41 is connected to the third stage. The first stage employs a high voltage PMOS tube 40 to isolate the negative pressure on the bus side, which is connected to the bus. When the bus is negative, the source and gate of the high voltage PMOS transistor 40 can be kept not pulled down in the normal low voltage range, and when the bus is positive, the positive voltage flows into the second stage through the high voltage PMOS transistor 40. The zener diode 42 is used for maintaining the voltage difference between the gate and the source of the high-voltage PMOS transistor 40 in the low-voltage range, so as to ensure that the gate oxide thereof is not broken down. The second stage adopts a high-voltage NMOS tube 41 to isolate positive high voltage, the high-voltage side of the high-voltage NMOS tube is connected with the output of the first stage, and the source stage of the high-voltage NMOS tube is connected with the third stage. Thus, the third stage sees a low voltage domain, regardless of whether the bus side is positive or negative high voltage.
Referring to fig. 5, a specific implementation of the low-side bus third stage drive circuit is shown in fig. 5. The first low-voltage NMOS 50 and the second low-voltage NMOS 51 are current mirror type to drive the bus, the drain of the first low-voltage NMOS 50 is connected to the output of the second stage in fig. 4, and the first current source and the first resistor 52 are used to charge and discharge the current mirror first low-voltage NMOS 50 and the second low-voltage NMOS 51. When the bus is dominant driving, the first switch 54 is closed, the second switch 53 is opened, the bias current 55 (first current source) charges the current mirror (first low voltage NMOS 50, second low voltage NMOS 51), the miller capacitance (first capacitance 56) connects the gates of the first low voltage NMOS 50 and the second low voltage NMOS 51, and the drain (third stage input) of the first low voltage NMOS 50. Due to the miller capacitance effect, the drain falling slope of the first low voltage NMOS transistor 50 is equal to Ibias/Cc, ibias being the current value of the bias current 55, cc being the capacitance value of the first capacitor 56. The falling edge slew rate of the bus can be adjusted by adjusting the capacitance and the bias current. During recessive driving, the first switch 54 is opened and the second switch 53 is closed, and the gate of the current mirror is discharged to ground through the first resistor 52. Similarly, due to the miller capacitance effect, the drain rising slope of the first low voltage NMOS 50 is equal to Vth/(r×cc), where R is the resistance of the first resistor 52, and Vth is the threshold voltage of the current mirror. The slew rate of the rising edge of the bus can be adjusted by adjusting the first resistor 52.
Referring to fig. 6, a specific implementation of a third stage of the high-side bus is shown in fig. 6. The first low-voltage PMOS transistor 60 and the second low-voltage PMOS transistor 61 are in a current mirror form to drive the bus, the drain of the first low-voltage PMOS transistor 60 is connected to the output of the second stage in fig. 4, and the second current source and the second resistor 62 are used for charging and discharging the current mirror first low-voltage PMOS transistor 60 and the second low-voltage PMOS transistor 61. At the time of dominant driving, the third switch 64 is closed, the fourth switch 63 is opened, the bias current 65 (second current source) charges the current mirror (first low voltage PMOS transistor 60, second low voltage PMOS transistor 61), the miller capacitance (second capacitance 66) connects the gates of the first low voltage PMOS transistor 60 and the second low voltage PMOS transistor 61, and the drain (third stage input) of the first low voltage PMOS transistor 60. Due to the miller capacitance effect, the drain rising slope of the first low voltage PMOS transistor 60 is equal to Ibias/Cc, ibias is the current value of the bias current 65, cc is the capacitance value of the second capacitor 66. The rising edge slew rate of the bus can be adjusted by adjusting the capacitance and the bias current. At the time of the recessive driving, the third switch 64 is opened, the fourth switch 63 is closed, and the gate of the current mirror is discharged to the ground through the second resistor 62. Similarly, due to the miller capacitance effect, the drain falling slope of the first low voltage PMOS transistor 60 is equal to Vth/(r×cc), R is the resistance of the second resistor 62, and Vth is the threshold voltage of the current mirror. Adjusting the second resistor 62 adjusts the falling edge slew rate of the bus.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the disclosure are intended to be covered by the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (4)
1. A differential bus driver, comprising:
A high-side first-stage driving circuit and a high-side second-stage driving circuit which are sequentially connected to the high-side bus terminal;
a low-side first-stage driving circuit and a low-side second-stage driving circuit connected in sequence at the low-side bus terminal;
The high-side first-stage driving circuit and the low-side first-stage driving circuit adopt a high-voltage PMOS (P-channel metal oxide semiconductor) tube to isolate negative high voltage of a bus terminal, the high-side first-stage driving circuit and the low-side first-stage driving circuit also comprise a zener diode, the zener diode is used for maintaining the gate-source voltage difference of the high-voltage PMOS tube in a low-voltage range, and the high-side second-stage driving circuit and the low-side second-stage driving circuit adopt a high-voltage NMOS tube to isolate positive high voltage of the bus terminal;
A high-side third stage drive circuit connected to the output of the high-side second stage drive circuit, and a low-side third stage drive circuit connected to the output of the low-side second stage drive circuit, the Gao Cedi third stage drive circuit and the low-side third stage drive circuit configured to control rising and falling edge slew rates of a differential bus;
The low-side third-stage driving circuit comprises a first low-voltage NMOS tube, a second low-voltage NMOS tube and a first capacitor, wherein the drain electrode of the first low-voltage NMOS tube is connected with the output of the low-side second-stage driving circuit, the first capacitor is connected with the grid electrodes of the first low-voltage NMOS tube and the second low-voltage NMOS tube, the drain electrode of the first low-voltage NMOS tube, and the low-side third-stage driving circuit further comprises a first current source and a first resistor which are connected with the drain electrodes of the second low-voltage NMOS tube and is used for charging and discharging the first low-voltage NMOS tube and the second low-voltage NMOS tube;
The Gao Cedi-level driving circuit comprises a first low-voltage PMOS tube, a second low-voltage PMOS tube and a second capacitor, wherein the drain electrode of the first low-voltage PMOS tube is connected with the output of the high-side second-level driving circuit, the second capacitor is connected with the grid electrodes of the first low-voltage PMOS tube and the second low-voltage PMOS tube, the drain electrode of the first low-voltage PMOS tube, and the Gao Cedi-level driving circuit further comprises a second current source and a second resistor which are connected with the drain electrode of the second low-voltage PMOS tube and is used for charging and discharging the first low-voltage PMOS tube and the second low-voltage PMOS tube.
2. The differential bus driver of claim 1, further comprising a first switch and a second switch connected between the second low voltage NMOS transistor and the first current source and the first resistor.
3. The differential bus driver of claim 1, further comprising third and fourth switches connected between the second low voltage PMOS transistor and a second current source and a second resistor.
4. The differential bus driver as in claim 3, wherein the first and second low voltage NMOS transistors and the first and second low voltage PMOS transistors each drive the bus in a current mirror.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110347046.0A CN113206654B (en) | 2021-03-31 | 2021-03-31 | Differential bus driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110347046.0A CN113206654B (en) | 2021-03-31 | 2021-03-31 | Differential bus driver |
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| Publication Number | Publication Date |
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| CN113206654A CN113206654A (en) | 2021-08-03 |
| CN113206654B true CN113206654B (en) | 2024-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110347046.0A Active CN113206654B (en) | 2021-03-31 | 2021-03-31 | Differential bus driver |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104731742A (en) * | 2013-12-18 | 2015-06-24 | 英飞凌科技股份有限公司 | Bus driver circuit with improved transition speed |
| CN107346969A (en) * | 2016-05-06 | 2017-11-14 | 亚德诺半导体集团 | bus driver/line driver |
| CN110635981A (en) * | 2018-06-20 | 2019-12-31 | 英飞凌科技股份有限公司 | Drive device for a differential bus and corresponding method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102017212543A1 (en) * | 2017-07-21 | 2019-01-24 | Robert Bosch Gmbh | Transceiver for a bus system and method for reducing conducted emissions |
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2021
- 2021-03-31 CN CN202110347046.0A patent/CN113206654B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104731742A (en) * | 2013-12-18 | 2015-06-24 | 英飞凌科技股份有限公司 | Bus driver circuit with improved transition speed |
| CN107346969A (en) * | 2016-05-06 | 2017-11-14 | 亚德诺半导体集团 | bus driver/line driver |
| CN110635981A (en) * | 2018-06-20 | 2019-12-31 | 英飞凌科技股份有限公司 | Drive device for a differential bus and corresponding method |
Non-Patent Citations (1)
| Title |
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| "基于TDR 技术的HDMI 高速差分总线特性阻抗的测量";刘蕊;《电子测试》;第98-99, 132页 * |
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