CN113206091A - Two-dimensional semiconductor field effect transistor, preparation process thereof and semiconductor device - Google Patents
Two-dimensional semiconductor field effect transistor, preparation process thereof and semiconductor device Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
Abstract
The invention relates to a two-dimensional semiconductor field effect transistor, a preparation process thereof and a semiconductor device, wherein the two-dimensional semiconductor field effect transistor sequentially comprises the following components from bottom to top: an insulating substrate region, a conductive channel region, and a gate region; the conductive channel region comprises a source, a drain, a first insulating medium layer and a two-dimensional semiconductor layer, wherein the first insulating medium layer is positioned between the source and the drain, and two ends of the two-dimensional semiconductor layer are electrically connected with the source and the drain to form a source end and a drain end; the gate region comprises a high-K dielectric layer, a metal gate and a second insulating dielectric layer, the metal gate and the second insulating dielectric layer are positioned on the high-K dielectric layer, the second insulating dielectric layer comprises a plurality of through holes, and electrode leads in the through holes are electrically connected with a source, a drain and the metal gate of the two-dimensional semiconductor layer. The method is suitable for the process of forming source-drain contact by self-alignment without methods such as carbon nano tubes, novel two-dimensional materials and the like; the preparation process flow is simple, the source-drain interconnection layer graph is formed before the two-dimensional semiconductor layer is deposited, the damage of the two-dimensional material after deposition when source-drain contact is formed is reduced, and the performance and yield of the device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a two-dimensional semiconductor field effect transistor, a preparation process thereof and a semiconductor device.
Background
The field effect transistor is a cornerstone of modern electronic technology, brings revolutionary changes to computers, communication, automation, medical treatment and the like, and brings about the digital life of the current. The field effect transistor controls the current between the source and the drain through the adjustment of the grid, so that the current can realize an on state and an off state, and a logic 1 and a logic 0 are defined. Today, silicon transistors have been developed along the curve of moore's law for decades, and the volume of computer chips made of silicon material will reach the physical limit due to the limitation of the physical property of silicon element itself, which will affect the integration of the chip and further hinder the operation speed of the computer, so that the semiconductor industry has to search for new alternative materials and thus develop new semiconductor integrated circuit technology. Thus, the most pressing problem currently faced is how to fabricate smaller transistor devices and to address some of the adverse level effects encountered during device size miniaturization, such as short channel effects and small size effects.
Among the currently available new materials, binary semiconductor materials stand out for their superior properties, taking carbon nanotubes as an example, for their ultra-small size, ultra-high intrinsic mobility for electrons and holes, and ultra-long carrier mean free path. The tiny diameter (1-2nm) of the single-walled carbon nanotube enables a grid to control the potential of a channel best, and also enables a carbon nanotube field effect transistor (CNT-FET) to be an ultra thin semiconductor structure, so that the device with smaller size can be manufactured without short channel effect; the stable characteristic of valence bonds in the carbon nano tubes and the smooth tube wall surface can overcome the scattering problem caused by unstable surface valence bonds and unsmooth material surface in the traditional MOSFET, and the carbon nano tubes are used as channels to easily realize ballistic transport transistors, so that the utilization efficiency of energy is greatly improved; the low scattering effect in the carbon nanotubes enables the channel of the FET to have very high electron mobility, which can be more than 70% higher than silicon material, for faster data transfer.
Research shows that the carbon nanotube makes the CNT-FET the most promising candidate of a complementary metal oxide semiconductor (Si-CMOS) device based on a semiconductor silicon material due to excellent electrostatic control and ballistic transmission characteristics of the carbon nanotube, but the carbon nanotube has different characteristics from silicon, and a standard preparation process does not exist at present, so that a silicon process is not mature in a process flow, and the mass production of a two-dimensional semiconductor material is greatly restricted.
Disclosure of Invention
In order to overcome the technical problems, the invention provides a two-dimensional semiconductor field effect transistor and a preparation method thereof. The invention discloses the following technical scheme:
a two-dimensional semiconductor field effect transistor, characterized in that: from supreme including in proper order down: an insulating substrate region, a conductive channel region, and a gate region; the conductive channel region comprises a source, a drain, a first insulating medium layer and a two-dimensional semiconductor layer, wherein the first insulating medium layer is positioned between the source and the drain, and two ends of the two-dimensional semiconductor layer are electrically connected with the source and the drain to form a source end and a drain end; the gate region comprises a high-K dielectric layer, a metal gate and a second insulating dielectric layer, the metal gate and the second insulating dielectric layer are located on the high-K dielectric layer, the second insulating dielectric layer comprises a plurality of through holes, and electrode leads in the through holes are electrically connected with a source end, a drain end and the metal gate of the two-dimensional semiconductor layer.
Meanwhile, the invention also discloses a preparation method of the two-dimensional semiconductor field effect transistor, which is characterized by comprising the following steps: the method comprises the following steps:
providing an insulating substrate:
forming patterned source and drain electrodes on the insulating substrate;
depositing a first insulating medium layer between the source electrode and the drain electrode;
arranging a two-dimensional semiconductor layer to enable the two-dimensional semiconductor layer to be electrically connected with the source electrode and the drain electrode to form source and drain ends of a conductive channel;
depositing a high-K dielectric layer to cover the conductive channel;
depositing a metal gate so that the metal gate is positioned above the conductive channel;
depositing a second insulating medium layer to enable the second insulating medium layer to cover the metal gate and the conducting channel;
the electrode lead penetrates through the second insulating medium layer and the high-K dielectric layer and is electrically connected with the source terminal and the drain terminal.
Compared with the prior art, the invention has the beneficial technical effects that: the method is suitable for the process of forming source-drain contact by self-alignment without methods such as carbon nano tubes, novel two-dimensional materials and the like; the preparation process flow is simple, the source-drain interconnection layer graph is formed before the two-dimensional semiconductor layer is deposited, the damage of the two-dimensional material after deposition when source-drain contact is formed is reduced, and the performance and yield of the device are improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
Fig. 1-6 are schematic views of the manufacturing process of the two-dimensional semiconductor field effect transistor of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It is to be understood that such description is merely illustrative and not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
Various structural schematics according to embodiments of the present invention are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In the present embodiment, a method for manufacturing a two-dimensional semiconductor field effect transistor is provided. Referring to fig. 1-6, which are schematic views of a two-dimensional semiconductor field effect transistor manufacturing process according to the present invention, the process for manufacturing the two-dimensional semiconductor field effect transistor 100 includes:
providing an insulating substrate 101;
in one embodiment, the insulating substrate 101 is a silicon dioxide substrate or a heavily doped silicon substrate with a thermal oxide silicon dioxide layer on the surface;
source and drain electrodes are patterned and formed on the substrate 101 by exposing through a photoresist, and as shown in fig. 1, 102a and 102a 'are PMOS source and drain electrodes, and 102 b' are NMOS source and drain electrodes. The source and drain electrodes may be formed by any suitable method, such as metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, Selective Epitaxial Growth (SEG), the like, or combinations thereof.
As shown in fig. 2, a first insulating dielectric layer 103-1 is deposited, the first insulating dielectric layer 103-1 separates the source and the drain, the first insulating dielectric layer 103-1 is level with the source and the drain, and the first insulating dielectric layer 103-1 is chemically and mechanically polished to form a carrier of the two-dimensional semiconductor layer. The first insulating dielectric layer 103 may be formed of a suitable dielectric material, such as silicon dioxide (SiO2), silicon nitride (SiNx), and the like.
As shown in fig. 3, a two-dimensional semiconductor layer 104 is deposited on the carrier, and in one embodiment, a CVD deposition method, a solution deposition method, and a thin film transfer method are used, so that the two-dimensional semiconductor layer 104 is electrically connected with the source and drain electrodes 102a and 102a ', and 102 b' to form source and drain terminals of a conductive channel; in one embodiment the two-dimensional semiconductor material is carbon nanotubes, graphene or molybdenum disulfide. In one embodiment, the two-dimensional semiconductor layer 104 is patterned by a masked etch.
Next, as shown in fig. 4, a high-K dielectric 105 is deposited, and in one embodiment, the high-K dielectric 105 is deposited layer by layer using an Atomic Layer Deposition (ALD) process, and the high-K dielectric 105 may have a dielectric constant higher than about 7.0, and may be a high-K dielectric such as YO, hafnium oxide, and the like.
As shown in fig. 5, a metal gate material is deposited, and a patterning process is performed on the metal gate 106 to form a gate pattern, and the etching is stopped on the surface of the high-K dielectric layer. The metal gate 106 may be a multi-layer structure, and the metal gate 106 may be made of TiN, W, AL, Mo, etc., or a combination thereof. The metal-containing gate can be formed by chemical vapor deposition, physical vapor deposition and other processes; the metal gate 106 is deposited layer by layer using an Atomic Layer Deposition (ALD) process in one embodiment.
Then, a second insulating medium layer 103-2 is deposited on the surfaces of the high-K medium layer and the metal gate, the metal gate is separated by the insulating medium layer 103-2, the two-dimensional semiconductor device is packaged, and the second insulating medium layer 103-2 is subjected to chemical mechanical polishing to form an insulating isolation layer of the two-dimensional semiconductor device. The second insulating dielectric layer 103-2 may be formed of a suitable dielectric material, such as silicon dioxide (SiO2), silicon nitride (SiNx), a multilayer dielectric material, etc., as shown in fig. 6.
And then, respectively perforating the second insulating dielectric layer above the source and drain electrodes 102a and 102a ', 102b and 102 b' and the metal gate 106 by adopting a conventional perforating process, and arranging electrode leads in the perforating holes to electrically connect the source and drain electrodes 102a and 102a ', 102b and 102 b' and the metal gate 106. In one embodiment, the electrode leads of the source and drain 102a and 102a ', and 102 b' may be routed in advance in the via holes so as not to affect the work function of the two-dimensional semiconductor material and the source and drain metals.
According to an embodiment of the present invention, there is provided a two-dimensional semiconductor field effect transistor, and fig. 6 shows an exemplary structure of the two-dimensional semiconductor field effect transistor 100 of the present invention, which includes:
from supreme including in proper order down: an insulating substrate region, a conductive channel region, and a gate region; the conductive channel region comprises a source electrode, a drain electrode, source and drain electrodes 102a and 102a ', 102b and 102 b', a first insulating medium layer 103-1 and a two-dimensional semiconductor layer 104, wherein the first insulating medium layer 103-1 is positioned between the source electrode and the drain electrode 102a and 102a ', 102b and 102 b', and two ends of the two-dimensional semiconductor layer 104 are electrically connected with the source electrode and the drain electrode 102a and 102a ', 102b and 102 b' to form a source end and a drain end; the gate region comprises a high-K dielectric layer 105, a metal gate 106 and a second insulating dielectric layer 103-2, the metal gate 106 and the second insulating dielectric layer 103-2 are positioned on the high-K dielectric layer, the second insulating dielectric layer comprises a plurality of through holes 107, and electrode leads in the through holes are electrically connected with a source terminal, a drain terminal and the metal gate of the two-dimensional semiconductor layer.
In one embodiment, the two-dimensional semiconductor layer 104 is a carbon nanotube layer, graphene or molybdenum disulfide.
In one embodiment, the material of the high-K dielectric layer 105 is YO or hafnium oxide.
In one embodiment, the metal gate 106 material is TiN, W, AL, Mo, or a combination of several.
In one embodiment, the via hole 107 further includes a filling material filling the space in the via hole outside the electrode lead.
The invention also discloses a semiconductor device which comprises the two-dimensional semiconductor field effect transistor.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
the preparation process of the two-dimensional semiconductor field effect transistor provided by the embodiment of the application is particularly suitable for a process of forming source-drain contact by self-alignment without methods such as a carbon nano tube, a novel two-dimensional material and the like; the preparation process flow is simple, the source-drain interconnection layer graph is formed before the two-dimensional semiconductor layer is deposited, the damage of the two-dimensional material after deposition when source-drain contact is formed is reduced, and the performance and yield of the device are improved.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (12)
1. A two-dimensional semiconductor field effect transistor, characterized in that: from supreme including in proper order down: an insulating substrate region, a conductive channel region, and a gate region; the conductive channel region comprises a source, a drain, a first insulating medium layer and a two-dimensional semiconductor layer, wherein the first insulating medium layer is positioned between the source and the drain, and two ends of the two-dimensional semiconductor layer are electrically connected with the source and the drain to form a source end and a drain end; the gate region comprises a high-K dielectric layer, a metal gate and a second insulating dielectric layer, the metal gate and the second insulating dielectric layer are located on the high-K dielectric layer, the second insulating dielectric layer comprises a plurality of through holes, and electrode leads in the through holes are electrically connected with a source end, a drain end and the metal gate of the two-dimensional semiconductor layer.
2. The fet of claim 1, wherein: the two-dimensional semiconductor layer is a carbon nanotube layer, graphene or molybdenum disulfide.
3. The fet of claim 1, wherein: the high-K dielectric layer material is YO or hafnium oxide.
4. The fet of claim 1, wherein: the metal gate material is TiN, W, AL, Mo or the combination of the materials.
5. The fet of claim 1, wherein: the through hole also comprises a filling material which fills the space outside the electrode lead in the through hole.
6. A preparation method of a two-dimensional semiconductor field effect transistor is characterized by comprising the following steps: the method comprises the following steps:
providing an insulating substrate:
forming patterned source and drain electrodes on the insulating substrate;
depositing a first insulating medium layer between the source electrode and the drain electrode;
arranging a two-dimensional semiconductor layer to enable the two-dimensional semiconductor layer to be electrically connected with the source electrode and the drain electrode to form source and drain ends of a conductive channel;
depositing a high-K dielectric layer to cover the conductive channel;
depositing a metal gate so that the metal gate is positioned above the conductive channel;
depositing a second insulating medium layer to enable the second insulating medium layer to cover the metal gate and the conducting channel;
the electrode lead penetrates through the second insulating medium layer and the high-K dielectric layer and is electrically connected with the source terminal and the drain terminal.
7. The method of claim 6, wherein: the two-dimensional semiconductor layer is a carbon nanotube layer, graphene or molybdenum disulfide.
8. The method of claim 6, wherein: the high-K dielectric layer material is YO or hafnium oxide.
9. The method of claim 6, wherein: the metal gate material is TiN, W, AL, Mo or the combination of the materials.
10. The method of claim 6, wherein: further comprising the steps of: and forming through holes in the second insulating medium layer and the high-K dielectric layer, so that the electrode lead passes through the second insulating medium layer and the high-K dielectric layer and is electrically connected with the source terminal and the drain terminal.
11. The method of claim 10, wherein: the through hole also comprises a filling material which fills the space outside the electrode lead in the through hole.
12. A semiconductor device characterized in that it comprises a two-dimensional semiconductor field effect transistor according to any of claims 1 to 5.
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| CN202110351170.4A CN113206091A (en) | 2021-03-31 | 2021-03-31 | Two-dimensional semiconductor field effect transistor, preparation process thereof and semiconductor device |
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| CN202110351170.4A CN113206091A (en) | 2021-03-31 | 2021-03-31 | Two-dimensional semiconductor field effect transistor, preparation process thereof and semiconductor device |
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