CN113206074A

CN113206074A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN113206074A
Application number: CN202110480911.9A
Authority: CN
Inventors: 蔡佩庭; 张钦福; 冯立伟
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2021-08-03
Anticipated expiration: 2041-04-30
Also published as: CN113206074B

Abstract

The application provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a plurality of lower electrodes which are arranged at intervals; wherein the lower electrode has an outer side portion; a support layer disposed around each of the lower electrodes and directly contacting an outer side of each of the lower electrodes; wherein the support layer includes a plurality of openings arranged at intervals; each opening part is contacted with a plurality of lower electrodes, the outer side part of the side wall of each lower electrode is at least partially contacted with the supporting layer, and the total area of the overlapped part of the cross section of at least one lower electrode and the cross section of the opening part is more than 70% of the area of the cross section of a single lower electrode. In the application, even if the partial area of the lower electrode in contact with the supporting layer is very small, the lower electrode cannot collapse, the opening part can expose the most surface of the lower electrode, and on the basis of maintaining the fact that the lower electrode cannot collapse, the process difficulty of the capacitor dielectric layer and the upper electrode is greatly reduced.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a semiconductor device and a preparation method thereof.

Background

As semiconductor devices are becoming more densely packed, the device size per unit area is decreasing. Semiconductor devices such as Dynamic Random Access Memories (DRAMs) may require a certain level of capacitance in each cell. Therefore, in order to avoid a decrease in capacitance of the capacitive element, the capacitive element requires a larger effective surface area, such as a cylindrical shape. However, when the capacitor is formed as a lower electrode having a high aspect ratio, the capacitor may be unstable. Such as collapsing and contacting other adjacent capacitive elements, resulting in damage and leakage current.

In the prior art, in order to prevent the lower electrode from collapsing, a support layer is usually formed around the lower electrode to support the lower electrode, but the arrangement of the support layer may affect the preparation processes of the capacitance dielectric layer and the upper electrode on the surface of the lower electrode.

Disclosure of Invention

In order to solve the problems, the application provides a semiconductor device and a manufacturing method thereof, and solves the technical problem that the arrangement of the existing supporting layer can influence the manufacturing process of the capacitance dielectric layer and the upper electrode on the surface of the lower electrode.

In a first aspect, the present application provides a semiconductor device comprising:

a plurality of lower electrodes arranged at intervals; wherein the lower electrode has an outer side portion;

a support layer disposed around each of the lower electrodes and directly contacting an outer side of each of the lower electrodes; wherein the support layer includes a plurality of openings arranged at intervals;

wherein each opening part is contacted with a plurality of lower electrodes, the outer side part of each lower electrode is at least partially contacted with the supporting layer, and the total area of the overlapped part of the cross section of at least one lower electrode and the cross section of the opening part is more than 70% of the area of the cross section of a single lower electrode.

In some embodiments, in the above semiconductor device, at least one of the lower electrodes is simultaneously in contact with two adjacent ones of the opening portions.

In some embodiments, in the above semiconductor device, an overlapping portion of a cross section of the two adjacent opening portions and a cross section of the lower electrode is discontinuous.

In some embodiments, in the above semiconductor device, the overlapping portion of the cross section of the two adjacent opening portions and the cross section of the lower electrode is continuous.

In some embodiments, in the above semiconductor device, the plurality of lower electrodes include a plurality of first lower electrodes arranged in a row and a plurality of second lower electrodes arranged in a row, the first and second lower electrodes are alternately arranged along a column direction, and the first and second lower electrodes are alternately arranged.

In some embodiments, in the above semiconductor device, each of the opening portions is in contact with two of the first lower electrodes and two of the second lower electrodes.

In some embodiments, in the above semiconductor device, the lower electrode has a cylindrical or columnar shape.

In some embodiments, the semiconductor device further includes:

a dielectric layer covering at least the outer side surface of the lower electrode and the surface of the support layer;

an upper electrode covering the surface of the dielectric layer; wherein, the upper electrode is filled between two adjacent lower electrodes.

In a second aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

providing a substrate;

forming a sacrificial layer over the substrate;

forming a support layer over the sacrificial layer;

forming a plurality of lower electrode openings which penetrate through the supporting layer and the sacrificial layer and are arranged at intervals;

forming a plurality of lower electrodes in the plurality of lower electrode openings; wherein the lower electrode has an outer side portion;

forming a plurality of openings penetrating through the support layer and arranged at intervals; wherein each opening part is contacted with a plurality of lower electrodes, the outer side part of each lower electrode is at least partially contacted with the supporting layer, and the total area of the overlapped part of the cross section of at least one lower electrode and the cross section of the opening part is more than 70% of the area of the cross section of a single lower electrode;

and removing the sacrificial layer.

In a third aspect, the present application provides a semiconductor device comprising:

a support layer disposed around each of the lower electrodes and directly contacting an outer side of each of the lower electrodes;

the outer side part of each lower electrode is at least partially contacted with the supporting layer, and the ratio of the contact length of at least one lower electrode outer side part and the supporting layer to the circumference of the outer side part of the lower electrode is less than 30%.

In a fourth aspect, the present application provides a semiconductor device comprising:

a plurality of lower electrodes arranged at intervals; wherein the lower electrode has an outer side portion; the plurality of lower electrodes include a plurality of first lower electrodes arranged in rows and a plurality of second lower electrodes arranged in rows, the first lower electrodes and the second lower electrodes are alternately arranged along a column direction, and the first lower electrodes and the second lower electrodes are alternately arranged;

a support layer disposed around each of the lower electrodes and directly contacting an outer side portion of each of the lower electrodes; wherein the support layer comprises a plurality of openings arranged at intervals;

wherein each of the openings includes a first opening portion and a second opening portion separated by one of the lower electrodes and simultaneously in contact with the lower electrode, the first opening portion being in contact with the two first lower electrodes and the two second lower electrodes, and the second opening portion being in contact with the two first lower electrodes and the two second lower electrodes.

In some embodiments, in the above semiconductor device, an outer side portion of the lower electrode located between the first opening portion and the second opening portion is at least partially contacted by the supporting layer.

In some embodiments, in the semiconductor device described above, a ratio of a contact length of the outer portion of the lower electrode between the first opening portion and the second opening portion to the support layer to a circumference of the outer portion of the lower electrode is less than 30%.

In some embodiments, in the above semiconductor device, in each of the openings, the first opening portion and the second opening portion are aligned in a column direction or a row direction.

In some embodiments, in the above semiconductor device, the plurality of openings are arranged in a row.

In some embodiments, the openings of two adjacent rows are aligned with each other in the semiconductor device.

In some embodiments, the openings of two adjacent rows are staggered.

In some embodiments, in the semiconductor device, a distance between two adjacent rows of the openings is greater than a row pitch of the first lower electrodes or a row pitch of the second lower electrodes.

In some embodiments, in the semiconductor device, a distance between two adjacent rows of the openings is less than or equal to a row pitch of the first lower electrodes or a row pitch of the second lower electrodes.

In some embodiments, in the above semiconductor device, in each row of the openings, two adjacent openings are spaced apart from each other by at least one of the lower electrodes.

Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:

the application provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a plurality of lower electrodes which are arranged at intervals; wherein the lower electrode has an outer side portion; a support layer disposed around each of the lower electrodes and directly contacting an outer side of each of the lower electrodes; wherein the support layer includes a plurality of openings arranged at intervals; each opening part is contacted with a plurality of lower electrodes, the outer side part of the side wall of each lower electrode is at least partially contacted with the supporting layer, and the total area of the overlapped part of the cross section of at least one lower electrode and the cross section of the opening part is more than 70% of the area of the cross section of a single lower electrode. In this application, even the cross section of a lower electrode with the total area of the overlap portion of the cross section of opening is greater than singly 70% of the cross section area of lower electrode, this lower electrode is very little with the partial area that the supporting layer contacted promptly, and this lower electrode can not collapse, and the opening can expose this lower electrode's most surface, on the basis that maintains that the lower electrode can not collapse, greatly reduced the technology degree of difficulty of capacitance dielectric layer and last electrode.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:

FIG. 1 is a schematic diagram of a front side top view of a semiconductor device shown in an exemplary embodiment of the present application;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 5 is a schematic cross-sectional view taken along line B-B' of FIG. 4;

FIG. 6 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 9 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 10 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 11 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 12 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 13 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 14 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 15 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 16 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 17 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 18 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 19 is a schematic diagram of a front side top view of another semiconductor device shown in an exemplary embodiment of the present application;

FIG. 20 is a schematic flow chart illustrating a method of fabricating a semiconductor device in accordance with an exemplary embodiment of the present application;

fig. 21 is a schematic cross-sectional structure view of a first intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;

fig. 22 is a schematic cross-sectional view of a second intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;

fig. 23 is a schematic cross-sectional view of a third intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;

fig. 24 is a schematic cross-sectional view of a fourth intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;

fig. 25 is a schematic cross-sectional view of a fifth intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;

fig. 26 is a schematic cross-sectional view of a sixth intermediate structure formed at a step associated with a method of fabricating a semiconductor device, as illustrated in an exemplary embodiment of the present application;

in the drawings, wherein like parts are designated with like reference numerals, the drawings are not necessarily to scale;

11-a substrate; 12-a lower electrode; 121-a first lower electrode; 1211 — a contact portion of the first lower electrode with the support layer; 122-a second lower electrode; 1221 — contact portion of second lower electrode with support layer; 13-a support layer; 14-an opening; 15-a dielectric layer; 16-an upper electrode; 17-a sacrificial layer; 18-lower electrode opening; 21-a substrate; 22-a lower electrode; 221-a first lower electrode; 222-a second lower electrode; 23-a support layer; 24-an opening; 25-a dielectric layer; 26-an upper electrode; 32-a lower electrode; 321-a first lower electrode; 322-a second lower electrode; 33-a support layer; 34-an opening; 341-first opening; 342-a second opening portion.

Detailed Description

The following detailed description will be provided with reference to the accompanying drawings and embodiments, so that how to apply the technical means to solve the technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and various features in the embodiments of the present application can be combined with each other without conflict, and the formed technical solutions are all within the scope of protection of the present application. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

In order to provide a thorough understanding of the present application, detailed structures and steps will be provided in the following description in order to explain the technical solutions proposed in the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

Example one

As shown in fig. 1 and 2, an embodiment of the present application provides a semiconductor device including: a substrate 11, a plurality of lower electrodes 12, a support layer 13, a plurality of openings 14, a dielectric layer 15, and an upper electrode 16.

In fig. 1, the substrate 11, the dielectric layer 15, and the upper electrode 16 are not shown in order to clearly show the shapes and positions of the lower electrode 12, the support layer 13, and the opening 14. The shape and location of the substrate 11, dielectric layer 15 and upper electrode 16 can be understood in conjunction with fig. 2.

The substrate 11 is a semiconductor substrate, and a source region and a peripheral region (not labeled in the figure) are disposed on the substrate 11, and the peripheral region is disposed on the periphery of the active region. A plurality of node contacts (not shown) are also formed in the substrate 11, and the node contacts are electrically connected to the lower electrode 12. Of course, other device structures such as an active pattern (not shown) and an isolation structure (not shown) may be formed in the substrate 11, which is not limited in this application.

A plurality of lower electrodes 12 are disposed above the substrate 11 at intervals, and the lower electrodes 12 are arranged in an array. The lower electrode 12 has a high aspect ratio, and the dimension in the Z direction of the lower electrode 12 is much larger than the dimensions in the X direction and the Y direction.

Each lower electrode 12 is shaped as a cylindrical structure with an upward opening. The material of the lower electrode 12 may be titanium nitride (TiN). The lower electrode 12 has an outer side portion.

A support layer 13 is disposed around each lower electrode 12 and in direct contact with the outer side of each lower electrode 12 to support each lower electrode 12, it being understood that the lower electrode 12 penetrates the support layer 13.

The support layer 13 is disposed on the outer side of the cylindrical lower electrode 12 and contacts with the outer side of the lower electrode 12, the extending direction of the support layer 13 is parallel to the bottom of the lower electrode 12, i.e., the transverse direction (X direction and Y direction), and the transverse support layer 13 can enhance the stability of the lower electrode 12, so that the lower electrode 12 does not collapse.

The upper surface of the support layer 13 is flush with the top of the lower electrode 12.

The material of the support layer 13 includes an insulating material, and may include at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron nitride (SiBN).

The supporting layer 13 includes a plurality of openings 14 arranged at intervals, wherein the openings 14 penetrate the supporting layer 13, each opening 14 is in contact with a plurality of lower electrodes 12, the outer side of each lower electrode 12 is at least partially in contact with the supporting layer 13, and the total area of the overlapping portions of the cross section of at least one lower electrode 12 and the cross section of the opening 14 is greater than 70% of the cross section area of a single lower electrode 12. When the lower electrode 12 is in contact with 1 opening 14, the area of the overlapping part of the cross section of the lower electrode 12 and the cross section of the opening 14 is more than 70% of the cross section area of the single lower electrode 12; when the lower electrode 12 is in contact with 2 or more than 2 opening portions 14, the total area of the overlapping portions of the cross-sections of all the opening portions 14 where the cross-section of the lower electrode 12 is in contact with the lower electrode 12 is greater than 70% of the cross-sectional area of a single lower electrode 12.

That is, in the present application, even if the total area of the overlapping portion of the cross section of the opening 14 and the cross section of the lower electrode 12 is greater than 70% of the area of the cross section of the single lower electrode 12, that is, the area of the portion of the lower electrode 12 in contact with the supporting layer 13 is small, the lower electrode 12 does not collapse, most of the surface of the lower electrode 12 is exposed by the opening 14, the dielectric layer 15 and the upper electrode 16 are prepared through the opening 14, and on the basis of maintaining the lower electrode 12 not to collapse, the process difficulty of the capacitor dielectric layer (dielectric layer 15) and the upper electrode 16 is greatly reduced, so that the process is uniformly performed, the film forming efficiency is effectively improved, and the performance of the capacitor and the semiconductor device is improved.

In some cases, the opening 14 may be further increased, that is, the contact area of the lower electrode 12 with the support layer 13 may be further decreased, and the overlapping portion of the cross section of the lower electrode 12 with the cross section of the opening 14 may be further increased. In two dimensions (X, Y), the single bottom electrode 12 can be even made to have holes around 80%, and only 20% of the bottom electrode 12 is in contact with the support layer 13, and the bottom electrode 12 will not collapse.

At least one lower electrode 12 may simultaneously contact two adjacent openings 14. And the overlapping portion of the cross section of two adjacent opening portions 14 and the cross section of the lower electrode 12 may be discontinuous, i.e., two adjacent opening portions 14 are spaced apart by the lower electrode 12.

In addition, the overlapping portions of the cross-sections of the two adjacent openings 14 and the cross-section of the lower electrode 12 may be continuous, as shown in fig. 3, i.e., the total area of the overlapping portions of the cross-sections of the two adjacent openings 14 and the cross-section of the lower electrode 12 may be further increased. The size of the opening 14 is further increased on the basis of maintaining the lower electrode 12 not to collapse, the process difficulty of the capacitor dielectric layer and the upper electrode 16 is further reduced, the process is uniformly performed, the film forming efficiency is effectively improved, and the performance of the capacitor and the semiconductor device is improved.

The plurality of lower electrodes 12 may include a plurality of first lower electrodes 121 and a plurality of second lower electrodes 122, the plurality of first lower electrodes 121 are arranged in a row, the plurality of second lower electrodes 122 are arranged in a row, the first lower electrodes 121 and the second lower electrodes 122 are alternately arranged along a column direction (Y direction), and the first lower electrodes 121 and the second lower electrodes 122 are alternately arranged.

In the present embodiment, the shape of the opening portion 14 is not limited, and in some cases, the opening portion 14 may be in contact with two first lower electrodes 121 and two second lower electrodes 122, that is, each opening portion 14 may be in contact with four lower electrodes 12 at the same time.

The dielectric layer 15 covers the surface of the lower electrode 12 and the surface of the supporting layer 13, the dielectric layer 15 is an insulating layer of a capacitor, and may be a dielectric layer with a high dielectric constant, and the material is at least one of silicon oxide and silicon nitride. The first dielectric layer 15 covers the surface of the lower electrode 12 and the surface of the support layer 13, i.e. the dielectric layer 15 extends along the contour of the lower electrode 12 and the contour of the support layer 13.

The top electrode 16 covers the surface of the dielectric layer 15 and is filled in the bottom electrode 12 and between two adjacent bottom electrodes 12. The upper electrode 16 effects planarization of the semiconductor device.

The material of the upper electrode 16 includes at least one of silicon doped with impurities, a metal material, a metal nitride, and a metal silicide.

The lower electrode 12, the dielectric layer 15, and the upper electrode 16 constitute a capacitor.

The present embodiment provides a semiconductor device including a plurality of lower electrodes 12 disposed at intervals above a substrate 11; wherein the lower electrode 12 has an outer side portion; a support layer 13 disposed around each lower electrode 12 and in direct contact with an outer side portion of each lower electrode 12; among them, the support layer 13 includes a plurality of openings 14 provided at intervals; each of the openings 14 is in contact with a plurality of lower electrodes 12, and the total area of the overlapping portions of the cross section of at least one of the lower electrodes 12 and the cross section of the opening 14 is greater than 70% of the cross section area of a single lower electrode 12. In the present application, even if the total area of the overlapping portion of the cross section of one lower electrode 12 and the cross section of the opening 14 is greater than 70% of the cross section area of a single lower electrode 12, that is, the area of the portion of the lower electrode 12 in contact with the supporting layer 13 is small, the lower electrode 12 does not collapse, the opening 14 can expose most of the surface of the lower electrode 12, and the process difficulty of the capacitor dielectric layer and the upper electrode 16 is greatly reduced on the basis of maintaining the lower electrode 12 not to collapse.

Example two

As shown in fig. 4 and 5, an embodiment of the present application provides a semiconductor device including: a substrate 21, a plurality of lower electrodes 22, a support layer 23, a plurality of openings 24, a dielectric layer 25, and an upper electrode 26.

Note that, in order to clearly show the shapes and positions of the lower electrode 22, the support layer 23, and the opening portion 24 in fig. 4, the substrate 21, the dielectric layer 25, and the upper electrode 26 are not shown in fig. 4. The shape and location of the substrate 21, dielectric layer 25 and upper electrode 26 can be understood in conjunction with fig. 5.

The substrate 21 is a semiconductor substrate, and a source region and a peripheral region (not labeled in the figure) are disposed on the substrate 21, and the peripheral region is disposed on the periphery of the active region. A plurality of node contacts (not shown) are also formed in the substrate 21, and the node contacts are electrically connected to the lower electrode 22. Of course, other device structures such as an active pattern (not shown) and an isolation structure (not shown) may be formed in the substrate 21, which is not limited in this application.

A plurality of lower electrodes 22 are disposed above the substrate 21 at intervals, and the lower electrodes 22 are arranged in an array. The lower electrode 22 has a high aspect ratio, and the dimension in the Z direction of the lower electrode 22 is much larger than the dimensions in the X direction and the Y direction.

Each of the lower electrodes 22 has a columnar structure. The material of the lower electrode 22 may be titanium nitride (TiN). The lower electrode 22 has an outer side portion.

A support layer 23 is disposed around each of the lower electrodes 22 and in contact with each of the lower electrodes 22 to support each of the lower electrodes 22, and it is also understood that the lower electrodes 22 penetrate the support layer 23.

The support layer 23 is disposed on the outer side of the pillar-shaped lower electrode 22 and directly contacts with the outer side of the lower electrode 22, the extending direction of the support layer 23 is parallel to the bottom of the lower electrode 22, i.e. the transverse direction, and the transverse support layer 23 can enhance the stability of the lower electrode 22, so that the lower electrode 22 does not collapse.

The upper surface of the support layer 23 is flush with the top of the lower electrode 22.

The material of the support layer 23 includes an insulating material, and may include at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron nitride (SiBN).

The support layer 23 includes a plurality of openings 24 arranged at intervals, wherein the openings 24 penetrate through the support layer 23, each opening 24 is in contact with a plurality of lower electrodes 22, the outer side of each lower electrode 22 is at least partially in contact with the support layer 23, and the total area of the overlapping portions of the cross section of at least one lower electrode 22 and the cross section of the opening 24 is greater than 70% of the cross section area of a single lower electrode 22. When the lower electrode 22 contacts 1 opening 24, the area of the overlapped part of the cross section of the lower electrode 22 and the cross section of the opening 24 is more than 70% of the cross section area of the single lower electrode 22; when the lower electrode 22 is in contact with 2 or more than 2 opening portions 24, the total area of the overlapping portions of the cross-sections of all the opening portions 24 of which the cross-section of the lower electrode 22 is in contact with the lower electrode 22 is greater than 70% of the cross-sectional area of a single lower electrode 22.

That is, in the present application, even if the total area of the overlapping portion of the cross section of the lower electrode 22 and the cross section of the opening 24 is greater than 70% of the cross section area of a single lower electrode 22, that is, the area of the portion of the lower electrode 22 in contact with the supporting layer 23 is small, the lower electrode 22 does not collapse, the opening 24 exposes most of the surface of the lower electrode 22, the dielectric layer 25 and the upper electrode 26 are prepared through the opening 24, and on the basis of maintaining the lower electrode 22 not to collapse, the process difficulty of the capacitor dielectric layer (dielectric layer 25) and the upper electrode 26 is greatly reduced, so that the process is uniformly performed, the film forming efficiency is effectively improved, and the performance of the capacitor and the semiconductor device is improved.

In some cases, the opening 24 may be further increased, that is, the contact area of the lower electrode 22 with the support layer 23 may be further decreased, and the overlapping portion of the cross section of the lower electrode 22 with the cross section of the opening 24 may be further increased. In two dimensions (X, Y), the single bottom electrode 22 can be even made with holes around 80%, and only 20% of the bottom electrode 22 is in contact with the support layer 23, and the bottom electrode 22 will not collapse.

At least one lower electrode 22 may simultaneously contact two adjacent opening portions 24. And the overlapping portion of the cross section of two adjacent opening portions 24 and the cross section of the lower electrode 22 may be discontinuous, i.e., two adjacent opening portions 24 are spaced apart by the lower electrode 22.

In addition, the overlapping portions of the cross-sections of the two adjacent opening portions 24 and the cross-section of the lower electrode 22 may be continuous, as shown in fig. 3, that is, the total area of the overlapping portions of the cross-sections of the two adjacent opening portions 24 and the cross-section of the lower electrode 22 may be further increased. The size of the opening 24 is further increased on the basis of maintaining the lower electrode 22 not to collapse, the process difficulty of the capacitor dielectric layer and the upper electrode 26 is further reduced, the process is uniformly performed, the film forming efficiency is effectively improved, and the performance of the capacitor and the semiconductor device is improved.

The plurality of lower electrodes 22 include a plurality of first lower electrodes 221 and a plurality of second lower electrodes 222, the plurality of first lower electrodes 221 are arranged in a row, the plurality of second lower electrodes 222 are arranged in a row, the first lower electrodes 221 and the second lower electrodes 222 are alternately arranged along a column direction (Y direction), and the first lower electrodes 221 and the second lower electrodes 222 are alternately arranged.

In the present embodiment, the shape of the opening portion 24 is not limited, and in some cases, the opening portion 24 may be in contact with two first lower electrodes 221 and two second lower electrodes 222, that is, each opening portion 24 may be in contact with four lower electrodes 22 at the same time.

The dielectric layer 25 covers the surface of the lower electrode 22 and the surface of the support layer 23, the dielectric layer 25 is an insulating layer of a capacitor, and may be a high dielectric constant dielectric layer, and the material is at least one of silicon oxide and silicon nitride. The first dielectric layer 25 covers the surface of the lower electrode 22 and the surface of the support layer 23, i.e. the dielectric layer 25 extends along the contour of the lower electrode 22 and the contour of the support layer 23.

The upper electrode 26 covers the surface of the dielectric layer 25 and is filled between two adjacent lower electrodes 22. The upper electrode 26 achieves planarization of the semiconductor device.

The material of the upper electrode 26 includes at least one of silicon doped with impurities, a metal material, a metal nitride, and a metal silicide.

The lower electrode 22, the dielectric layer 25, and the upper electrode 26 constitute a capacitor.

The present embodiment provides a semiconductor device including a plurality of lower electrodes 22 disposed at intervals above a substrate 21; wherein the lower electrode 22 has an outer side portion; a support layer 23 disposed around each lower electrode 22 and directly contacting an outer side portion of each lower electrode 22; among them, the support layer 23 includes a plurality of openings 24 provided at intervals; wherein each opening 24 is in contact with a plurality of lower electrodes 22, and the total area of the overlapping portions of the cross section of at least one lower electrode 12 and the cross section of the opening 24 is greater than 70% of the cross section area of a single lower electrode 22. In the present application, even if the total area of the overlapping portion of the cross section of one lower electrode 22 and the cross section of the opening portion 24 is greater than 70% of the cross section area of a single lower electrode 22, that is, the area of the portion of the lower electrode 22 in contact with the supporting layer 23 is small, the lower electrode 22 will not collapse, the opening portion 24 exposes most of the surface of the lower electrode 22, and the process difficulty of the capacitor dielectric layer and the upper electrode 26 is greatly reduced on the basis of maintaining the lower electrode 22 not to collapse.

EXAMPLE III

As shown in fig. 6, an embodiment of the present application provides another semiconductor device, including: a plurality of lower electrodes 12, a support layer 13, and a plurality of openings 14.

The plurality of lower electrodes 12 are arranged in an array. Each lower electrode 12 may be in the shape of a cylindrical structure or a columnar structure. The material of the lower electrode 12 may be titanium nitride (TiN). Wherein the lower electrode 12 has an outer side.

The support layer 13 is disposed around each lower electrode 12 and directly contacts an outer side portion of each lower electrode 12 to support each lower electrode 12.

The support layer 13 is provided on the outer side of the cylindrical or columnar lower electrode 12 and contacts the outer side of the lower electrode 12. The material of the support layer 13 includes an insulating material, and may include at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron nitride (SiBN).

The outer side of each lower electrode 12 is at least partially in contact with the support layer 13, and the ratio of the contact length (the length of the contact portion 1211 or 1221) of the outer side of each lower electrode 12 with the support layer 13 to the circumference of the outer side of the lower electrode 12 is less than 30%.

The portion of the outer side of the lower electrode 12 not in contact with the support layer 13 may be exposed due to the provision of the opening 14 in the support layer 13.

When the lower electrode 12 is in contact with 1 opening 14, the ratio of the contact length of the lower electrode 12 and the supporting layer 13 to the outer circumference of the single lower electrode 12 is less than 30% (i.e. 1 opening 14 is exposed by more than 70%); when the lower electrode 12 contacts 2 or more than 2 openings 14, the ratio of the contact length of the lower electrode 12 and the supporting layer 13 to the outer circumference of the single lower electrode 12 is less than 30% (i.e. 2 or more than 2 openings 14 are exposed to more than 70% in total).

That is to say, in the present application, even if the ratio of the contact length corresponding to the lower electrode 12 to the outer side circumference of a single lower electrode 12 is less than 30%, that is, the length of the contact portion between the lower electrode 12 and the supporting layer 13 is very short, the lower electrode 12 does not collapse, the opening 14 exposes most of the surface of the lower electrode 12, so that the dielectric layer and the upper electrode are prepared through the opening 14, and on the basis of maintaining the lower electrode 12 not to collapse, the process difficulty of the capacitor dielectric layer and the upper electrode is greatly reduced, the process is performed uniformly, the film formation efficiency is effectively improved, and thus the performance of the capacitor and the semiconductor device is improved.

In some cases, the opening portion 14 may be further increased, that is, the contact length of the lower electrode 12 with the support layer 13 may be further decreased. Even a single bottom electrode 12 can be made with holes around 80%, and only 20% of the bottom electrode 12 is in contact with the support layer 13, and the bottom electrode 12 will not collapse.

In the present embodiment, the above features are described based on a two-dimensional plane (plane where X, Y is located).

The present embodiment provides a semiconductor device including a plurality of lower electrodes 12 arranged at intervals; a support layer 13 disposed around each lower electrode 12 and in direct contact with an outer side portion of each lower electrode 12; wherein, the outer side of each lower electrode 12 is at least partially contacted with the supporting layer 13, and the ratio of the contact length of at least one lower electrode 12 and the supporting layer 13 to the circumference of the outer side of the lower electrode 12 is less than 30%. In the present application, even if the ratio of the contact length of the lower electrode 12 to the supporting layer 13 to the outer circumference of the lower electrode 12 is less than 30%, i.e., the contact portion of the lower electrode 12 to the supporting layer 13 is small, the lower electrode 12 does not collapse.

Example four

As shown in fig. 7, an embodiment of the present application provides a semiconductor device including: a plurality of lower electrodes 32, a support layer 33, and a plurality of openings 34.

The plurality of lower electrodes 32 are arranged in an array.

Each lower electrode 32 has a cylindrical structure or a columnar structure in shape. The material of the lower electrode 32 may be titanium nitride (TiN). The lower electrode 32 has an outer side.

The plurality of lower electrodes 32 include a plurality of first lower electrodes 321 and a plurality of second lower electrodes 322, the plurality of first lower electrodes 321 are arranged in a row, the plurality of second lower electrodes 322 are arranged in a row, the first lower electrodes 321 and the second lower electrodes 322 are alternately arranged along a column direction (Y direction), and the first lower electrodes 321 and the second lower electrodes 322 are alternately arranged.

The support layer 33 is disposed around each of the lower electrodes 32 and directly contacts an outer side of each of the lower electrodes 32 to support each of the lower electrodes 32.

The support layer 33 is provided on the outer side of the cylindrical or columnar lower electrode 32 and contacts the outer side of the lower electrode 32.

The material of the support layer 33 includes an insulating material, and may include at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron nitride (SiBN).

The support layer 33 includes a plurality of openings 34 arranged at intervals therethrough, each of the openings 34 includes a first opening portion 341 and a second opening portion 342 separated by one of the lower electrodes 32 and simultaneously contacting the lower electrode 32, the first opening portion 341 contacts the two first lower electrodes 321 and the two second lower electrodes 322, and the second opening portion 342 contacts the two first lower electrodes 321 and the two second lower electrodes 322.

That is, the first opening 341 and the second opening 342 are in contact with four lower electrodes 32, and are in contact with three lower electrodes 32, respectively, in addition to being in contact with the lower electrode 32 therebetween at the same time.

The outer side portion of the lower electrode 32 located between the first opening portion 341 and the second opening portion 342 is at least partially in contact with the support layer 33. That is, in order to prevent the lower electrode 32 located between the first opening portion 341 and the second opening portion 342 from collapsing, the lower electrode 32 needs to be at least partially in contact with the support layer 33.

In some cases, a ratio of a contact length of the outer portion of the lower electrode 32 between the first opening portion 341 and the second opening portion 342 to the support layer 33 to a circumference of the outer portion of the lower electrode 22 is less than 30%.

That is to say, in the present application, even if the ratio of the contact length corresponding to the lower electrode 32 to the outer circumference of the single lower electrode 32 is less than 30%, that is, the length of the contact portion between the lower electrode 32 and the supporting layer 33 is very short, the lower electrode 32 does not collapse, the opening 34 exposes most of the surface of the lower electrode 32, and a dielectric layer (not shown in the figure) and an upper electrode (not shown in the figure) are prepared through the opening 34, so that the process difficulty of the capacitor dielectric layer and the upper electrode is greatly reduced on the basis of maintaining the lower electrode 32 not to collapse, the process is performed uniformly, the film formation efficiency is effectively improved, and the performance of the capacitor and the semiconductor device is improved.

In some cases, the opening 34 may be further increased, i.e., the contact length of the lower electrode 32 and the supporting layer 33 may be further decreased, i.e., the single lower electrode 32 may even be made to have holes around 80%, and only 20% of the lower electrode 32 is in contact with the supporting layer 33, and the lower electrode 32 will not collapse.

In the present embodiment, of each opening 34, the first opening portion 341 and the second opening portion 342 are aligned along the column direction (Y direction) and the plurality of openings 34 are arranged in a row.

The openings 34 in two adjacent rows are aligned, and the distance between the openings 34 in two adjacent rows may be greater than the line pitch of the first lower electrodes 321 or the line pitch of the second lower electrodes 322 (as shown in fig. 7, 8, 9, and 10), or may be less than or equal to the line pitch of the first lower electrodes 321 or the line pitch of the second lower electrodes 322 (as shown in fig. 11).

In each row of openings 34, two adjacent openings 34 are spaced apart from each other by at least one lower electrode 32, for example, as shown in fig. 7 and 8, in each row of openings 34, two adjacent openings 34 are spaced apart from each other by two lower electrodes 32; as shown in fig. 9, 10 and 11, in each row of openings 34, two adjacent openings 34 are spaced apart from each other by one lower electrode 32.

In the present embodiment, the above features are described based on a two-dimensional plane.

The present embodiment provides a semiconductor device including a plurality of lower electrodes 32 provided at intervals; the plurality of lower electrodes 32 include a plurality of first lower electrodes 321 and a plurality of second lower electrodes 322, the plurality of first lower electrodes 321 are arranged in a row, the plurality of second lower electrodes 322 are arranged in a row, the first lower electrodes 321 and the second lower electrodes 322 are alternately arranged along a column direction, and the first lower electrodes 321 and the second lower electrodes 322 are alternately arranged; a support layer 33 disposed around each lower electrode 32 and directly contacting an outer side portion of each lower electrode 32; wherein the supporting layer 33 comprises a plurality of openings 34 arranged at intervals; each of the openings 34 includes a first opening portion 341 and a second opening portion 342 separated by one of the lower electrodes 32 and simultaneously contacting the lower electrode 32, the first opening portion 341 contacting the two first lower electrodes 321 and the two second lower electrodes 322, and the second opening portion 342 contacting the two first lower electrodes 321 and the two second lower electrodes 322. In the present application, in each opening 34, the first opening 341 and the second opening 342 are separated by a lower electrode 32, the contact area between the lower electrode 32 and the supporting layer 33 is small, the lower electrode 32 does not collapse, the opening 34 exposes most of the surface of the lower electrode 32, and the process difficulty of the capacitor dielectric layer and the upper electrode is greatly reduced on the basis of maintaining the lower electrode 32 not to collapse.

EXAMPLE five

On the basis of the fourth embodiment, the present embodiment provides another semiconductor device, which also includes a plurality of lower electrodes 32, a support layer 33, and a plurality of openings 34.

In the present embodiment, the shapes of the respective members are the same as those of the fourth embodiment, and in each of the openings 34, the first opening portion 341 and the second opening portion 342 are aligned along the column direction (Y direction) and the plurality of openings 34 are arranged in a row.

The present embodiment is different from the fourth embodiment only in that: the openings 34 in two adjacent rows are staggered.

In this case, the distance between two adjacent rows of openings 34 may be greater than the line pitch of the first lower electrodes 321 or the line pitch of the second lower electrodes 322 (as shown in fig. 12), or may be less than or equal to the line pitch of the first lower electrodes 321 or the line pitch of the second lower electrodes 322 (as shown in fig. 13 and 14).

In each row of openings 34, two adjacent openings 34 are spaced apart from each other by at least one lower electrode 32, for example, as shown in fig. 13, in each row of openings 34, two adjacent openings 34 are spaced apart from each other by two lower electrodes 32; as shown in fig. 12 and 14, in each row of openings 34, two adjacent openings 34 are spaced apart from each other by one lower electrode 32.

The shapes and positions of other parts are the same as those in the fourth embodiment, and the description is omitted here

The present embodiment provides a semiconductor device including a plurality of lower electrodes 32 provided at intervals; the plurality of lower electrodes 32 include a plurality of first lower electrodes 321 and a plurality of second lower electrodes 322, the plurality of first lower electrodes 321 are arranged in a row, the plurality of second lower electrodes 322 are arranged in a row, the first lower electrodes 321 and the second lower electrodes 322 are alternately arranged along a column direction, and the first lower electrodes 321 and the second lower electrodes 322 are alternately arranged; a support layer 33 disposed around each lower electrode 32 and directly contacting an outer side portion of each lower electrode 32; wherein the supporting layer 33 comprises a plurality of openings 34 arranged at intervals; each of the openings 34 includes a first opening portion 341 and a second opening portion 342 separated by one of the lower electrodes 32 and simultaneously contacting the lower electrode 32, the first opening portion 341 contacting the two first lower electrodes 321 and the two second lower electrodes 322, and the second opening portion 342 contacting the two first lower electrodes 321 and the two second lower electrodes 322. In the present application, in each opening 34, the first opening 341 and the second opening 342 are separated by a lower electrode 32, the contact area between the lower electrode 32 and the supporting layer 33 is small, the lower electrode 32 does not collapse, the opening 34 exposes most of the surface of the lower electrode 32, and the process difficulty of the capacitor dielectric layer and the upper electrode 36 is greatly reduced on the basis of maintaining the lower electrode 32 not to collapse.

EXAMPLE six

An embodiment of the present application provides a semiconductor device, including: a plurality of lower electrodes 32, a support layer 33, and a plurality of openings 34.

The plurality of lower electrodes 32 are arranged in an array.

The support layer 33 includes a plurality of openings 34 arranged at intervals, each of the openings 34 includes a first opening portion 341 and a second opening portion 342 separated by one of the lower electrodes 32 and simultaneously in contact with the lower electrode 32, the first opening portion 341 is in contact with two of the first lower electrodes 321 and two of the second lower electrodes 322, and the second opening portion 342 is in contact with two of the first lower electrodes 321 and two of the second lower electrodes 322.

That is to say, in the present application, even if the ratio of the contact length corresponding to the lower electrode 32 to the outer side circumference of a single lower electrode 32 is less than 30%, that is, the length of the contact portion between the lower electrode 32 and the supporting layer 33 is very short, the lower electrode 32 does not collapse, the opening 34 exposes most of the surface of the lower electrode 32, and a dielectric layer (not shown in the figure) and an upper electrode (not shown in the figure) are prepared through the opening 34, so that the process difficulty of the capacitor dielectric layer and the upper electrode is greatly reduced on the basis of maintaining the lower electrode 32 not to collapse, the process is performed uniformly, the film forming efficiency is effectively improved, and the performance of the capacitor and the semiconductor device is improved.

In some cases, the opening 34 may be further increased, that is, the contact length of the lower electrode 32 and the support layer 33 may be further decreased, and the single lower electrode 32 may even be made to have holes around 80%, and only 20% of the lower electrode is in contact with the support layer 33, and the lower electrode 32 may not collapse.

In the present embodiment, of each opening 34, the first opening portion 341 and the second opening portion 342 are aligned along the row direction (X direction) and the plurality of openings 34 are arranged in a row.

The two adjacent rows of openings 34 are aligned, and the distance between the two adjacent rows of openings 34 may be greater than the line pitch of the first lower electrodes 321 or the line pitch of the second lower electrodes 322 (as shown in fig. 15), or may be less than or equal to the line pitch of the first lower electrodes 321 or the line pitch of the second lower electrodes 322 (as shown in fig. 16).

In each row of openings 34, two adjacent openings 34 are spaced apart from each other by at least one lower electrode 32, for example, as shown in fig. 15, in each row of openings 34, two adjacent openings 34 are spaced apart from each other by two lower electrodes 32; as shown in fig. 16, in each row of openings 34, two adjacent openings 34 are spaced apart from each other by one lower electrode 32.

EXAMPLE seven

On the basis of the sixth embodiment, the present application provides another semiconductor device, which also includes: a plurality of lower electrodes 32, a support layer 33, and a plurality of openings 34.

In the present embodiment, the shapes of the respective members are the same as those in the sixth embodiment, and in each of the openings 34, the first opening portion 341 and the second opening portion 342 are aligned along the column direction (Y direction) and the plurality of openings 34 are arranged in a row.

The present embodiment is different from the sixth embodiment only in that: the openings 34 in two adjacent rows are staggered.

In this case, the distance between two adjacent rows of openings 34 may be greater than the line pitch of the first lower electrodes 321 or the line pitch of the second lower electrodes 322 (as shown in fig. 17), or may be smaller than or equal to the line pitch of the first lower electrodes 321 or the line pitch of the second lower electrodes 322 (as shown in fig. 18 and 19).

In each row of openings 34, adjacent two openings 34 are spaced apart from each other by at least one lower electrode 32, for example, as shown in fig. 17 and 18, in each row of openings 34, adjacent two openings 34 are spaced apart from each other by two lower electrodes 32; as shown in fig. 19, in each row of the openings 34, two adjacent openings 34 are spaced apart from each other by three lower electrodes 32.

The shapes and positions of other parts are the same as those in the sixth embodiment, and the description is omitted here

Example eight

On the basis of the first embodiment or the second embodiment, as shown in fig. 20, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:

step S110: a substrate 11 is provided.

The substrate 11 is a semiconductor substrate 11, and a source region and a peripheral region (not labeled in the figure) are disposed on the substrate 11, and the peripheral region is disposed on the periphery of the active region. A plurality of node contacts (not shown) are also formed in the substrate 11, and the node contacts are electrically connected to the lower electrode 12. Of course, other device structures such as an active pattern (not shown) and an isolation structure (not shown) may be formed in the substrate 11, which is not limited in this application.

Step S120: a sacrificial layer 17 is formed over the substrate 11.

The sacrificial layer 17 is used to form a base for forming the subsequent support layer 13 and the lower electrode 12.

Step S130: as shown in fig. 21, the support layer 13 is formed over the sacrifice layer 17.

The extending direction of the support layer 13 is parallel to the extending direction of the substrate 11.

Step S140: as shown in fig. 22, a plurality of lower electrode openings 18 are formed to penetrate the support layer 13 and the sacrificial layer 17 and to be spaced apart.

Specifically, a mask etching method may be used to form a plurality of lower electrode openings 18 that penetrate through the support layer 13 and the sacrificial layer 17 and are disposed at intervals.

Wherein the lower electrode opening 18 is used for subsequently forming the lower electrode 12 with a high aspect ratio.

The plurality of lower electrode openings 18 are arranged in an array, and the cross-sectional shape of each lower electrode opening 18 is circular.

The plurality of lower electrode openings 18 may include a plurality of first lower electrode openings (not labeled) and a plurality of second lower electrode openings (not labeled), the plurality of first lower electrode openings are arranged in a row, the plurality of second lower electrode openings 122 are arranged in a row, the first lower electrode openings and the second lower electrode openings are alternately arranged along a column direction (Y direction), and the first lower electrode openings and the second lower electrode openings are alternately arranged.

Step S150: as shown in fig. 23, a plurality of lower electrodes 12 are formed in the plurality of lower electrode openings 18.

The lower electrode 12 is shaped as a cylindrical or columnar structure with an upward opening. The material of the lower electrode 12 may be titanium nitride (TiN).

The plurality of lower electrodes 12 are arranged in an array corresponding to the lower electrode openings 18.

The plurality of lower electrodes 12 may include a plurality of first lower electrodes 121 (disposed in the first lower electrode openings) and a plurality of second lower electrodes 122 (disposed in the second lower electrode openings), the plurality of first lower electrodes 121 are arranged in a row, the plurality of second lower electrodes 122 are arranged in a row, the first lower electrodes 121 and the second lower electrodes 122 are alternately disposed along a column direction (Y direction), and the first lower electrodes 121 and the second lower electrodes 122 are alternately disposed.

Step S160: as shown in fig. 24, a plurality of openings 14 are formed through the support layer 13 and provided at intervals; wherein each opening 14 is in contact with a plurality of lower electrodes 12, the outer side of each lower electrode 12 is at least partially in contact with the support layer 13, and the total area of the overlapping portions of the cross section of at least one lower electrode 12 and the cross section of the opening 14 is greater than 70% of the cross section area of a single lower electrode 12.

In order to remove the sacrificial layer 17 and form the dielectric layer 15 and the upper electrode 16 on the surface of the lower electrode 12, it is necessary to form an opening 14 on the support layer 13 to expose the sacrificial layer 17 and provide a flow channel of an etcher for the subsequent removal of the sacrificial layer 17.

A plurality of openings 14 are formed at intervals to penetrate the support layer 13, wherein each of the openings 14 is in contact with a plurality of lower electrodes 12, and the total area of the overlapping portions of the cross section of at least one of the lower electrodes 12 and the cross section of the opening 14 is greater than 70% of the cross section area of a single lower electrode 12. That is, in the present application, even if the total area of the overlapping portions of the cross section of at least one lower electrode 12 and the cross section of the opening 14 is greater than 70% of the cross section area of a single lower electrode 12, that is, the area of the portion of the lower electrode 12 in contact with the supporting layer 13 is small, the lower electrode 12 does not collapse, and the opening 14 can expose a large area of the sacrificial layer 17, which is beneficial to the removal uniformity of the sacrificial layer 17.

In some cases, the opening 14 may be further increased, that is, the contact area of the lower electrode 12 with the support layer 13 may be further decreased, and the overlapping portion of the cross section of the lower electrode 12 with the cross section of the opening 14 may be further increased. Even a single bottom electrode 12 can be made with holes around 80%, and only 20% of the bottom electrode 12 is in contact with the support layer 13, and the bottom electrode 12 will not collapse.

Step S170: as shown in fig. 25, the sacrificial layer 17 is removed.

Specifically, the opening 14 is used to remove the sacrificial layer 17 by an etching method, and the opening 14 exposes a large area of the sacrificial layer 17, which is beneficial to the entering of an etchant to improve the etching efficiency of the sacrificial layer 17 and the removal uniformity of the sacrificial layer 17.

Step S180: as shown in fig. 26, a dielectric layer 15 is formed to cover the surface of the lower electrode 12 and the surface of the support layer 13.

Step S190: forming an upper electrode 16 covering the surface of the dielectric layer 15; wherein, the upper electrode 16 is filled between two adjacent lower electrodes 12.

The removal of the sacrifice layer 17 makes the opening portion 14 available for providing a passage of a film forming gas for the subsequent formation of the capacitor dielectric layer and the upper electrode 16. Therefore, the inside and outside of the cylindrical structure of the lower electrode 12, or the outside of the columnar structure, are made to communicate with the opening 14, so that the film forming gas can enter below the support layer 13 through the opening 14, whereby the corresponding capacitor dielectric layer and the upper electrode 16 can be formed on both the inside and outside of the cylindrical structure of the lower electrode 12, or on the outside of the columnar structure.

The dielectric layer 15 covers the surface of the lower electrode 12 and the surface of the supporting layer 13, the dielectric layer 15 is an insulating layer of a capacitor, and may be a dielectric layer with a high dielectric constant, and the material is at least one of silicon oxide and silicon nitride. The first dielectric layer 15 covers the surface of the lower electrode 12 and the support layer 33, i.e. the dielectric layer 15 extends along the contour of the lower electrode 12 and the contour of the support layer 13.

The upper electrode 16 covers the surface of the dielectric layer 15 and is filled between two adjacent lower electrodes 12, and when the lower electrodes 12 are cylindrical, the upper electrode 16 is also filled in the lower electrodes 12. The upper electrode 16 effects planarization of the semiconductor device.

In this embodiment, even if the total area of the overlapping portions of the cross section of one lower electrode 12 and the cross section of the opening portion 14 is more than 70% of the cross section area of a single lower electrode 12, that is, the partial area of the lower electrode 12 in contact with the support layer 13 is small, the lower electrode 12 does not collapse.

On the basis of maintaining the lower electrode 12 not to collapse, the removal efficiency of the sacrificial layer 17 is greatly improved, the process difficulty of the capacitance dielectric layer and the upper electrode 16 is reduced, the process is uniformly carried out, the film forming efficiency is effectively improved, and the performance of the capacitor and the semiconductor device is improved.

The embodiment provides a preparation method of a semiconductor device, which comprises the following steps: providing a substrate 11; forming a sacrificial layer 17 over the substrate 11; forming a support layer 13 over the sacrificial layer 17; forming a plurality of lower electrode openings 18 penetrating the support layer 13 and the sacrificial layer 17 and arranged at intervals; forming a plurality of lower electrodes 12 within the plurality of lower electrode openings 18; a plurality of openings 14 penetrating the support layer 13 and provided at intervals; wherein each opening 14 is in contact with a plurality of lower electrodes 12, and the total area of the overlapping portions of the cross section of at least one lower electrode 12 and the cross section of the opening 14 is more than 70% of the cross section area of a single lower electrode 12; the sacrificial layer 17 is removed. Even if the total area of the overlapped portion of the cross section of one lower electrode 12 and the cross section of the opening 14 is larger than 70% of the cross section area of a single lower electrode 12, that is, the area of the portion of the lower electrode 12 in contact with the supporting layer 13 is small, the lower electrode 12 will not collapse, the opening 14 can expose most of the surface of the lower electrode 12, and the process difficulty of the capacitor dielectric layer and the upper electrode 16 is greatly reduced on the basis of maintaining the lower electrode 12 not to collapse.

Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising:

2. The semiconductor device according to claim 1, wherein at least one of the lower electrodes is simultaneously in contact with two adjacent opening portions.

3. The semiconductor device according to claim 2, wherein an overlapping portion of a cross section of the two adjacent openings and a cross section of the lower electrode is discontinuous.

4. The semiconductor device according to claim 2, wherein overlapping portions of the cross section of the two adjacent opening portions and the cross section of the lower electrode are continuous.

5. The semiconductor device according to claim 1, wherein the plurality of lower electrodes include a plurality of first lower electrodes and a plurality of second lower electrodes, the plurality of first lower electrodes are arranged in a row, the plurality of second lower electrodes are arranged in a row, the first lower electrodes and the second lower electrodes are alternately arranged in a column direction, and the first lower electrodes and the second lower electrodes are alternately arranged.

6. The semiconductor device according to claim 5, wherein each of the opening portions is in contact with two of the first lower electrodes and two of the second lower electrodes.

7. The semiconductor device according to claim 1, wherein the lower electrode has a cylindrical shape or a columnar shape.

8. The semiconductor device according to claim 1, further comprising:

9. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a sacrificial layer over the substrate;

forming a support layer over the sacrificial layer;

and removing the sacrificial layer.

10. A semiconductor device, comprising:

11. A semiconductor device, comprising:

12. The semiconductor device according to claim 11, wherein an outer side portion of the lower electrode located between the first opening portion and the second opening portion is at least partially in contact with the support layer.

13. The semiconductor device according to claim 12, wherein a ratio of a contact length of the outer portion of the lower electrode between the first opening and the second opening to the support layer to a circumference of the outer portion of the lower electrode is less than 30%.

14. The semiconductor device according to claim 11, wherein in each opening, the first opening portion and the second opening portion are provided in alignment along a column direction or a row direction.

15. The semiconductor device according to claim 14, wherein the plurality of openings are arranged in a row.

16. The semiconductor device according to claim 15, wherein two adjacent rows of the openings are aligned.

17. The semiconductor device of claim 15, wherein adjacent rows of the openings are staggered.

18. The semiconductor device according to claim 16 or 17, wherein a distance between two adjacent rows of the openings is larger than a row pitch of the first lower electrodes or a row pitch of the second lower electrodes.

19. The semiconductor device according to claim 16 or 17, wherein a distance between two adjacent rows of the openings is smaller than or equal to a row pitch of the first lower electrodes or a row pitch of the second lower electrodes.

20. The semiconductor device of claim 15, wherein in each row of the openings, adjacent two of the openings are spaced apart by at least one of the lower electrodes.