CN113204932A

CN113204932A - Advanced cell-aware fault model for yield analysis and physical fault analysis

Info

Publication number: CN113204932A
Application number: CN202110138409.XA
Authority: CN
Inventors: R·郭; B·阿彻
Original assignee: Synopsys Technologies Co Ltd
Current assignee: Synopsys Technologies Co Ltd
Priority date: 2020-01-31
Filing date: 2021-02-01
Publication date: 2021-08-03

Abstract

The application relates to an advanced cell-aware fault model for yield analysis and physical fault analysis. To specifically identify faults within a semiconductor cell, a SPICE netlist associated with a semiconductor cell design is retrieved and one or more transistor characteristics are identified within the SPICE netlist. An advanced cell aware fault model is executed for the semiconductor cells, and one or more fault test methods of the advanced cell aware fault model for cells of the semiconductor chip design return results. The method for identifying faults within the semiconductor cells continues by correlating one or more faults detected as a result of the fault test method with one or more transistor characteristics within the SPICE netlist and generating a user interface for identifying one or more faulty transistors within the semiconductor chip design.

Description

Advanced cell-aware fault model for yield analysis and physical fault analysis

RELATED APPLICATIONS

This patent application claims priority from united states provisional application No. 62/968,810, filed on 31/1/2020, which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to yield analysis concepts related to semiconductor manufacturing.

Background

As semiconductor fabrication technology advances, transistor fabrication processes are becoming more complex and transistor dimensions are continually shrinking. Defects in transistors are becoming increasingly subtle and difficult for yield analysis engineers to identify yield limiting factors. These problems become more prevalent as semiconductor technology and transistor dimensions continue to shrink, for example, to 5nm technology and below.

Defects in a transistor may affect the functionality or performance of the transistor. For example, some defects may cause the transistor to remain in an off state rather than switching between 0 and 1; some other defects may cause excessive leakage and make signal transitions much slower than desired. For yield analysis and physical failure analysis, it has become an important issue to quickly identify the defect location and find the root cause of the transistor defect.

Disclosure of Invention

Discussed herein is a method comprising: identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design; receiving results of one or more fault test models for a unit of the semiconductor chip design, the results generated at one or more output pins of the unit of the semiconductor chip design based at least in part on inputs provided to input pins of the unit of the semiconductor chip design specified by the one or more fault test models, and wherein the one or more fault test models are executed based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design; correlating the detected one or more faults with one or more transistor characteristics within the netlist to identify one or more faulty transistors within the semiconductor chip design based at least in part on the results of the one or more fault test models; and providing, by a processor, a user interface identifying the one or more failed transistors within the semiconductor chip design.

In certain implementations of the method, identifying one or more transistor characteristics comprises: receiving a user input of a transistor characteristic of interest; identifying the transistor characteristics of interest within the netlist associated with the semiconductor chip design; and extracting the transistor characteristics of interest from the netlist associated with the semiconductor chip design. Further, providing the user interface may include: data identifying the location of one or more faults within a cell of a semiconductor chip design is provided within a graphical display that overlays the location of the one or more faults onto a cell layout.

The method may further comprise the steps of: generating at least one user interface that uniquely identifies at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface that uniquely identifies the at least one transistor comprises data extracted from a netlist that uniquely identifies the at least one transistor and data extracted from a netlist that identifies the one or more transistor characteristics. Correlating the detected one or more faults with one or more transistor characteristics within the netlist may comprise looking up results generated at the one or more output pins of the cells of the semiconductor chip design within a data structure that identifies expected outputs of the cells of the semiconductor chip design. In some embodiments, identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design includes: identifying library cells within a semiconductor chip design; and retrieving one or more transistor characteristics of the library element from a memory storage area. The method may additionally comprise: comparing one or more transistor characteristics of the one or more failed transistors to one or more transistor characteristics of other transistors extracted from a netlist associated with a semiconductor chip design; determining whether one or more of the transistor characteristics of the one or more failed transistors match one or more of the transistor characteristics of at least one of the other transistors; upon determining that at least one of the transistor characteristics of the one or more failed transistors matches at least one of the transistor characteristics of the at least one of the other transistors, determining whether one or more faults detected for the one or more failed transistors are shared with the at least one of the other transistors; and upon determining that at least one of the one or more faults is shared with at least one of the other transistors, identifying the at least one of the other transistors as a faulty transistor within the user interface.

Additionally described is a system comprising a memory storing instructions and a processor coupled with the memory and executing instructions that, when executed, cause the processor to: identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design; executing an advanced cell-aware fault model for a semiconductor chip design to provide inputs specified within one or more fault test models to input pins of cells of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within a netlist associated with the semiconductor chip design, and wherein providing the inputs to input pins of a cell causes the cell to generate a result at one or more output pins of the cell; correlating the detected one or more faults with one or more transistor characteristics within a netlist to identify one or more faulty transistors within a semiconductor chip design based at least in part on the results of the one or more fault test models; and providing a user interface identifying the one or more failed transistors within the semiconductor chip design.

For certain implementations of the system, identifying one or more transistor characteristics comprises: receiving a user input of a transistor characteristic of interest; identifying the transistor characteristics of interest within the netlist associated with the semiconductor chip design; and extracting the transistor characteristics of interest from the netlist associated with the semiconductor chip design. In some embodiments, providing a user interface comprises: data identifying the location of one or more faults within a cell of a semiconductor chip design is provided within a graphical display that overlays the location of the one or more faults onto a cell layout. Additionally, the processor may be further configured to generate at least one user interface that uniquely identifies at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface that uniquely identifies the at least one transistor comprises data extracted from the netlist that uniquely identifies the at least one transistor and data extracted from the netlist that identifies the one or more transistor characteristics.

Correlating the detected one or more faults with one or more transistor characteristics within the netlist may include looking up results generated at the one or more output pins of the cells of the semiconductor chip design within a data structure that identifies expected outputs of the cells of the semiconductor chip design.

For a particular system, identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design includes: identifying library cells within a semiconductor chip design; and retrieving one or more transistor characteristics of the library element from a memory storage area. Moreover, the processor may be further configured to determine whether one or more faults detected for the semiconductor chip design are shared with a plurality of transistors within the semiconductor chip design.

Also discussed herein is a non-transitory computer-readable medium comprising stored instructions that, when executed, cause the processor to: identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design; executing an advanced cell-aware fault model for a semiconductor chip design to provide inputs specified within one or more fault test models to input pins of cells of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within a netlist associated with the semiconductor chip design, and wherein providing the inputs to input pins of a cell causes the cell to generate a result at one or more output pins of the cell; correlating the detected one or more faults with one or more transistor characteristics within a netlist to identify one or more faulty transistors within a semiconductor chip design based at least in part on the results of the one or more fault test models; and providing a user interface that identifies the one or more failed transistors within the semiconductor chip design.

In certain implementations, identifying one or more transistor characteristics includes: receiving a user input of a transistor characteristic of interest; identifying the transistor characteristics of interest within the netlist associated with the semiconductor chip design; and extracting the transistor characteristics of interest from the netlist associated with the semiconductor chip design. Providing a user interface may include: data identifying the location of one or more faults within a cell of a semiconductor chip design is provided within a graphical display that overlays the location of the one or more faults onto a cell layout.

Particular implementations of a non-transitory computer-readable medium further include stored instructions that, when executed by a processor, cause the processor to generate at least one user interface that uniquely identifies at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface that uniquely identifies the at least one transistor includes data extracted from the netlist that uniquely identifies the at least one transistor and data extracted from the netlist that identifies the one or more transistor characteristics. In some implementations, correlating the detected one or more faults with one or more transistor characteristics within the netlist includes looking up results generated at the one or more output pins of the cells of the semiconductor chip design within a data structure that identifies expected outputs of the cells of the semiconductor chip design. For a particular implementation, identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design includes: identifying library cells within a semiconductor chip design; and retrieving one or more transistor characteristics of the library element from a memory storage area.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the disclosure. The drawings are intended to provide an understanding and appreciation for the embodiments of the disclosure, and are not intended to limit the scope of the disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

FIG. 1 is a flow diagram illustrating example operations of an advanced cell aware fault model.

FIG. 2 shows an example SPICE netlist for a semiconductor chip design.

FIG. 3 illustrates parameters of an example fault test model.

Fig. 4 illustrates an example user interface for providing information regarding a fault detected within a semiconductor unit.

Fig. 5 depicts a flow diagram of various processes used during the design and manufacture of integrated circuits according to some embodiments of the present disclosure.

FIG. 6 depicts an abstract diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

Aspects of the present disclosure relate to advanced cell-aware fault models for yield analysis and physical fault analysis. The described aspects augment cell-aware fault modeling for semiconductor manufacturing with detailed transistor physical features that can be identified and extracted from the SPICE netlist. By utilizing data of detailed transistor physical characteristics, the cell-aware fault modeling process predicts how a properly functioning cell should operate and, for a number of possible types of malfunctions, how a malfunctioning cell will operate. The method thereby enables the detection of faulty transistors within a physical semiconductor chip. Advanced cell-aware fault models exhibit their benefits of helping yield analysis and physical fault analysis engineers quickly identify transistor defects as a yield limiting factor.

An advanced cell-aware fault model 100 that takes into account physical characteristics of transistors and a method of implementing the same are discussed herein. Advanced cell-aware fault model 100, when executed, identifies and extracts data from the SPICE netlist that is indicative of characteristics of transistors within the cell design, such as physical features of transistors within the cell design. The identified and extracted data enables the advanced cell-aware fault model 100 to predict how a cell should operate with proper functionality, and to predict how a particular malfunctioning transistor may affect the functionality of the overall cell design. Transistor characteristics for extraction may be identified based on user-specified data indicative of various parameters, based on automated configurations used to identify feature-specific data within the SPICE netlist (e.g., based on a generated database, and/or based on results of machine-learning-based analysis of data reflecting historical cell designs trained to identify defects within a particular cell), and so forth. The extracted data indicative of the physical characteristics of the transistors is used in logic diagnostics to identify candidate defects as specific transistors or specific regions within the cell design. Based on the physical characteristics of the diagnostic candidates, yield analysis and physical failure analysis engineers may quickly identify the location and root cause of systematic defects that affect product yield. Thus, the use of the advanced cell-aware fault model 100 enables the identification and eventual resolution of systematic defects within a cell, such as defects attributable to a single transistor, a single type of transistor (even if multiple individual transistors are contemplated), or within a particular region of a cell, with reduced use of processing resources for defect analysis, as exhaustive testing criteria that may involve redundant or inefficient testing strategies need not be performed to specifically identify those systematic defects. Furthermore, because the failure test model does not require very detailed test guidelines to accurately and precisely identify the root cause of defects within the cells, production yield may increase over time as the completion of the cell failure analysis may require a shorter time.

Many modern SOC (system on chip) designs are based on standard library cells. Failures within these standard library cells are often identified at cell boundary pins. For example, "fixed" fault models (e.g., identifying defects that do not allow a transistor to change output values) and "transition fault" models (e.g., identifying transition time faults) on the cell pins have detected most defects within the library cells. However, as transistor sizes continue to decrease and standard library cells continue to increase in complexity, detection of particular faults within standard library cells based on boundary pin analysis becomes more difficult.

Advanced cell-aware testing, which utilizes characteristics of physical transistors within standard library cells to generate failure test models for predicting failure behavior of overall library cells based on certain dysfunctional transistors, may be utilized to identify and/or target defects within standard library cells, even as the size of library cells decreases and the complexity of those library cells increases. The cell-aware test method and model are generated with an advanced cell-aware fault model. Once the cell-aware fault model is generated, the cell-aware fault model may be used in a fault test model generation process to target defects inside a complex cell.

The advanced cell aware fault model 100 contains defect data that indicates the behavior of a particular defect within a library cell. The defect data contains identification data that can be used to identify the particular defect to which the defect data applies. The defect data for a particular defect also identifies the standard library cell to which it applies, the transistor (or transistors) within the standard library cell to which it applies (e.g., based on data uniquely identifying the transistor (or transistors) extracted from the SPICE netlist of the cell design), the type of defect for the transistor (or transistors), and data indicative of the behavior of the standard library cell when the particular transistor (or transistors) is malfunctioning based on the identified type of defect. For example, the defect data identifies input pin values that are used to distinguish between non-defective cells and defective affected cells. Defects are simulated using a SPICE simulator, and their behavior is captured and stored as part of the defect data in a cell-aware fault model file. The stored defect data is utilized to generate a fault test model, such as via an input/output truth table (e.g., TestMax ATPG tool from Synopsys) to generate a test pattern that targets the behavior of defects (e.g., by generating pin-input combinations that can be used to distinguish between properly and improperly functioning transistors). These fault test models are implemented by providing inputs to the input pins of the cells according to an input-output truth table, and receiving results of the fault test models at the output pins of the cells, which may be compared against expected results within the identified input-output truth table to identify the root cause of the defect. The defect data also directs a logic diagnostic tool (e.g., TestMax diagnostics) to diagnose the failed chip by identifying the type of defect and the location of the defect within the failed chip. The location of the defect may be specified via a generated graphical display, such as the example graphical display 402 reflected in fig. 4 and discussed in more detail herein.

Aspects of the present disclosure relate to an advanced cell-aware fault model 100 that identifies and describes transistor defects within standard library cells, thereby enabling systematic defects within cells that reduce manufacturing yield to be remedied with minimal processing resource utilization for testing the cells and identifying the defects. Cell-aware fault model 100 contains transistor characteristics that identify detailed transistor physical characteristics associated with a particular defect, which correlation is reflected in the input-output truth table of standard library cells that distinguish between properly functioning and improperly functioning cell designs, and is used to distinguish the location of the defect within an improperly functioning cell design. These physical features may be identified and extracted from the SPICE netlist description of the library element, for example, via text-based extraction techniques for identifying relevant text and for extracting relevant text of the SPICE netlist reflected as a text file. Detailed transistor physical characteristics reflected in the advanced cell-aware fault model 100 are used in logic diagnostics (e.g., TestMax diagnostics from Synopsys) and can effectively identify the root cause of a fault within an identified defective cell.

Semiconductor fabrication technology has evolved from planar FETs (field effect transistors) to finfets, and is now evolving to either gate-around (GAA) FETs or MBCFETs (multi-bridge channel field effect transistors) of 5nm and below. As each generation of technology advances, transistor construction becomes more complex. Defects with respect to transistors have affected the functionality, drive strength or leakage of the transistors.

During technology development or product yield ramp-up, manufacturers or fabless design companies need to quickly identify yield limiting factors for cell designs. Fault model-based logic diagnostics can facilitate defect localization for yield analysis and physical analysis. The specific fault model may include a fixed fault model and a transition fault model.

The advanced cell aware fault model 100 of some embodiments contains fault data that indicates the behavior of the fault. For example, defect data for a particular defect contains input pin values that distinguish between different responses between non-defective cells and defective affected cells. The captured defect behavior is used for fault test model generation to generate test patterns that accurately target the defect behavior, and/or to diagnose a failing chip, such as by supplementing data utilized by logic diagnostic tools (e.g., TestMax diagnostics from Synopsys).

The advanced cell aware fault model 100 contains defect data such as characteristics of physical information of a cell defect. For example, the advanced cell-aware fault model 100 generates data defining bounding boxes around the defects (the bounding boxes are visually reflected via a graphical display, such as the example graphical display 402 reflected in fig. 4), and data identifying layers of the defects in order to identify locations of the defects within the cells. Advanced cell-aware fault model 100 augments transistor characteristics of identified cell defects with detailed physical features of the transistors extracted from the SPICE netlist of the cell. The extracted physical features are used in logical diagnostic reports and/or fed to a yield analysis tool to quickly identify yield limiting factors as discussed herein.

FIG. 1 illustrates an example flow chart showing steps for constructing and executing an example advanced cell aware fault model 100. Advanced cell-aware fault model 100 identifies and extracts transistor physical features from the SPICE netlist as indicated at

block

101 and 102 of fig. 1 (example SPICE netlist 200 is reflected in fig. 2). Data indicative of the transistor physical features may be identified and extracted based at least in part on user input identifying particular parameters of interest and/or automatically identified parameters (e.g., generated via a computing system based at least in part on analysis of various SPICE netlists, etc.). In addition to identifying the specific parameters of each transistor, data extraction additionally identifies and extracts data that uniquely identifies each transistor (e.g., such as the location of the cell and the transistors within the SPICE netlist, or some other data that uniquely distinguishes each transistor from other transistors within the cell and as reflected within the SPICE netlist). As just one example, data extracted from the SPICE netlist may be automatically identified as being related to a particular defect within an identified cell. The SPICE netlist may be provided as a text file (e.g., as shown in the example of fig. 2), and the extraction of these features may include text recognition and extraction of text strings identified as being relevant to uniquely identifying particular transistors during later analysis and/or identified as being reflected within the SPICE netlist in relation to defect recognition within a cell. For each transistor instance, the SPICE netlist contains data identifying the transistor instance, as well as a list of parameters associated with the transistor instance and their corresponding values. These parameters are related to the physical characteristics of each transistor instance in the cell layout. Different instances of the same type of transistor may have the same value for some parameters, but they may have different values for other parameters. The difference in values shows different physical characteristics of each individual transistor, which affect the functionality of the transistors within the cell layout. An example of the data content of the SPICE netlist is reflected in the figure, with individual parameters emphasized. Referring to FIG. 2, which illustrates a fragment of a SPICE netlist 200 of three transistor instance items, data uniquely identifying each transistor instance item is identified (dashed circles denoted 201 in the illustration of FIG. 2) and extracted, and individual parameters determined to be relevant to defect detection (e.g., based on manual identification and/or automatic identification) are similarly identified (solid circles denoted 202 in the illustration of FIG. 2) and extracted. As just one example, text-based data identification and extraction continues through an advanced cell-aware fault model that identifies a particular text string reflected within a memory storage region associated with the advanced cell-aware fault model 100 as relevant to uniquely identifying a particular transistor and/or distinguishing defects. Related text strings within the SPICE netlist and adjacent text indicating values associated with those related text strings (e.g., a defined number of characters or text between the identified related text strings and delimiters within the text) are extracted for further analysis.

The following is an example description of several transistors in the SPICE netlist file (example data is also shown in fig. 2):

XMPA1 I1:F1109 A1:F1108 VDD:F1107 VBP pch_svt_mac ad＝0.00203p as＝0.00406p

+dfm_flag＝1edgeflag＝0l＝0.02u matchingflag＝0nfin＝2nrd＝0nrs＝0ojh＝0

+pd＝0.128u ploda1＝2e-08 ploda2＝0 ploda3＝0 plodb1＝0 plodb2＝0 plodb3＝0

+…

+spobl1＝3.26e-07 spobl2＝1.39e-07 spobr1＝1.39e-07 spobr2＝3.26e-07 nfin_a_ddb＝1 nfin_b_ddb＝0

+spot＝4.3e-08 spotl1＝4.3e-08 spotl2＝4.3e-08 spotr1＝4.3e-08 spotr2＝4.3e-08 nfin_a_sdb2＝3nfin_b_sdb2＝2$angle＝90

XMPA2 I1:F1109 A2:F1112 VDD:F1113 VBP pch_svt_mac ad＝0.00203p as＝0.00406p

+pd＝0.128u ploda1＝0 ploda2＝0 ploda3＝0 plodb1＝2e-08 plodb2＝0 plodb3＝0

+…

+spob＝3.26e-07 spobl1＝1.39e-07 spobl2＝1.39e-07 spobr1＝3.26e-07 nfin_a_ddb＝0 nfin_b_ddb＝1

+spobr2＝1.39e-07 spot＝4.3e-08 spotl1＝4.3e-08 spotl2＝4.3e-08 spotr1＝4.3e-08

+spotr2＝4.3e-08nfin_a_sdb2＝3nfin_b_sdb2＝3$angle＝90

XMPI1 X:F1115 I1:F1116 VDD:F1117 VBP pch_svt_mac ad＝0.01078p as＝0.01078p

+dfm_flag＝1edgeflag＝0l＝0.02u matchingflag＝0nfin＝4nrd＝0nrs＝0ojh＝0

+pd＝0.448u ploda1＝0 ploda2＝0 ploda3＝0 plodb1＝0 plodb2＝0 plodb3＝0 ppitch＝0

+…

+sodxb4＝5.92454e-08 sodyb＝1.34e-07 sodyt＝1.70115e-07 spob＝3.26e-07 nfin_a_ddb＝0nfin_b_ddb＝0

+spobl1＝4.3e-08 spobl2＝3.26e-07 spobr1＝4.3e-08 spobr2＝4.3e-08 spot＝4.3e-08

+spotl1＝4.3e-08 spotl2＝4.3e-08 spotr1＝4.3e-08 spotr2＝4.3e-08 nfin_a_sdb2＝3 nfin_b_sdb2＝2$angle＝90

in the above example, there are three transistors of the same type "pch svt mac". For the parameter "nfin" (which specifies the number of fins per metal gate finger of the transistor and varies from transistor to transistor), the transistors have values of 2, and 4, respectively; thereby reflecting only one example parameter that varies between transistors and which in the example shown is determined to indicate the presence of a defect within the operation of the transistor). The differences in the nfin parameters between transistors cause the transistors to operate differently under certain conditions, and thus these differences may be utilized by the advanced cell-aware fault model 100 as only one of a plurality of parameters (based on which transistor is defective) that reflect the differences in transistor characteristics that result in different fault behaviors of the cells. Different values of the nfin parameter represent different physical characteristics of each of these transistors. For another parameter "angle" (which is also indicated as being related to the presence of defects in the fault test model determination cells, as reflected by the illustrated example SPICE netlist 200 of fig. 2), all three transistors have the same value of 90. It should be noted that there are several parameters in the transistor description of SPICE net list, but some parameters may not be relevant to accurately identify the underlying cause of a defect within a cell, and thus the advanced cell-aware fault model 100 identifies and extracts only those parameters relevant to distinguishing the type of defect, in order to minimize the processing resources required to analyze all known parameters of all transistors within a cell. Each parameter shows a different aspect of the physical layout. By examining these parameters, embodiments select and extract transistor characteristics, such as transistor models, parameters, and values thereof, that are believed to be relevant to distinguishing the type and/or location of defects within a cell. These extracted transistor characteristics can be used to construct a fault test model to distinguish between properly functioning transistors and malfunctioning transistors within the cell. It should be understood that certain parameters may be considered relevant to identifying defect locations within one library cell design, but may not be relevant to identifying defect locations within another library cell design. As an example, identifying and extracting transistor characteristics that are considered relevant for defect identification and localization may be a two-step process:

step 1: transistor characteristics are identified (reflected at block 101 of fig. 1). The advanced cell aware fault model 100 includes generation tools to automatically identify and extract relevant transistor characteristics. These transistor characteristics are identified as being relevant and extracted for individual transistors within the cell to be analyzed for possible failure and/or yield limiting factors. The generation tool of the advanced cell-aware fault model 100 extracts specific transistor characteristics that are manually identified by a user, and/or the generation tool of the advanced cell-aware fault model 100 extracts specific transistor characteristics that are automatically identified as being relevant to distinguishing between properly functioning transistors and malfunctioning transistors (e.g., based on a library of data that correlates the specific transistor characteristics with defect identification). If the user knows which transistor characteristics are of interest, the user may input (e.g., via user input) these characteristics to the advanced cell aware fault model 100 for use by the generation tool, and the generation tool then focuses on the user specified transistor characteristics. In many cases, the user may not be aware of the exact transistor characteristics of interest, or there may be too many parameters in the SPICE netlist for the user to manually select the particular transistor characteristics of interest. In this case, the cell-aware fault test model generation tool investigates all transistors in the SPICE netlist file and compares the parameters of all transistors and their values. These parameters may be classified or grouped based on whether all transistors of the same type have the same value or different values. The similarity (or non-similarity) of these physical feature values can be used to enhance the cell-aware fault model.

Step 2: the physical features are extracted and a physical feature data structure (e.g., a data table) is created to be included in the unit-aware fault test model file (reflected within block 102 of fig. 1). Once the physical features are identified (or specified by the user), the unit-aware fault test model generation tool extracts the parameters and their corresponding values and adds this information to the unit-aware fault model file. The physical layout data structure is then constructed to contain characteristics of the physical data indicative of all of the transistors, as reflected at block 103. The enhanced cell-aware fault model 100 then, in some examples, generates a logical diagnostic report (as shown at block 104) that provides an indication of whether the identified parameters indicate a possible fault (e.g., based on a comparison with a library of data used to identify faults of the advanced cell-aware fault model), and/or provides the generated physical layout data structure to a yield analysis tool to identify systematic faults within the cells, as reflected at block 105. For example, when the physical layout data structure is utilized via a yield analysis tool, the enhanced cell-aware fault model 100 generates one or more cell input-output truth tables (as reflected within block 106 of fig. 1) that accurately identify possible defects within the cells to be used as test criteria for the fault test model based at least in part on the physical layout data structure. Because the physical characteristics of the transistors indicate how the transistors will react to particular inputs, enhanced cell-aware fault model 100 predicts how an individual faulty transistor affects the operation of even a complex cell based on the physical characteristics of the individual transistor as reflected within the input-output truth table generated and used as the test criteria for the fault test model. Thus, the truth table specifies the expected outputs (detectable at the cell output pins) for a given set of inputs (provided at the cell input pins). For example, for a given input to an overall cell, the advanced cell-aware fault model 100 predicts how the input will flow with signals through and between various components (e.g., transistors) of the cell (e.g., with a signal flowing from one transistor to another, with the input to a first transistor becoming the output of the first transistor used as an input to a second transistor) for a cell that is functioning properly. Advanced cell-aware fault model 100 provides the inputs of the input-output truth table to the cells as part of the fault test model, as indicated at block 107, and monitors the outputs of the cells based on the inputs provided according to the test criteria and the input-output truth table of the fault test model, as reflected within block 108. Upon identifying deviations from the expected output for a given cell, the advanced cell-aware fault model 100 identifies the fault within the cell, for example, by generating a fault report containing the identification of the fault, as reflected at block 109. Specific defects are accurately identified so as to indicate areas within the cell (e.g., at specific transistor locations), thereby enabling downstream processes and/or cell designers utilizing advanced cell-aware fault models to remedy the identified defects. Further, as reflected herein, the defect report may include a graphical display providing a visual overlay over the displayed indication of the cell layout, such that a visual indication of the location of the defect within the cell layout is provided to the user. In some embodiments, the graphical display may be interactive, enabling a user to selectively zoom in/out of the layout for additional detail regarding the location of the detected defect. Because the truth table is specifically generated to identify a particular fault, the advanced cell-aware fault model 100 does not have to perform exhaustive testing of all possible inputs to the cells to identify a particular source of a defect, thereby reducing the amount of processing resources necessary for defect identification. Similarly, with a truth table specifically provided for precise adaptation to identify a particular fault within a library cell, the precise location of the fault within the cell can be precisely identified without requiring each transistor within the cell to be individually analyzed to confidently determine the location of the fault. Specific information about defects is determined and included within a defect report by identifying similarities between defects of a particular cell and defects detected for other cells that share one or more physical characteristics (e.g., portions of a transistor layout of a cell). For example, based on determined similarities between defects detected for different cells and/or defects detected for different input combinations of individual cells, advanced cell-aware fault model 100 correlates particular defects with particular physical characteristics of the cells, thereby providing a particular indication of particular faulty portions of the cells.

Based on the predicted outputs of the various library cell designs and the determined similarities between the cell designs and the detected defects, the cell input-output truth table identifies pin inputs of test criteria of a fault test model that differentiate cells that properly function from cells that do not properly function, wherein a particular combination of inputs within the test criteria of the fault test model is utilized to differentiate particular fault types. As a simplified example, the input-output truth table of the fault test model may specify that an input "1" on the first input pin should produce an output "1" on the first output pin. If the unit under test produces an output of "0" on the first output pin, this output may indicate a fault. A combination of multiple input-output combinations is then utilized to specifically identify the source of the fault, and thereby differentiate among multiple possible faults to identify a particular fault type for the cell, which is then reflected within the defect report. According to the example above, where the presence of a fault in a cell has been identified (based on an incorrect output on a first output pin), the input-output table is referenced to specify an input "0" on a second input pin as part of the test criteria of the fault test model, a corresponding expected output on the second output pin is "0" for a first fault type, and an expected output on the same second output pin is "1" for a second fault type. When considering additional combinations of expected inputs and outputs, advanced cell-aware fault model 100 is able to distinguish between multiple fault types within a complex cell, thereby enabling the advanced cell-aware fault model to specifically identify faulty transistors within the complex cell and reflect the specifically identified faulty transistors within a defect report (e.g., via data extracted from SPICE's that uniquely identifies the faulty transistors).

As mentioned above, the extracted physical information may be provided in a data structure having a table format, such as within a table of a unit-aware fault model file. An example cell-aware fault model 100 with physical features extracted from the SPICE netlist is shown below (this data is also represented by the example depicted in fig. 3):

Transistor_and_subcell_layout_data:

-[Table,Device]

-[Name,Type,llx,lly,urx,ury,layers,Active_Device, Related_Pin,device_model,device_feature]

-[XMPA1,transistor,80,432,100,432,pgate_mac tpdiff,XMPA1,,pch_svt_mac, nfin＝2 nfin_b_sdb2＝2 angle＝90]

-[XMPA2,transistor,170,432,190,432,pgate_mac tpdiff,XMPA2,,pch_svt_mac, nfin＝2 nfin_b_sdb2＝3 angle＝90]

-[XMPI1,transistor,80,144,100,144,ngate_mac tndiff,XMPI1,,pch_svt_mac, nfin＝4 nfin_b_sdb2＝2 angle＝90]

in the above example, the first row shows the physical characteristics extracted by the generation tool of the advanced cell-aware fault model 100, and each subsequent row shows the characteristic values for each transistor. Each column corresponds to a physical feature of the transistor, e.g., column "device _ model" shows the type of transistor, and column "device _ feature" shows the physical feature (e.g., number of fins, transistor angle, etc.) of each transistor. The data in this data structure may be later included in a logical diagnostic report or imported to a yield analysis tool to identify defects within the cells.

In some embodiments, the extracted data may be used to identify similarities (or non-similarities) between transistors included within the design. For example, upon identifying an error or failure within a design, such as may be attributable to a failed transistor, identifying similarities and/or non-similarities between transistors includes determining whether one or more transistor characteristics match across multiple transistors (e.g., one or more parameters are shared between multiple transistors). The identified similarities and/or dissimilarities between transistor parameters may be used to determine whether an identified fault is shared between all transistors having a given parameter, or whether a fault is isolated to a single transistor (or multiple unrelated transistors). For example, a particular fault may be indicated as being caused by a particular transistor parameter (or a particular combination of transistor parameters) such that the determination of whether the particular fault is shared among the plurality of parameters includes identifying all other transistors sharing the parameter with the faulty transistor identified as being related to the transistor fault. When a faulty transistor is displayed within the graphical display, the graphical display is then updated to reflect the location (and/or other characteristics) of those transistors identified as sharing parameters with the initially identified faulty transistor.

Furthermore, data indicative of various transistor parameters may be shared with (e.g., performed via shared processing resources and/or via a separate computing entity) the diagnostic and/or yield explorer system 401 as reflected in fig. 4, which may provide additional data regarding yield and/or detected faults within the cells, such that the additional transistor parameters may supplement the data provided by such systems (e.g., as reflected in fig. 4), and such that yield analysis may be used to reflect improved yield resulting from implementation of advanced cell-aware fault modeling. In some embodiments, these additional systems may be configured to utilize data indicative of various physical parameters to modify the displayed output (e.g., by showing identified similar transistors within a graphical display, by labeling the displayed transistors within the display, etc.). An example graphical display showing a graphical overlay indicating the location within the graphical illustration of the cell layout of various defects detected via application of the advanced cell aware fault model is shown at fig. 4.

The advanced cell aware fault model 100 may be utilized as part of the overall cell design and fabrication process. For example, after constructing a netlist for a new cell design, the advanced cell-aware fault model identifies and extracts transistor characteristic data for transistors (e.g., all transistors within the cell design) within the cell design. Based on the physical characteristics of the transistors as identified within the transistor characteristic data, the advanced cell-aware fault model generates an input-output data table or other such data structure that identifies how a particular transistor affects the operation of the overall cell in the event of a fault. The advanced cell aware fault model identifies specific input combinations within the input-output data table that can be used to distinguish between normally operating cells and malfunctioning cells and to distinguish between types of faults within the cells, which enables the advanced cell aware fault model to specifically identify individual faulty transistors within the constructed cells.

During testing of the constructed cells (e.g., after fabrication), and/or when modeling the expected operation of the cells, advanced cell-aware fault model 100 executes one or more fault test models that include specifically identified combinations of inputs to the cells to determine whether the cells are functioning properly, and to distinguish between various fault types, in order to enable the advanced cell-aware fault model to specifically identify faulty transistors within the fabricated (or simulated) cells.

By executing the one or more fault test models, the advanced cell aware fault model 100 causes the cell to generate an output at an output pin of the cell. Advanced cell aware fault model 100 then compares the generated outputs against data stored within an input-output data table for the data inputs utilized to see if the outputs of the fault test model indicate a faulty transistor, and determines which transistor(s) within the cell are faulty by correlating the outputs received from the cell for a given set of inputs with the corresponding entries within the input-output data table that identify the particular fault of the cell.

The input-output data table may be generated separately for each semiconductor chip design. For example, an input-output table may be generated for each cell within a semiconductor chip design as part of the semiconductor chip design process. However, the input-output data tables for the standard library cells may be stored in memory for retrieval when constructing a failure test model for a newly developed semiconductor chip design that includes one or more standard library cells. During design of a semiconductor chip, standard library cells included within the semiconductor chip design are identified, and the advanced cell-aware fault model retrieves relevant input-output data tables for the standard library cells, and then utilizes the retrieved input-output data tables during testing of the semiconductor chip design.

FIG. 5 illustrates an example set of processes 700 used during design, inspection, and fabrication of an article of manufacture, such as an integrated circuit, for transforming and inspecting design data and instructions representing the integrated circuit. Each of these processes may be constructed and implemented as a plurality of modules or operations. The term "EDA" stands for the term "electronic design automation". These processes begin with the creation of a product idea 710 with information provided by a designer that is transformed to create an article of manufacture using a set of EDA processes 712. When the design is complete, the design is taped out 734, at which point the work (e.g., geometric versions) of the integrated circuit is sent to a fabrication facility to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are fabricated 736 and a packaging and assembly process 738 is performed to produce a finished integrated circuit 740.

The specifications of a circuit or electronic structure may vary from a low-level transistor material layout to a high-level description language. High-level abstraction can be used to design circuits and systems using hardware description languages ("HDL"), such as VHDL, Verilog, systemveilog, SystemC, MyHDL, or OpenVera. The HDL description may be transformed into a logic level register transfer level ("RTL") description, a gate level description, a layout level description, or a mask level description. Each lower level of abstraction, which is a less abstract description, adds more useful details to the design description, such as more details of the modules that comprise the description. The lower level of abstraction, which is a less abstract description, may be computer generated, derived from a design library, or created by another design automation process. An example of a specification language at the lower abstraction language level for specifying a more detailed description is SPICE, which is used for detailed description of circuits with many analog components. The description at each abstraction level is enabled for use by a respective tool (e.g., formal verification tool) for that layer. The design process may use the sequence depicted in fig. 5. The described process is enabled by EDA products (or tools).

During system design 714, the functionality of the integrated circuit to be fabricated is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and/or code lines), and cost reduction. The partitioning of the design into different types of modules or components may be done at this stage.

During logic design and functional verification 716, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy. For example, components of a circuit may be inspected to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification may use simulators and other programs, such as test bench generators, static HDL checkers, and formal checkers. In some embodiments, special systems called components of "emulators" or "prototype systems" are used to accelerate functional verification.

During synthesis and testing of design 718, the HDL code is transformed into a netlist. In some embodiments, the netlist may be a curved structure, where the edges of the curved structure represent components of the circuit, and where the nodes of the curved structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by EDA products to verify that the integrated circuit, when manufactured, works according to a specified design. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, finished integrated circuits may be tested to verify that the integrated circuits meet the requirements of the specification.

During netlist verification 720, the netlist is checked for compatibility with timing constraints and for correspondence with the HDL code. During design planning 722, an overall plan view of the integrated circuit is constructed and analyzed for timing and top level layout.

During layout or physical implementation 724, physical placement (positioning of circuit components such as transistors or capacitors) and routing (circuit components connected by multiple conductors) is performed, and selection of cells from the library to enable particular logic functions may be performed. As used herein, the term "cell" may designate a set of transistors, other components, AND interconnects that provide a boolean logic function (e.g., AND, OR, NOT, XOR) OR a storage function (e.g., flip-flop OR latch). As used herein, a circuit "block" may refer to two or more cells. Both the cells and the circuit blocks may be referred to as modules or components and are enabled as both physical structures and analog structures. Parameters, such as dimensions, are specified (based on "standard cells") for the selected cells and made accessible in a database for use by the EDA product.

During the analysis and extraction 726, verified circuit functionality is at the layout level, which permits improvements in layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, lithographic constraints, etc., are correct and that the circuitry functionality matches the HDL design specification. During resolution enhancement 730, the geometry of the layout is transformed to improve how the circuit design is fabricated.

During tape-out, data is created for use in producing a photolithographic mask (after applying photolithographic enhancements as appropriate). During mask data preparation 732, the "tape-out" data is used to generate photolithographic masks used to produce finished integrated circuits.

The storage subsystem of a computer system (e.g., computer system 900 of FIG. 6) may be used to store programs and data structures used by some or all of the EDA products described herein as well as products used to develop libraries and cells of physical and logical designs using libraries.

Fig. 6 illustrates an example machine of a computer system 900 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Additionally, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Example computer system 900 includes a processing device 902, a main memory 904 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM) such as synchronous DRAM (sdram)), a static memory 906 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

The processing device 902 represents one or more processors, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 902 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 902 may be configured to execute the instructions 926 for performing the operations and steps described herein.

Computer system 900 may further include a network interface device 908 to communicate over a network 920. Computer system 900 may also include a video display unit 910 (e.g., a Liquid Crystal Display (LCD) or a Cathode Ray Tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generation device 916 (e.g., a speaker), the graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

The data storage 918 may include a machine-readable storage medium 924 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methodologies or functions described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and/or within the processing device 902 during execution thereof by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media.

In some embodiments, the instructions 926 include instructions to implement the functionality corresponding to the present disclosure. While the machine-readable storage medium 924 is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and processing device 902 to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations that produce a desired result. The operations are those requiring physical manipulations of physical quantities. These quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, specific terms refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and so forth.

In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular, more than one element may be depicted in the figures, and similar elements are labeled with similar reference numerals. The disclosure and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method, comprising:

identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design;

receiving results of one or more fault test models for a unit of the semiconductor chip design, the results generated at one or more output pins of the unit of the semiconductor chip design based at least in part on inputs provided to input pins of the unit of the semiconductor chip design specified by the one or more fault test models, and wherein the one or more fault test models are executed based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design;

correlating the detected one or more faults with one or more transistor characteristics within the netlist to identify one or more faulty transistors within the semiconductor chip design based at least in part on the results of the one or more fault test models; and

providing, by a processor, a user interface identifying the one or more failed transistors within the semiconductor chip design.

2. The method of claim 1, wherein identifying one or more transistor characteristics comprises:

receiving a user input of a transistor characteristic of interest;

identifying the transistor characteristics of interest within the netlist associated with the semiconductor chip design; and

extracting the transistor characteristics of interest from the netlist associated with the semiconductor chip design.

3. The method of claim 1, wherein providing a user interface comprises: providing data identifying locations of one or more faults within the cells of the semiconductor chip design within a graphical display that overlays the locations of the one or more faults onto a cell layout.

4. The method of claim 1, further comprising:

generating at least one user interface that uniquely identifies at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface that uniquely identifies the at least one transistor comprises data extracted from the netlist that uniquely identifies the at least one transistor and data extracted from the netlist that identifies the one or more transistor characteristics.

5. The method of claim 1, wherein correlating one or more detected faults with one or more transistor characteristics within the netlist comprises looking up results generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying expected outputs of the cell of the semiconductor chip design.

6. The method of claim 1, wherein identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design comprises:

identifying a library element within the semiconductor chip design; and

one or more transistor characteristics of the library element are retrieved from a memory storage area.

7. The method of claim 1, further comprising:

comparing one or more transistor characteristics of the one or more failed transistors with one or more transistor characteristics of other transistors extracted from the netlist associated with the semiconductor chip design;

determining whether one or more of the transistor characteristics of the one or more failed transistors match one or more of the transistor characteristics of at least one of the other transistors;

upon determining that at least one of the transistor characteristics of the one or more failed transistors matches at least one of the transistor characteristics of the at least one of the other transistors, determining whether one or more failures detected for the one or more failed transistors are shared with the at least one of the other transistors; and

upon determining that at least one of the one or more faults is shared with at least one of the other transistors, identifying the at least one of the other transistors as a faulty transistor within the user interface.

8. A system, comprising:

a memory storing instructions; and

a processor coupled with the memory and executing instructions that, when executed, cause the processor to:

executing an advanced cell-aware fault model for the semiconductor chip design to provide inputs specified within one or more fault test models to input pins of cells of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design, and wherein providing the inputs to input pins of the cells causes the cells to generate results at one or more output pins of the cells;

providing a user interface that identifies the one or more failed transistors within the semiconductor chip design.

9. The system of claim 8, wherein identifying one or more transistor characteristics comprises:

receiving a user input of a transistor characteristic of interest;

10. The system of claim 8, wherein providing a user interface comprises: providing data identifying locations of one or more faults within the cells of the semiconductor chip design within a graphical display that overlays the locations of the one or more faults onto a cell layout.

11. The system of claim 8, wherein the processor is further configured to generate at least one user interface that uniquely identifies at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface that uniquely identifies the at least one transistor comprises data extracted from the netlist that uniquely identifies the at least one transistor and data extracted from the netlist that identifies the one or more transistor characteristics.

12. The system of claim 8, wherein correlating one or more detected faults with one or more transistor characteristics within the netlist comprises looking up results generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying expected outputs of the cell of the semiconductor chip design.

13. The system of claim 8, wherein identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design comprises:

identifying a library element within the semiconductor chip design; and

14. The system of claim 8, wherein the processor is further configured to determine whether one or more faults detected for a semiconductor chip design are shared with a plurality of transistors within the semiconductor chip design.

15. A non-transitory computer readable medium comprising stored instructions that, when executed by a processor, cause the processor to:

16. The non-transitory computer-readable medium of claim 15, wherein identifying one or more transistor characteristics comprises:

receiving a user input of a transistor characteristic of interest;

17. The non-transitory computer-readable medium of claim 15, wherein providing a user interface comprises: providing data identifying locations of one or more faults within the cells of the semiconductor chip design within a graphical display that overlays the locations of the one or more faults onto a cell layout.

18. The non-transitory computer-readable medium of claim 15, further comprising stored instructions that, when executed by a processor, cause the processor to generate at least one user interface that uniquely identifies at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface that uniquely identifies the at least one transistor comprises data extracted from the netlist that uniquely identifies the at least one transistor and data extracted from the netlist that identifies the one or more transistor characteristics.

19. The non-transitory computer-readable medium of claim 15, wherein correlating one or more detected faults with one or more transistor characteristics within the netlist comprises looking up results generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying expected outputs of the cell of the semiconductor chip design.

20. The non-transitory computer-readable medium of claim 15, wherein identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design comprises:

identifying a library element within the semiconductor chip design; and