CN113203758A - In-situ multi-parameter test chip structure for TEM/SEM (transmission electron microscope) and preparation method - Google Patents

In-situ multi-parameter test chip structure for TEM/SEM (transmission electron microscope) and preparation method Download PDF

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CN113203758A
CN113203758A CN202110526897.1A CN202110526897A CN113203758A CN 113203758 A CN113203758 A CN 113203758A CN 202110526897 A CN202110526897 A CN 202110526897A CN 113203758 A CN113203758 A CN 113203758A
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lead
electrode lead
layer
mass block
execution
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CN113203758B (en
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聂萌
黄语恒
尹奎波
陈姝宁
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Southeast University
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N23/00Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
    • G01N23/22Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
    • G01N23/225Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion
    • G01N23/2251Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material using electron or ion using incident electron beams, e.g. scanning electron microscopy [SEM]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N23/00Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
    • G01N23/02Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material
    • G01N23/04Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material and forming images of the material
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N3/00Investigating strength properties of solid materials by application of mechanical stress
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/08Measuring resistance by measuring both voltage and current

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Abstract

The invention discloses an in-situ multi-parameter test chip structure for a TEM/SEM (transmission electron microscope) and a preparation method thereof, wherein a chip functional area comprises a mass block, a heat sink beam, a thermal actuator, an electrostatic actuator, a supporting beam, a lead beam, a sample stage, an insulating layer, an electrode lead pressure welding block and a substrate; the device is integrally in a symmetrical structure, wherein the thermal actuator, the electrostatic actuator, the heat sink beam, the mass block, the support beam, the lead beam and the sample stage are symmetrically distributed along the mass block as a central axis. The device is a dual-drive structure, the drive structures are a thermal actuator and a static actuator respectively, static-dynamic test combination can be carried out, and therefore the test chip has the following functions: quasi-static single-parameter or multi-parameter testing of electrical parameters and mechanical parameters of a sample to be tested; analyzing creep and fatigue characteristics of a sample to be tested under plane stretching; and analyzing the coupling relation rule between the fatigue characteristic of the sample to be tested and the mechanical parameter of the electrical parameter, and analyzing the reliability failure of the sample to be tested.

Description

In-situ multi-parameter test chip structure for TEM/SEM (transmission electron microscope) and preparation method
Technical Field
The invention relates to the technical field of in-situ test chips, in particular to an in-situ multi-parameter test chip for a TEM/SEM (transmission electron microscope) and a preparation method thereof.
Background
Over the past decades, there has been great interest in the mechanical and mechanical properties of low dimensional materials, especially one and two dimensional nanomaterials, which are important fundamental research directions due to their unique properties that are different from bulk materials and the potential to possess unique and customizable physical properties, including various nanotechnology applications, including energy harvesting and storage, nanoelectromechanical systems (NEMS), flexible electronics, and stretchable electronics. In addition, when the characteristic size of the material is reduced to the micro-nano level, the mechanical property of the material is obviously different from that of a macroscopic body material, and the mechanical property of the nano material is closely related to a deformation mechanism of the micro-nano scale. Therefore, the development of a method which can realize in-situ observation of the change of the microstructure of a research material along with static and dynamic mechanical parameters under a TEM/SEM (transmission electron microscope/scanning electron microscope) and at a sub-angstrom, atomic or nano scale and can extract the force-electrical properties of the material has very important significance for improving the reliability of a micro-nano electronic device and promoting the development of related fields.
The force-electricity coupling characteristics under multiple static and dynamic stress loads are closely related to the formation and evolution of the internal structure of the material, but the current related research results are mainly established on independent tests of a large number of static and dynamic loads, and the mechanical characteristics under the multiple stress loads cannot be comprehensively understood. With the rapid development of nano material characterization test and Micro Electro Mechanical System (MEMS) technology, in-situ mechanical loading of nano materials in a transmission electron microscope becomes possible. However, few mechanical testing techniques are currently available for in-situ static and dynamic multiple stress loading under transmission electron microscopy, and reported techniques are generally limited to single-shot loading, or small-stress dynamic loading. Currently, a real-time force-electric coupling test technology which can be used for an in-situ TEM/SEM (transmission electron microscope) and can simultaneously realize large-stress uniaxial tension and high-frequency dynamic loading is not provided.
The existing commercial sample rod on the market is a PI type nano-indentor of Hysitron company, and can realize uniaxial tension and mechanical property test of a material sample, but the experimental instrument is expensive, needs to customize a specific experimental environment and cannot realize multi-physical field integration.
A force-thermal coupling test chip based on a thermal actuator and a heating resistance wire is developed by a university of Beijing industry, Korean-Xiaodong professor topic group, the chip can realize in-situ mechanical uniaxial stretching of a material sample at high temperature, but the chip has larger integral rigidity of the structure, so that the chip influences the accurate measurement of the mechanical property of the material sample in the stretching process, the error of the mechanical property test of the micro-nano material such as Young modulus is larger, and the electrical property of the sample cannot be measured.
The device can realize static and dynamic stress loading tests of the material sample, but the chip preparation process is complex, and the electrical test technology is a two-probe test, so that the influence of contact resistance between a test material and a sample table cannot be eliminated, and the accurate measurement of the electrical characteristics of the material sample in the stretching process is seriously influenced.
The double-inclination transmission electron microscope MEMS sample rod is developed by professor Horacio D.Espenosa of northwest university of America, can realize static mechanical stretching and measurement, can obtain high-resolution imaging of materials through biaxial inclination, and is equipped with a capacitive sensor to automatically detect the stress borne by the materials, but the sample rod is complex in design and cannot carry out dynamic mechanical measurement.
Therefore, the development of an in-situ test chip device based on a TEM/SEM (transmission electron microscope) which can be used for in-situ static-dynamic test of the mechanical-electrical multi-parameter coupling characteristics of a material sample and can be applied in mass production is still one of the problems to be solved in the field.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the in-situ multi-parameter testing chip for the TEM/SEM electron microscope and the preparation method thereof have two mechanical load modes of static state and dynamic state, can realize quasi-static and dynamic multi-parameter testing of the electrical and mechanical parameters of a material sample to be tested, and the coupling relation rule between creep deformation and fatigue and the electrical and mechanical parameters, and realize the reliability failure analysis of the material sample to be tested by static-dynamic testing combination. Meanwhile, a standard micromachining process preparation method for large-scale batch production of the test chip is provided.
The invention relates to an in-situ multi-parameter test chip structure for a TEM/SEM (transmission electron microscope), which comprises an electrostatic actuator, a thermal actuator and an electrode lead; the electrostatic actuator, the thermal actuator and the electrode lead are respectively symmetrical about the same central axis.
The electrostatic actuator is provided with a first sample table, and the first sample table moves along the central axis along with the electrostatic actuator;
the thermal actuator is provided with a second sample table, and the second sample table moves along the central axis along with the thermal actuator;
the first sample table and the second sample table are provided with insulating layers;
the electrode lead comprises a first electrode lead, a second electrode lead, a third electrode lead and a fourth electrode lead, one end of the first electrode lead and one end of the second electrode lead are positioned on the first sample table, and one end of the third electrode lead and one end of the fourth electrode lead are positioned on the second sample table; the other ends of the first electrode lead, the second electrode lead, the third electrode lead and the fourth electrode lead are connected with an external test circuit, and the electrode leads and the external test circuit form a four-probe test circuit.
Furthermore, the external test circuit comprises a voltmeter and a current source, the other ends of the first electrode lead and the third electrode lead are used for connecting the voltmeter, the other ends of the second electrode lead and the fourth electrode lead are used for connecting the current source, and the electrode lead, the voltmeter and the current source form a four-probe test circuit for testing the electrical characteristics of the material sample to be tested.
Compared with the prior art, the invention has the following beneficial effects:
in the driving function, the test chip integrates two driving structures, namely thermal execution driving of high stress load and electrostatic comb actuator driving of high frequency stress load, and the rigidity of the thermal actuator structure is far greater than that of the electrostatic driving structure and a material sample to be tested.
And 2, in the test function, different loads can be sequentially loaded on the same material sample to be tested, and multi-parameter test analysis of the material sample to be tested, such as stress, Young modulus, creep deformation, fatigue property, conductivity and the like, can be realized.
2.1. The method is characterized in that static force loading is carried out under the driving of a thermal actuator with higher rigidity, and quasi-static single-parameter or multi-parameter tests of electrical parameters (conductivity) and mechanical parameters (Young modulus, stress, creep property and the like) of a sample are researched on line.
2.2. Dynamic force is loaded at high frequency under the drive of the static comb tooth actuator with smaller rigidity, and the mechanical and electrical characteristics of the sample are researched on line.
2.3. And (4) researching fatigue characteristics of the high-frequency load after the high-frequency load acts for different time lengths, and analyzing reliability.
2.4. And (4) loading the static force on the sample after the fatigue cycle is completed, and analyzing the mechanical and electrical characteristic coupling rule of the sample under the fatigue characteristic.
3, the defect of single performance of the existing TEM/SEM mechanical test chip is solved, multiple mechanical load and electrical property characterization functions can be provided in a relatively small space of the TEM, the number of electrostatic comb teeth can be properly increased in a relatively large space of the SEM, and a high-frequency and high-stress load mode is realized.
Drawings
FIG. 1 is a diagram illustrating a test chip structure according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the first step of the first embodiment of the present invention.
FIG. 3 is a sectional view showing the structure of the second step of the manufacturing method in the first embodiment of the chip manufacturing method according to the present invention.
FIG. 4 is a sectional view showing the structure of the third step of the manufacturing method in the first embodiment of the chip manufacturing method of the present invention.
FIG. 5 is a cross-sectional view showing the structure of the fourth step of the manufacturing method in the first embodiment of the chip manufacturing method of the present invention.
FIG. 6 is a cross-sectional view showing the structure of the fifth step of the manufacturing method in the first embodiment of the chip manufacturing method of the present invention.
FIG. 7 is a sectional view showing the structure of the sixth step of the manufacturing method in the first embodiment of the chip manufacturing method of the present invention.
FIG. 8 is a sectional view showing the structure of the first step of the manufacturing method in the second embodiment of the chip manufacturing method of the present invention.
FIG. 9 is a sectional view showing the structure of the second step of the manufacturing method in the second embodiment of the chip manufacturing method according to the present invention.
FIG. 10 is a sectional view showing the structure of the third step of the manufacturing method in the second embodiment of the chip manufacturing method of the present invention.
FIG. 11 is a sectional view showing the structure of the fourth step of the manufacturing method in the second embodiment of the chip manufacturing method of the present invention.
FIG. 12 is a cross-sectional view showing the structure of the fifth step of the manufacturing method in the second embodiment of the chip manufacturing method of the present invention.
FIG. 13 is a sectional view showing the structure of the sixth step of the production method in the second embodiment of the production of chips in accordance with the present invention.
FIG. 14 is a sectional view showing the structure of the seventh step of the manufacturing method in the second embodiment of the chip manufacturing method of the present invention.
FIG. 15 is a sectional view showing the structure of the eighth step of the manufacturing method in the second embodiment of the chip manufacturing method of the present invention.
FIG. 16 is a sectional view showing the structure of the ninth step of the production method in the second embodiment of the production of a chip of the present invention.
FIG. 17 is a sectional view showing the structure of the tenth step of the production method in the second embodiment of the production of a chip of the present invention.
FIG. 18 is a sectional view showing the structure of the tenth step of the manufacturing method in the second embodiment of the chip manufacturing method of the present invention.
FIG. 19 is a schematic diagram of a four-probe electrical test according to an embodiment of the present invention.
Wherein, 1, a silicon substrate; 2. an oxygen burying layer; 3. a device layer; 401. an insulating layer; 402. a back side protective layer; 403. a substrate insulating layer; 5. pressing and welding the electrode lead; 6. an undercut structure; 7. a sacrificial layer; 8. an anchor point fixing region; 9. a sample of a material to be tested;
31. an electrostatic actuator; 311. a first sample stage; 312. a first mass block; 313. a support beam; 314. a first lead beam; 315. a moving tooth actuation beam; 316. fixing the tooth actuation beam; 317. supporting beam anchor points; 318. fixing a tooth execution beam anchor point; 319. a first fixed tooth actuation beam; 320. a second fixed tooth actuation beam; 310. a first lead beam anchor point;
32. a thermal actuator; 321. a second sample stage; 322. a second mass block; 323. a heat sink beam; 324. a second lead beam; 325. a V-shaped beam; 326. a second lead beam anchor point; 327. anchoring points of the V-shaped beams; 328. sinking the beam to anchor points;
33. an electrode lead; 331. a first electrode lead; 332. a second electrode lead; 333. a third electrode lead; 334. and a fourth electrode lead.
Detailed Description
The in-situ multi-parameter test chip structure for the TEM/SEM comprises an electrostatic actuator 31, a thermal actuator 32 and an electrode lead 33, as shown in FIG. 1; the electrostatic actuator 31, the thermal actuator 32, and the electrode lead 33 are respectively symmetrical about the same central axis.
The electrostatic actuator 31 is provided with a first sample table 311, and the first sample table 311 moves along the central axis along with the electrostatic actuator 31;
a second sample stage 321 is arranged on the thermal actuator 32, and the second sample stage 321 moves along the central axis along with the thermal actuator 32;
insulating layers are arranged on the first sample table 311 and the second sample table 321;
the electrode lead 33 comprises a first electrode lead 331, a second electrode lead 332, a third electrode lead 333 and a fourth electrode lead 334, wherein one end of each of the first electrode lead 331 and the second electrode lead 332 is positioned on the first sample stage 311, and one end of each of the third electrode lead 333 and the fourth electrode lead 334 is positioned on the second sample stage 321; the other ends of the first electrode lead 331, the second electrode lead 332, the third electrode lead 333 and the fourth electrode lead 334 are all connected with an external test circuit, the external test circuit comprises a voltmeter and a current source, the other ends of the first electrode lead 331 and the third electrode lead 333 are used for being connected with the voltmeter, the other ends of the second electrode lead 332 and the fourth electrode lead 334 are used for the current source, and the electrode lead, the voltmeter and the current source form a four-probe test circuit for testing the electrical characteristics of the sample.
The electrostatic actuator 31 includes a first mass 312, a support beam 313, a first lead beam 314, a movable-tooth actuation beam 315, and a fixed-tooth actuation beam 316;
the first mass block 312 is located on the central axis and is a symmetric axis of the electrostatic actuator 31, the support beam 313, the first lead beam 314, the movable-tooth actuation beam 315, and the fixed-tooth actuation beam 316 are symmetric with respect to the first mass block 312, and the support beam 313, the first lead beam 314, and the movable-tooth actuation beam 315 are respectively connected to the first mass block 312 vertically;
the two ends of the first lead beam 314 are connected with first lead beam anchor points 310, and insulating layers are arranged on the first lead beam 314 and the first lead beam anchor points 310;
at the end of the first mass 312 near the thermal actuator 32 is a first sample stage 311; the first electrode lead 331 and the second electrode lead 332 are positioned on the first lead beam 314, and due to the presence of the insulating layer on the first lead beam 314, electrical isolation between the first electrode lead 331, the second electrode lead 332 and the first lead beam 314 is achieved; one ends of the first electrode lead 331 and the second electrode lead 332 are located on the first sample table 311, an electrode lead pressure welding block 5 is further arranged on the insulating layer of the first lead beam anchor point 310, and the other ends of the first electrode lead 331 and the second electrode lead 332 are connected with an external current source and a voltmeter through the electrode lead pressure welding block 5.
Two ends of the support beam 313 are connected with support beam anchor points 317, the number of the support beams 313 can be multiple, the number of the support beams 313 is two, and the movable tooth execution beam 315 and the fixed tooth execution beam 316 are both positioned between the two support beams 313;
the chip can be provided with a plurality of groups of movable tooth execution beams 315 and fixed tooth execution beams 316, movable teeth are vertically connected to the movable tooth execution beams 315, fixed teeth are vertically connected to the fixed tooth execution beams 316, and the movable teeth and the fixed teeth have the same length and are arranged in a one-to-one correspondence manner;
fixed tooth execution beams 316 are parallel to movable tooth execution beams 315, fixed tooth execution beams 316 include a first fixed tooth execution beam 319 and a second fixed tooth execution beam 320, first fixed tooth execution beam 319 and second fixed tooth execution beam 320 are identical in structure and symmetrical with respect to first mass 312, and one ends of first fixed tooth execution beam 319 and second fixed tooth execution beam 320, which are far away from first mass 312, are respectively connected with fixed tooth execution beam anchor points 318.
The support beam anchor 317 and the fixed tooth execution beam anchor 318 are provided with electrode lead bonding pads 5 for supplying power to the electrostatic actuator 31 from the outside.
The thermal actuator 32 includes a second mass 322, a heat sink beam 323, a V-beam 325, and a second lead beam 324;
the second mass block 322 is located on the central axis, the heat sink beams 323, the V-shaped beams 325 and the second lead beams 324 are respectively connected with the second mass block 322 and are symmetrical with respect to the second mass block 322, and the heat sink beams 323 are distributed on two sides of the V-shaped beams 325; the second lead beam 324 is located at one end of the second mass 322 near the electrostatic actuator 31; two ends of the V-shaped beam 325 are connected with V-shaped beam anchor points 327, two ends of the second lead beam 324 are connected with second lead beam anchor points 326, and two ends of the heat sink beam are connected with heat sink beam anchor points 328;
insulating layers are disposed on the second wirebond beam 324 and on the second wirebond beam anchor 326;
a second sample stage 321 is arranged at one end of the second mass block 322 close to the electrostatic actuator 31; the third electrode lead 333 and the fourth electrode 334 lead are located on the second lead beam 324, and due to the existence of the insulating layers on the second lead beam 324 and the second lead beam anchor point 326, the electrical isolation between the third electrode lead 333, the fourth electrode lead 334 and the second lead beam 324 is realized; the other ends of the third electrode lead 333 and the fourth electrode lead 334 are connected to an external current source and a voltmeter through the electrode lead bonding block 5.
The specific use method comprises the following steps: as shown in fig. 19, the material sample 9 to be measured is placed on the sample stage by using a FIB, PDMS, or other transfer technique, and the material sample is placed along the central axis direction.
Applying direct-current voltage excitation on the electrode lead pressure welding blocks 5 at two ends of the thermal actuator 32, performing high-stress uniaxial tension test on the material sample 9 to be tested, observing the microstructure of the material sample 9 to be tested in situ and reading the electrical characteristics of the material sample 9 to be tested, wherein the electrical characteristics refer to conductivity or resistivity, the force applied to the material sample can be calculated through the displacement of the left electrostatic actuator 31, F is k x, wherein k is the overall rigidity of the electrostatic actuator 31, the overall rigidity of the electrostatic actuator 31 comprises the rigidity of the supporting beam 313 and the first lead beam 314, and x represents the moving distance of the electrostatic actuator 31. The stress borne by the material sample 9 to be tested is sigma F/a, wherein a is the cross-sectional area of the material sample to be tested, and the strain amount of the material sample 9 to be tested can be observed through SEM/TEM, so that the mechanical properties of the material sample 9 to be tested, such as young modulus, breaking strength and the like, can be obtained, and the creep property of the material can also be analyzed through long-time static loading.
Because the rigidity of the thermal actuator 32 is far greater than that of the electrostatic actuator 31 and the material sample 9 to be tested, the thermal actuator can be regarded as a fixed structure, high-frequency alternating-current voltage excitation is applied to the electrode lead pressure welding blocks 5 at the two ends of the electrostatic actuator 31, dynamic tensile test of high-frequency stress is carried out, the fatigue characteristic of the material to be tested is obtained, meanwhile, the voltage waveform can be changed, and different mechanical load tests can be carried out. If the related test is performed in the SEM, the number of comb teeth of the electrostatic actuator 31 may be increased appropriately, the maximum output force of the electrostatic actuator 31 may be increased, and the electrostatic actuator 31 may be regarded as a capacitance sensor as required, so as to realize the automatic detection of the stress applied to the sample to be detected.
A first preparation method of an in-situ multi-parameter test chip for a TEM/SEM (transmission electron microscope) comprises the following steps:
step 1, as shown in FIG. 2, growing 100-200nm silicon nitride layers on the upper surface and the lower surface of an SOI wafer to form an insulating layer 401 and a back surface protection layer 402; the SOI wafer sequentially comprises a device layer 3, a buried oxide layer 2 and a silicon substrate 1 from top to bottom, an insulating layer 401 is positioned on the surface of the device layer 3, and a back surface protection layer 402 is positioned on the surface of the silicon substrate 1; the insulating layer 401 and the back protection layer 402 are both made of silicon nitride materials; the device layer 3 is made of a single crystal silicon material;
step 2, as shown in fig. 3, patterning the insulating layer 401 by using photolithography and reactive ion etching processes, and only remaining the insulating layer 401 located in a sample stage, a lead beam region, and a lead beam anchor region, where the sample stage includes a first sample stage 311 and a second sample stage 321, and the lead beam includes a first lead beam 314 located in the electrostatic actuator 31 and a second lead beam 324 located in the thermal actuator 32; the wirebond beam anchors include a first wirebond beam anchor 310 and a second wirebond beam anchor 326;
step 3, as shown in fig. 4, preparing a Ti/Au metal layer with a thickness of 50/250nm on the device layer 3 and the insulating layer 401 by adopting photoetching and electron beam evaporation processes as an electrode lead and an electrode lead pressure welding block 5; the electrode lead is used for being connected with a sample to be measured and measuring an electrical signal of the sample of the material to be measured. The electrode lead bonding pad 5 is used for connecting the thermal actuator 32 and the electrostatic actuator 31 to an external power supply;
step 4, as shown in fig. 5, a thermal actuator 32 and an electrostatic actuator 31 are prepared on the device layer 3 by using photolithography and reactive ion etching processes;
the electrostatic actuator 31 includes a first mass 312, a support beam 313, a moving-tooth actuation beam 315, a stationary-tooth actuation beam 316, a moving tooth connected perpendicular to the moving-tooth actuation beam 315, a stationary tooth connected perpendicular to the stationary-tooth actuation beam 316, a first lead beam 314, a first lead beam anchor 310, a stationary-tooth actuation beam anchor 318, and a support beam anchor 317.
The thermal actuator 32 includes a second mass 322, a heat sink beam 323, a V-beam 325, a second lead beam 324, a second lead beam anchor 326, a heat sink beam anchor 328, and a V-beam anchor 327.
Step 5, as shown in fig. 6, etching the movable structure, the fixed-tooth execution beam 316 and the back protection layer 402 below the fixed-tooth area in the device layer 3 by using photolithography and reactive ion etching processes; the movable structure comprises a first mass 312, a support beam 313, a first lead beam 314, a movable tooth actuation beam 315, a movable tooth vertically connected with the movable tooth actuation beam 315 in the electrostatic actuator 31, and a second mass 322, a heat sink beam 323, a V-shaped beam 325 and a second lead beam 324 in the thermal actuator 32;
and 6, as shown in fig. 7, etching the movable structure, the fixed tooth execution beam 316, the silicon substrate 1 and the buried oxide layer 2 below the fixed tooth area by adopting a deep reactive ion etching technology to form an undercut structure 6, releasing the movable structure of the device layer 3, and completing the preparation of the chip taking the monocrystalline silicon as the device layer 3.
A second preparation method of the in-situ multi-parameter test chip for the TEM/SEM comprises the following steps:
step 1, as shown in fig. 8, growing a layer of silicon nitride with a thickness of 50-100nm on a silicon substrate 1 to form a substrate insulating layer 403;
step 2, as shown in FIG. 9, depositing a 2-3 μm thick sacrificial layer 7 on the substrate insulating layer 403 by CVD process; the sacrificial layer 7 is made of SiO2And the like;
step 3, as shown in fig. 10, etching the sacrificial layer 7 by using photolithography and reactive ion etching processes to form an anchor point fixing region 8 for fixing the anchor points of the thermal actuator 32 and the electrostatic actuator 31; thermal actuator 32 anchors include second lead beam anchor 326, heat-sink beam anchor 328, and V-beam anchor 327; the electrostatic actuator 31 anchor includes a support beam anchor 317, a stationary tooth execution beam anchor 318, and a first lead beam anchor 310;
step 4, as shown in fig. 11, depositing a silicon nitride insulating material with a thickness of 2-3 μm by CVD, filling the anchor fixing region 8 with the silicon nitride insulating material by photolithography and reactive ion etching, and keeping the surface of the silicon nitride insulating material and the surface of the sacrificial layer 7 horizontal;
step 5, as shown in fig. 12, depositing a layer of polysilicon with a thickness of 3-5 μm on the surface of the silicon nitride insulating material and the sacrificial layer 7 by CVD as the device layer 3;
step 6, as shown in FIG. 13, growing 100-200nm silicon nitride on the polysilicon to form an insulating layer 401;
step 7, as shown in fig. 14, patterning the insulating layer 401 by using photolithography and reactive ion etching processes, and only remaining the insulating layer 401 located in the sample stage, the lead beam region, and the lead beam anchor region;
step 8, as shown in fig. 15, preparing 50/250nm thick Ti/Au metal layer as electrode lead and electrode lead pressure welding block 5 on the polysilicon device layer 3 and the insulating layer 401 by using photoetching and electron beam evaporation processes;
step 9, as shown in fig. 16, preparing an electrostatic actuator 31 and a thermal actuator 32 on the polysilicon device layer 3 by photolithography and reactive ion etching processes;
step 10, as shown in fig. 17, the sacrificial layer 7 is etched to release the movable structures of the electrostatic actuator 31 and the thermal actuator 32;
step 11, as shown in fig. 18, the silicon substrate insulating layer 403 and the silicon substrate 1 below the TEM observation region are etched through by using photolithography and deep reactive ion etching processes to form a TEM observation window, thereby completing the preparation of the chip structure using polysilicon as the device layer 3.
The chip multi-drive test structure designed by the invention can be prepared by two preparation methods provided by the invention. The foregoing illustrates and describes the principles, general features, and advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are intended to further illustrate the principles of the invention, and that various changes and modifications may be made without departing from the spirit and scope of the invention, which is also intended to be covered by the appended claims. The scope of the invention is defined by the claims and their equivalents.

Claims (7)

1. An in-situ multi-parameter test chip structure for a TEM/SEM (transmission electron microscope) is characterized by comprising an electrostatic actuator, a thermal actuator and an electrode lead; the electrostatic actuator, the thermal actuator and the electrode lead are respectively symmetrical about the same central axis;
the electrostatic actuator is provided with a first sample table, and the first sample table moves along the central axis along with the electrostatic actuator;
the thermal actuator is provided with a second sample table, and the second sample table moves along the central axis along with the thermal actuator;
the first sample table and the second sample table are provided with insulating layers;
the electrode lead comprises a first electrode lead, a second electrode lead, a third electrode lead and a fourth electrode lead, one end of the first electrode lead and one end of the second electrode lead are positioned on the first sample table, and one end of the third electrode lead and one end of the fourth electrode lead are positioned on the second sample table; the other ends of the first electrode lead, the second electrode lead, the third electrode lead and the fourth electrode lead are connected with an external test circuit, and the electrode leads and the external test circuit form a four-probe test circuit.
2. The in-situ multiparameter test chip structure for a TEM/SEM (transmission electron microscope) according to claim 1, wherein the external test circuit comprises a voltmeter and a current source, the other ends of the first and third electrode leads are used for connecting the voltmeter, the other ends of the second and fourth electrode leads are used for the current source, and the electrode leads, the voltmeter and the current source form a four-probe test circuit.
3. The in-situ multiparameter test chip structure for TEM/SEM electron microscopes according to claim 1, wherein the electrostatic actuators comprise a first mass, a support beam, a first lead beam, a movable tooth execution beam and a fixed tooth execution beam;
the first mass block is positioned on the central axis and is a symmetric axis of the electrostatic actuator, the support beam, the first lead beam, the movable tooth execution beam and the fixed tooth execution beam are all symmetric about the first mass block, and the support beam, the first lead beam and the movable tooth execution beam are respectively and vertically connected with the first mass block;
two ends of the first lead beam are connected with first lead beam anchor points, and insulating layers are arranged on the first lead beam and the first lead beam anchor points;
a first sample table is arranged at one end, close to the thermal actuator, of the first mass block; the first electrode lead and the second electrode lead are positioned on the first lead beam, and due to the existence of the insulating layer on the first lead beam, the electric isolation among the first electrode lead, the second electrode lead and the first lead beam is realized; one end of the first electrode lead and one end of the second electrode lead are located on the first sample table, an electrode lead press welding block is further arranged on the first lead beam anchor point insulating layer, and the other ends of the first electrode lead and the second electrode lead are connected with an external test circuit through the electrode lead press welding block.
4. The in-situ multiparameter test chip structure for a TEM/SEM (transmission electron microscope) according to claim 1, wherein two ends of the supporting beam are connected with supporting beam anchor points, the two supporting beams are provided, and the movable tooth execution beam and the fixed tooth execution beam are both arranged between the two supporting beams;
the movable tooth execution beam is vertically connected with movable teeth, the fixed tooth execution beam is vertically connected with fixed teeth, and the movable teeth and the fixed teeth are the same in length and are arranged in a one-to-one correspondence manner;
the fixed tooth execution beams are parallel to the movable tooth execution beams and comprise first fixed tooth execution beams and second fixed tooth execution beams, the first fixed tooth execution beams and the second fixed tooth execution beams are identical in structure and symmetrical about the first mass block, and one ends, far away from the first mass block, of the first fixed tooth execution beams and one ends, far away from the first mass block, of the second fixed tooth execution beams are respectively connected with fixed tooth execution beam anchor points;
electrode lead pressure welding blocks are arranged on the supporting beam anchor point and the fixed tooth execution beam anchor point and used for applying an excitation signal to an external electrostatic actuator.
5. The in-situ multiparameter test chip structure for a TEM/SEM (TEM/SEM electron microscope) as claimed in claim 1, wherein the thermal actuator comprises a second mass block, a heat sink beam, a V-shaped beam and a second lead beam;
the second mass block is positioned on the central axis, the heat sink beam, the V-shaped beam and the second lead beam are respectively connected with the second mass block and are symmetrical relative to the second mass block, and the heat sink beams are distributed on two sides of the V-shaped beam; the second lead beam is positioned at one end of the second mass block close to the electrostatic actuator; two ends of the V-shaped beam are connected with V-shaped beam anchor points, two ends of the second lead beam are connected with second lead beam anchor points, and two ends of the heat sink beam are connected with heat sink beam anchor points;
insulating layers are arranged on the second lead beam and anchor points at two ends of the second lead beam;
a second sample stage is arranged at one end, close to the electrostatic actuator, of the second mass block; and the other ends of the third electrode lead and the fourth electrode lead are connected with an external test circuit through an electrode lead press welding block.
6. A method for preparing an in-situ multi-parameter test chip structure for TEM/SEM according to any one of claims 1-5, comprising the following steps:
step 1, growing 100-200nm silicon nitride layers on the upper surface and the lower surface of an SOI wafer to form an insulating layer and a back protective layer; the SOI wafer sequentially comprises a device layer, an oxygen burying layer and a silicon substrate from top to bottom, wherein an insulating layer is positioned on the surface of the device layer, and a back surface protective layer is positioned on the surface of the silicon substrate;
step 2, patterning the insulating layer by adopting photoetching and reactive ion etching processes, and only reserving the insulating layer in the sample stage, the lead beam area and the lead beam anchor point;
step 3, preparing metal layers on the device layer and the insulating layer by adopting photoetching and electron beam evaporation processes to serve as electrode leads and electrode lead press welding blocks;
step 4, preparing a thermal actuator and an electrostatic actuator on the device layer by adopting photoetching and reactive ion etching processes;
step 5, etching a movable structure area, a fixed tooth execution beam and a back protection layer below the fixed tooth in the device layer by adopting photoetching and reactive ion etching processes; the movable structure comprises a first mass block, a support beam, a first lead beam, a movable tooth execution beam, a movable tooth vertically connected with the movable tooth execution beam, a second mass block, a heat sink beam, a V-shaped beam and a second lead beam in the thermal actuator;
and 6, etching the movable structure area, the fixed tooth execution beam, the silicon substrate and the buried oxide layer below the fixed tooth by adopting a deep reactive ion etching technology, releasing the movable structure of the device layer, and finishing the preparation of the chip taking the monocrystalline silicon as the device layer.
7. A method for preparing an in-situ multi-parameter test chip structure for TEM/SEM according to any one of claims 1-5, comprising the following steps:
step 1, growing a layer of silicon nitride with the thickness of 50-100nm on a silicon substrate to form a substrate insulating layer;
step 2, depositing a sacrificial layer with the thickness of 2-3 microns on the substrate insulating layer by a CVD process;
step 3, etching the sacrificial layer by adopting photoetching and reactive ion etching processes to form an anchor point fixing area for fixing anchor points of the thermal actuator and the electrostatic actuator;
step 4, depositing a silicon nitride insulating material with the thickness of 2-3 microns by CVD, filling the anchor fixing area with the silicon nitride insulating material by photoetching and reactive ion etching processes, and keeping the surface of the silicon nitride insulating material and the surface of the sacrificial layer horizontal;
step 5, depositing a layer of polycrystalline silicon with the thickness of 3-5 microns on the surfaces of the silicon nitride insulating material and the sacrificial layer by adopting CVD (chemical vapor deposition) as a device layer;
step 6, growing 100-200nm silicon nitride on the polysilicon to form an insulating layer;
step 7, patterning the insulating layer by adopting photoetching and reactive ion etching processes, and only reserving the insulating layer in the sample stage, the lead beam area and the lead beam anchor point area;
step 8, preparing metal layers on the device layer and the insulating layer by adopting photoetching and electron beam evaporation processes to serve as electrode leads and electrode lead pressure welding blocks;
step 9, preparing an electrostatic actuator and a thermal actuator on the device layer by adopting photoetching and reactive ion etching processes;
step 10, corroding the sacrificial layer, and releasing movable structures of the electrostatic actuator and the thermal actuator;
and 11, etching through the silicon substrate and the substrate insulating layer below the TEM observation area by adopting photoetching and deep reactive ion etching processes to form a TEM observation window, and finishing the preparation of the chip structure taking the polycrystalline silicon as the device layer.
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