CN113200514A - Silicon-based eutectic bonding structure, micromechanical device, packaging structure and preparation method - Google Patents
Silicon-based eutectic bonding structure, micromechanical device, packaging structure and preparation method Download PDFInfo
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- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
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- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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Abstract
The invention discloses a silicon-based eutectic bonding structure, a micro-mechanical device, a packaging structure and a preparation method, wherein the silicon-based eutectic bonding structure comprises a silicon boss wrapped in an insulating layer, and the surface height of the silicon boss is higher than or equal to that of the insulating layer positioned at the bottom of the silicon boss; the device unit in the micro mechanical device is bonded and connected with the substrate unit through the silicon-based eutectic bonding structure, and the electrode of the substrate silicon wafer is led out to the device silicon wafer through the silicon-based eutectic bonding structure; forming a silicon boss structure by using a silicon local oxidation method, exposing a silicon area of the device and ensuring the etching penetration of a movable structure of the device; the cover plate packaging interconnection structure unit in the micromechanical packaging structure is bonded with the micromechanical device through a silicon-based eutectic bonding structure so as to be mechanically and electrically connected. According to the invention, the surface height of the silicon boss is higher than or equal to the surface height of the insulating layer by regulating and controlling the thickness of the local silicon oxide layer twice, so that the mechanical connection reliability and the electrical contact reliability of the silicon-based eutectic bonding structure are improved.
Description
Technical Field
The invention relates to a micro mechanical device, a packaging structure and a preparation method, in particular to a silicon-based eutectic bonding structure, a micro mechanical device, a packaging structure and a preparation method.
Background
Micro Electro Mechanical Systems (MEMS) is a generic term for forming Micro Mechanical elements on a silicon or other dielectric wafer by semiconductor process and Micro nano processing technology and finally integrating with a signal processing circuit. The wafer bonding technology is a key technology for manufacturing and packaging MEMS devices, and the main wafer bonding technologies include silicon fusion bonding, silicon glass anodic bonding, glass paste bonding, polymer bonding, eutectic bonding, diffusion bonding and the like. Different bonding technologies have limitations, but compared with silicon-silicon bonding (bonding temperature is about 600-1200 ℃, surface quality requirement of wafer is high), anodic bonding (450 ℃, high voltage is applied, compatibility with IC is difficult, surface quality requirement of wafer is high), glass slurry bonding (450 ℃, screen printing process is complex, screen printing introduces pollution and bonding alignment accuracy is poor, sealing ring width occupies hundreds of micrometers, compatibility with IC is difficult), and polymer bonding (airtight leakage exists), the eutectic bonding technology represented by the gold-silicon eutectic bonding (the eutectic temperature point is 363 ℃), has few limiting factors, has the advantages of low-temperature bonding (only slightly higher than the eutectic temperature point), high strength, integration of homomorphic/heterogeneous bonding and air-tight/vacuum packaging, meanwhile, the electrical conductivity of the eutectic bonding layer provides a new idea for the design of the electrical interconnection structure of the MEMS device.
In the eutectic bonding technology, common eutectic reaction systems include Au-Sn, Al-Ge, Au-Si, Al-Si and the like. For eutectic bonding technologies such as Au-Sn, Al-Ge, Au-Ge and the like, eutectic reaction between metals is carried out, so that the corresponding bonding medium can be completed only by depositing a layer of metal film, and meanwhile, an electrical interconnection structure for forming a eutectic bonding layer is easily constructed by forming a local electrical contact (such as forming a metal/semiconductor contact) and a local electrical isolation region of the eutectic bonding metal and a silicon wafer body. However, Au-Si, Al-Si, etc. as a eutectic bonding technique based on the principle of silicon-based eutectic reaction are eutectic reactions between a metal and a silicon semiconductor, and thus it requires the silicon bulk of a silicon wafer to provide a source of silicon in the eutectic reaction. In this case, if the Si-based eutectic bonding technology such as Au-Si, Al-Si, etc. also needs to construct an electrical interconnection structure for forming the eutectic bonding layer by forming local electrical contact (e.g. forming metal/semiconductor contact) and local electrical isolation region of the eutectic bonding metal and the Si wafer body, a step introduced by the insulating layer is generated between the bonding metal medium and the Si wafer body for Si-based eutectic reaction to form a certain height difference, and the existence of the height difference enables the liquid phase flow channel formed by the metal/bulk silicon eutectic reaction to be limited at the edge of the step introduced by the insulating layer, which will prevent the reliable formation of the bonding structure based on Si-based eutectic reaction.
Disclosure of Invention
The invention aims to overcome the existing problems and provides a silicon-based eutectic bonding structure, a micro-mechanical device adopting the silicon-based eutectic bonding structure, a packaging structure and a preparation method, wherein the silicon-based eutectic bonding structure, the micro-mechanical device, the packaging structure and the preparation method form a silicon boss wrapped by a silicon local oxide layer on one side of a silicon wafer providing a silicon source in the bonding structure, and the thickness of the silicon boss and the surface of the silicon local oxide layer are kept at the same height or the surface of the silicon boss is slightly higher than the surface of the silicon local oxide layer through twice thickness regulation and control of the silicon local oxide layer, so that the requirements of the eutectic bonding structure on local electrical contact and local electrical isolation and the requirements of full contact and eutectic reaction between a bonding metal medium and a silicon body based on the silicon-based eutectic reaction principle are effectively considered, the mechanical bonding reliability and the electrical interconnection contact reliability of the eutectic bonding structure based on the silicon-based, and the application range of the silicon-based eutectic reaction bonding structure in manufacturing, packaging and interconnection of MEMS devices is widened.
The purpose of the invention is realized by the following technical scheme:
a silicon-based eutectic bonding structure is positioned between two silicon wafers, wherein both the two silicon wafers are provided with an insulating layer and a bonding metal layer, one of the silicon wafers is provided with a silicon boss structure, the periphery of a side wall silicon boss is wrapped by the insulating layer, and the insulating layer extends to the bottom of the silicon boss; the surface height of the silicon boss is equal to or higher than the surface height of the insulating layer at the bottom of the silicon boss;
the surface of the silicon boss is covered by a metal reaction medium in the silicon-based eutectic bonding reaction, and the silicon boss structure is used as a silicon body reaction medium in the silicon-based eutectic bonding reaction.
A silicon-based interconnection structure comprises interconnection silicon columns and a silicon-based eutectic bonding structure, wherein the silicon-based eutectic bonding structure is arranged on the interconnection silicon columns, and insulation grooves obtained by etching and penetrating silicon wafers are arranged on the peripheries of the interconnection silicon columns.
A micromechanical device comprises a substrate unit and a device unit, wherein the substrate unit comprises a substrate silicon wafer, and the device unit comprises a device silicon wafer;
and a silicon-based interconnection structure is arranged on the device silicon wafer, wherein an electrode of the substrate silicon wafer is led out to a device side metal layer on the outer side of the device silicon wafer through a bonding metal layer and a silicon boss structure of the silicon-based interconnection structure.
The device silicon wafer is provided with a device movable structure, and the device movable structure is obtained by etching and penetrating a silicon boss which is not covered with an insulating layer and a bonding metal layer.
A device etching stop region positioned above the device insulating layer is arranged on the device silicon wafer; when the movable structure of the device is released by etching, etching is carried out in the etching stop region of the device, etching is stopped at the insulating layer of the device, an independent silicon island structure of different bulk silicon electrode leading-out regions of the device silicon wafer is formed, the periphery of the independent silicon island structure is surrounded by an annular insulating groove formed by etching stop or etching penetration to form an independent silicon body electrical connection passage, and mutual electrical isolation of different bulk silicon electrode regions is realized.
The device comprises a device silicon wafer and is characterized in that a device insulating layer and a device side metal layer are sequentially arranged on the top side of the device silicon wafer, the device insulating layer is provided with a device top side insulating layer window, and the device side metal layer is electrically contacted with the device silicon wafer through the device top side insulating layer window.
A micro-mechanical packaging structure adopting a silicon-based eutectic bonding structure comprises a micro-mechanical device and a cover plate packaging interconnection structure unit, wherein the cover plate packaging interconnection structure unit comprises a cover plate silicon wafer, and the cover plate silicon wafer is bonded and connected with a device silicon wafer of the micro-mechanical device through the silicon-based eutectic bonding structure; and the electrode of the device silicon wafer is led out to the metal layer on the top side of the cover plate silicon wafer through the silicon-based eutectic bonding structure.
Insulation grooves surrounding the periphery of the window of the cover plate insulation layer are arranged on the cover plate silicon wafer and the cover plate top side metal layer, and the cover plate silicon wafer positioned on the inner side of the insulation grooves forms a silicon column vertical interconnection structure; and the cover plate insulating layer realizes the electrical isolation of the cover plate silicon chip outside the bonding metal layer and the silicon column vertical interconnection structure.
A method for preparing a micro-mechanical device with a silicon-based eutectic bonding structure comprises the following steps:
(1) preparing a substrate silicon wafer, depositing a substrate insulating layer on the substrate silicon wafer, and carrying out photoetching corrosion on the substrate insulating layer to form a substrate insulating layer window which is used as an electrode leading-out window of the substrate silicon wafer;
(2) depositing a substrate side bonding metal layer on the top side of a substrate silicon wafer, performing photoetching corrosion, and forming a metal-semiconductor contact structure at the position of a substrate insulating layer window;
(3) preparing a device silicon wafer, depositing a device silicon nitride layer on the device silicon wafer, and photoetching and corroding or etching the device silicon nitride layer to form a silicon nitride window; the silicon nitride window is used as a silicon thermal oxidation area of the next step, and the rest device silicon nitride layer is used as a protective layer for forming a silicon boss of the next step;
(4) carrying out a high-temperature thermal oxidation process on a device silicon wafer containing a device silicon nitride layer pattern to form a device first silicon oxide layer; on the device silicon chip, the part which is not covered with the device silicon nitride layer is oxidized to form a device first silicon oxide layer, and the part which is covered with the device silicon nitride layer forms a silicon boss; the surface height of the first silicon oxide layer of the device is higher than that of the device silicon wafer covered with the silicon nitride layer of the device;
(5) etching a first silicon oxide layer of a device formed on a silicon wafer of the device by a wet etching process;
(6) performing secondary high-temperature thermal oxidation process on the device silicon wafer containing the device silicon nitride layer pattern to form a device second silicon dioxide layer serving as a device insulating layer at the bottom side of the device silicon wafer; the surface height of the device silicon wafer covered with the device silicon nitride layer is higher than or equal to the surface height of the second silicon dioxide layer of the device;
(7) corroding the silicon nitride layer of the device completely by a wet corrosion process to expose the surface of the silicon boss, wherein the silicon boss is used as a bottom electrode leading-out window and an etching release window of the silicon wafer of the device and a silicon plane in silicon-based eutectic reaction;
depositing a device side bonding metal layer on the bottom side of the device silicon wafer, performing photoetching corrosion, and forming a metal-semiconductor contact structure, an etching release window and a silicon-based eutectic bonding plane at a bottom side electrode leading-out window of the device silicon wafer;
(8) carrying out face-to-face alignment bonding process on the bonding metal sides of the device silicon wafer and the substrate silicon wafer to realize mechanical and electrical connection between the device silicon wafer and the substrate silicon wafer;
(9) depositing a device insulating layer on the top side of the device silicon wafer, and etching the device insulating layer to form a device top side insulating layer window and a top side bulk silicon etching exposure window which are used as top side electrode leading-out windows of the device silicon wafer;
(10) depositing a device side metal layer on the top side of the device silicon wafer, and etching the device side metal layer;
(11) photoetching and corroding the device silicon wafer at the top-side silicon etching exposure window, etching and penetrating the device silicon wafer to form a device movable structure, wherein the device movable structure is supported by a eutectic bonding structure corresponding to a silicon boss of the device silicon wafer; and simultaneously, etching is stopped at the device insulating layer at the bottom side of the device silicon wafer to form independent silicon island structures of different electrode lead-out areas.
In the step (2), a substrate cavity etching window is formed on the top side of the substrate silicon wafer in an etching mode, and a substrate cavity structure is formed through dry etching or wet etching.
A preparation method of a micro-mechanical packaging structure adopting a silicon-based eutectic bonding structure comprises the following steps:
(1) preparing a cover plate silicon wafer, depositing a cover plate silicon nitride layer on the cover plate silicon wafer, and etching the cover plate silicon nitride layer to form a silicon nitride window; the silicon nitride window is used as a silicon thermal oxidation area of the next step, and the rest device silicon nitride layer is used as a protective layer for forming a silicon boss of the next step;
(2) carrying out a high-temperature thermal oxidation process on a cover plate silicon wafer containing a cover plate silicon nitride layer pattern to form a cover plate first silicon oxide layer; on the cover plate silicon chip, the part not covered with the cover plate silicon nitride layer is oxidized to form a cover plate first silicon oxide layer, the part covered with the cover plate silicon nitride layer forms a silicon boss, and the silicon boss respectively is an annular bonding seal ring structure and a silicon column interconnection bonding electrode leading-out structure; the surface height of the first silicon oxide layer of the cover plate is higher than that of the cover plate silicon wafer covered with the silicon nitride layer of the cover plate;
(3) etching a first silicon oxide layer of the cover plate formed by oxidizing the silicon wafer of the cover plate by a wet etching process;
(4) carrying out secondary high-temperature thermal oxidation process on the cover plate silicon wafer containing the cover plate silicon nitride layer pattern to form a cover plate second silicon dioxide layer serving as a cover plate insulating layer on the bottom side of the cover plate silicon wafer; the surface height of the cover plate silicon wafer covered with the cover plate silicon nitride layer is higher than or equal to the surface height of the second silicon dioxide layer of the cover plate;
(5) the cover plate silicon nitride layer is completely corroded by a wet corrosion process, the surface of the silicon boss is exposed and serves as a bottom electrode leading-out window of the cover plate silicon wafer;
depositing a cover plate side bonding metal layer on the bottom side of the cover plate silicon wafer, performing photoetching corrosion, and forming a metal and semiconductor contact structure at a bottom side electrode lead-out window of the cover plate silicon wafer;
(6) carrying out face-to-face alignment bonding process on the prepared cover plate silicon chip and a micro mechanical device to be wafer-level packaged to realize mechanical and electrical connection between a packaging structure and the micro mechanical device;
(7) depositing a cover plate top side metal layer on the top side of the cover plate silicon wafer, and etching the cover plate top side metal layer; etching the silicon area of the cover plate silicon wafer body exposed by the cover plate top side metal layer, stopping at the cover plate insulating layer and forming an annular cover plate insulating groove; the cover plate silicon wafer positioned on the inner side of the insulation groove forms an independent silicon column vertical interconnection structure, and the cover plate top side metal layer positioned on the inner side of the insulation groove forms an electric signal interface region;
(8) the preparation of the micromechanical wafer-level packaging structure with the vertically interconnected silicon pillars is completed.
In the step (5), after photoetching and corrosion are carried out on the bonding metal layer on the side of the cover plate, etching is carried out on the second silicon dioxide layer of the cover plate silicon wafer, and the silicon area of the cover plate silicon wafer body is exposed; and etching the exposed bulk silicon region of the cover plate silicon wafer by using dry etching or wet etching to form a cover plate cavity.
Compared with the prior art, the invention has the following beneficial effects:
in the invention, a eutectic bonding structure based on a silicon-based eutectic reaction principle between metal and a silicon body is improved by utilizing a two-step silicon local oxidation process, a silicon boss wrapped by a silicon local oxide layer is formed on one side of a silicon wafer providing a silicon source in the bonding structure, the surface of the silicon boss and the surface of the silicon local oxide layer are kept at the same height or the surface of the silicon boss is slightly higher than the surface of the silicon local oxide layer through twice thickness regulation and control of the silicon local oxide layer, thereby effectively meeting the requirements of the eutectic bonding structure based on the silicon-based eutectic reaction principle on local electrical contact and local electrical isolation and the requirements of full contact and eutectic reaction between the bonding metal medium and the silicon body, improving the mechanical bonding reliability and the electrical interconnection contact reliability of the eutectic bonding structure based on the silicon-based eutectic reaction principle, and the application range of the silicon-based eutectic reaction bonding structure in manufacturing, packaging and interconnection of MEMS devices is widened.
Drawings
Fig. 1 is a cross-sectional view of a micro-mechanical device and a package structure in the present invention.
FIGS. 2 to 12 are sectional views showing a manufacturing process of a micro-mechanical device according to the present invention, in which FIG. 2 is a sectional view showing a window of a substrate insulating layer etched on a cover insulating layer of a substrate silicon wafer, FIG. 3 is a sectional view showing a cover cavity etched on the substrate silicon wafer and a bonding metal layer deposited on a substrate side, FIG. 4 is a sectional view showing a silicon nitride layer deposited on the device silicon wafer and etched, FIG. 5 is a sectional view showing a high temperature thermal oxidation process performed on the device silicon wafer, FIG. 6 is a sectional view showing a first silicon oxide layer etched clean on the device silicon wafer, FIG. 7 is a sectional view showing a high temperature thermal oxidation process performed on the device silicon wafer, FIG. 8 is a sectional view showing a bonding metal layer etched clean and deposited on a device side, FIG. 9 is a sectional view showing a bonding process performed on a metal side of the device silicon wafer and the substrate silicon wafer in a face-to-face alignment manner, FIG. 10 is a cross-sectional view of a device insulating layer deposited and patterned on the top side of a device silicon wafer, FIG. 11 is a cross-sectional view of a device side bonding metal layer deposited and patterned on the top side of the device silicon wafer, and FIG. 12 is a cross-sectional view of a device movable structure etched through the device silicon wafer.
Fig. 13 to 19 are sectional views showing a manufacturing process of a package structure according to the present invention, in which fig. 13 is a sectional view showing a cover silicon nitride layer deposited on a cover silicon wafer and patterned, fig. 14 is a sectional view showing a high temperature thermal oxidation process performed on the cover silicon wafer once, fig. 15 is a sectional view showing a first silicon oxide layer of a cover formed by oxidizing the cover silicon wafer and etched clean, fig. 16 is a sectional view showing a high temperature thermal oxidation process performed on the cover silicon wafer twice, fig. 17 is a sectional view showing a cover silicon nitride layer etched clean and deposited on a cover side bonding metal layer, fig. 18 is a sectional view showing a cover cavity etched on the cover silicon wafer, and fig. 19 is a sectional view showing a vertical interconnection structure of silicon pillars etched on the cover silicon wafer.
The reference numbers in the figures are respectively:
Detailed Description
In order to make those skilled in the art understand the technical solutions of the present invention well, the following description of the present invention is provided with reference to the embodiments and the accompanying drawings, but the embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, the micromechanical device using a silicon-based eutectic bonding structure in this embodiment includes a device silicon wafer 203, where a device insulating layer 202 and a device side bonding metal layer 201 are sequentially disposed on both sides of the device silicon wafer 203, where the device insulating layer 202 on the bottom side is disposed with a device bottom side insulating layer window, and the device side bonding metal layer 201 on the bottom side electrically contacts the device silicon wafer 203 through the device bottom side insulating layer window; the device side bonding metal layer 201 on the bottom side and the substrate side bonding metal layer 104 are connected with each other to form a bonding structure; a silicon boss 211 is arranged at a position, corresponding to the window of the insulating layer at the bottom side of the device, on the device silicon wafer 203, the periphery of the silicon boss 211 is wrapped by the insulating layer, and the insulating layer extends to the bottom of the silicon boss 211; the surface height of the silicon boss 211 is equal to or slightly higher than that of the insulating layer; the surface of the silicon boss 211 is covered by a metal reaction medium in the silicon-based eutectic bonding reaction, and the structure of the silicon boss 211 is used as a silicon body reaction medium in the silicon-based eutectic bonding reaction.
Further, the silicon-based eutectic bonding structure in the embodiment can realize both electrical contact and mechanical bonding.
Referring to fig. 2 to 12, the method for manufacturing a micromechanical device according to the present embodiment includes the steps of:
(1) preparing a silicon wafer with low resistivity as a substrate silicon wafer 102 (for example, selecting a silicon wafer with the resistivity of 0.02 omega cm), depositing substrate insulating layers 103 and 101 (for example, silicon oxide, silicon nitride and the like) on the top sides of the silicon wafers, and performing photoetching corrosion on the insulating layers to form a substrate insulating layer window 111 with a certain width as a substrate silicon electrode lead-out window and a substrate cavity etching window, as shown in fig. 2.
(2) Depositing a substrate side bonding metal layer 104 (such as bonding medium metal Au or Al in a silicon-based eutectic system of Au-Si, Al-Si and the like) on the top side of the substrate silicon wafer, performing photoetching corrosion, forming a substrate side bonding metal layer with a certain width at a preset substrate insulating layer window 111 to construct a metal/semiconductor contact structure of the metal layer 104 and the substrate silicon 102, further performing photoetching corrosion on the top side of the substrate silicon wafer to only expose a substrate cavity etching window, and forming a substrate cavity structure 112 through dry etching or wet etching, as shown in FIG. 3.
(3) Preparing a silicon wafer with low resistivity as the device silicon wafer 203 (for example, selecting a silicon wafer with resistivity of 0.02 Ω · cm), depositing a device-side silicon nitride layer 221 on the silicon wafer (for example, LPCVD), and performing photolithography etching or etching (for example, reactive ion etching RIE) on the silicon nitride layer at the bottom side to form a silicon nitride window with a certain width as a silicon thermal oxidation region of the next step, and using the remaining silicon nitride layer as a protective layer formed by the silicon boss of the next step, as shown in fig. 4.
(4) The device silicon wafer 203 including the silicon nitride pattern 221 is subjected to a first high temperature thermal oxidation process of silicon to form a first silicon oxide layer 202' with a certain thickness, and at this time, it is known from the principle of thermal oxidation of silicon that the height of the surface of bulk silicon covered with silicon nitride is lower than that of the surface of silicon oxide formed by oxidation without covering with silicon nitride, and a first silicon mesa 211 is formed in the area covered with silicon nitride, as shown in fig. 5.
(5) Then, the first oxide layer 202' formed by oxidizing the device silicon wafer 203 is etched clean by a wet etching process (e.g., BOE buffered oxide etchant), as shown in fig. 6.
(6) The device silicon wafer 203 containing the silicon nitride pattern 221 is subjected to a second high-temperature thermal oxidation process of silicon to form a second silicon oxide layer 202 with a certain thickness, and the height of the surface of bulk silicon covered with silicon nitride is slightly higher than or equal to the height of the surface of silicon oxide formed by oxidation without covering silicon nitride (according to the principle of silicon thermal oxidation, the difference between the heights of the two surfaces can be adjusted by the thickness of the first silicon oxide layer 202' and the thickness of the second silicon oxide layer 202, and the difference can be set to zero to eliminate the difference in height of the insulating layer introduced on the surface of the silicon wafer body), as shown in fig. 7.
(7) Then, the silicon nitride layer 221 is etched to be clean by a wet etching process (such as hot phosphoric acid) to expose the silicon boss surface of the device silicon wafer 203, and the silicon boss surface is used as a device bulk silicon etching exposed region and a device bulk silicon electrode leading-out window (namely, a bonding metal/bulk silicon eutectic reaction interface), then, a device bottom side bonding metal layer 201 (such as bonding medium metal Au or Al and the like in a silicon-based eutectic system of Au-Si, Al-Si and the like) is deposited, and photoetching is carried out, so that a device bottom side bonding metal region with a certain width is formed only at the preset device bulk silicon electrode leading-out window (namely, the bonding metal/bulk silicon eutectic reaction interface), and the device bulk silicon etching exposed region is not covered by the bonding metal, as shown in fig. 8.
(8) The device silicon wafer and the bonding metal side of the substrate silicon wafer are subjected to a face-to-face alignment bonding process, wherein the device bottom side bonding metal layer 201 and the substrate top side bonding metal layer 104 form a bonding structure through a silicon-based eutectic reaction (for example, a bonding metal/bulk silicon eutectic bonding process of Au-Si, Al-Si and the like, the device bottom side bonding metal 201 of the device silicon wafer is firstly subjected to a eutectic reaction with a bulk silicon electrode lead-out window at a silicon boss 211 of the device silicon wafer to form a liquid phase, and then is further subjected to a eutectic reaction with the substrate top side bonding metal layer 104), and the bonding metal layer 201 is in metal/semiconductor contact with the device bulk silicon 203, and the bonding metal 104 is in metal/semiconductor contact with the substrate bulk silicon 102 and is converted into ohmic contact under the high-temperature effect of the bonding process, as shown in fig. 9.
(9) The device silicon wafer bonded with the substrate silicon wafer into a whole is subjected to a thinning process to be thinned to the thickness required by the device silicon wafer, then an insulating layer 204 is deposited (such as plasma enhanced chemical vapor deposition PECVD) on the top side of the device silicon wafer 203, and the insulating layer is subjected to photoetching corrosion or etching patterning to form a device silicon wafer top side silicon electrode lead-out window 212 and a device silicon wafer top side silicon etching exposed area 213, as shown in FIG. 10.
(10) A metal layer 205 is deposited (e.g., sputtered) on the top side of the device wafer 203 and patterned by photolithographic etching or etching to form bulk silicon electrode lead-out regions on the top side of the device wafer, as shown in fig. 11.
(11) Photoetching and corroding the top side of the device silicon wafer 203, etching and penetrating the device silicon wafer 203 (a device silicon wafer etching penetrating region 214) at a device silicon wafer top side silicon etching exposed region 213 through Deep Reactive Ion Etching (DRIE) to form a device movable structure 216, wherein the device movable structure 216 is supported by a eutectic bonding structure corresponding to a silicon boss 211 in the device silicon wafer 203, and etching the device silicon wafer 203 at the device silicon wafer top side silicon etching exposed region through Deep Reactive Ion Etching (DRIE) and etching an insulating silicon wafer 203 at the bottom of the device silicon wafer 203
Etching stops at the insulating layer 202 (a device silicon wafer etching stop region 215), so as to form independent silicon island structures of different bulk silicon electrode lead-out regions in the device silicon wafer 203 (i.e. to realize the electrical isolation of different bulk silicon electrode regions from each other), thereby completing the preparation of the micromechanical device structure adopting the improved silicon-based eutectic bonding, as shown in fig. 12.
Example 2
Referring to fig. 1, the micromechanical package structure using silicon-based eutectic bonding in this embodiment includes a micromechanical device and a cover plate package interconnection structure unit, where the micromechanical device includes a substrate unit and a device unit, the substrate unit includes a substrate silicon wafer 102, and a substrate insulating layer 103 and a substrate-side bonding metal layer 104 are sequentially disposed on the substrate silicon wafer 102.
The cover plate packaging interconnection structure unit comprises a cover plate silicon wafer 303, wherein a cover plate insulating layer 302 and a cover plate side bonding metal layer 301 are sequentially arranged on the bottom side of the cover plate silicon wafer 303, and a cover plate top side metal layer 304 is arranged on the top side of the cover plate silicon wafer 303; the cover plate side bonding metal layer 301 is bonded and connected with the device side bonding metal layer 201 through a silicon-based eutectic bonding structure containing the silicon boss 211, and a cover plate insulating layer window is arranged on the cover plate insulating layer 302; the lid side bond metal layer 301 is in electrical contact with the lid silicon die 303 through the lid insulating layer window. The silicon-based eutectic bonding structure is characterized in that an insulating groove obtained by etching and penetrating through a silicon wafer is annularly sleeved on the outer side of the silicon-based eutectic bonding structure, and a silicon-based interconnection structure is formed in the insulating groove.
Further, insulation grooves 314 surrounding the periphery of the window of the cover plate insulation layer 302 are arranged on the cover plate silicon wafer 303 and the cover plate top side metal layer 301, and the cover plate silicon wafer 303 positioned on the inner side of the insulation grooves 314 forms a silicon pillar vertical interconnection structure 313; the cover plate insulating layer 302 achieves electrical isolation of the bonding metal layer from the cover plate silicon wafer 303 outside the silicon pillar vertical interconnect structure 313.
The micromechanical device in this embodiment may be the micromechanical device in embodiment 1, or may be any other micromechanical device implemented by the prior art.
Referring to fig. 1 and fig. 13 to 19, the method for manufacturing a micromechanical package structure according to this embodiment includes the following steps:
(1) a silicon wafer with low resistivity is prepared as a cover silicon wafer 303 (for example, a silicon wafer with resistivity of 0.02 Ω · cm is selected), a cover silicon nitride layer 321 is deposited on the silicon wafer by low pressure chemical vapor deposition LPCVD, and the silicon nitride layer on the bottom side of the cover silicon wafer is etched by photolithography to form a silicon nitride window with a certain width as a silicon thermal oxidation region in the next step, and the remaining silicon nitride is used as a protective layer formed on a silicon boss in the next step, as shown in fig. 13.
(2) The cover plate silicon wafer 303 containing the silicon nitride pattern 321 is subjected to a first high-temperature thermal oxidation process of silicon to form a first silicon oxide layer 302' with a certain thickness, and at this time, it is known from the principle of thermal oxidation of silicon that the height of the surface of bulk silicon covered with silicon nitride is lower than that of the surface of silicon oxide formed by oxidation without covering with silicon nitride, and silicon bosses 315 and 311 are formed in the area covered with silicon nitride, wherein the silicon boss 315 area is used as an annular bonding sealing ring area (surrounding the structure of a device to be packaged) for packaging the cover plate silicon wafer, and the silicon boss 311 area is used as a silicon pillar interconnection bonding electrode area for packaging the cover plate silicon wafer, as shown in fig. 14.
(3) Then, the first oxide layer 302' formed by oxidizing the cover silicon wafer 303 is etched clean by a wet etching process (e.g., BOE buffered oxide etchant), as shown in fig. 15.
(4) The cover silicon wafer 303 containing the silicon nitride pattern 321 is subjected to a second high-temperature thermal oxidation process of silicon to form a second silicon oxide layer 302 with a certain thickness, and the height of the surface of bulk silicon covered with silicon nitride is slightly higher than or equal to the height of the surface of silicon oxide formed by oxidation without covering silicon nitride (according to the principle of silicon thermal oxidation, the difference between the heights of the two surfaces can be adjusted by the thickness of the first silicon oxide layer 302' and the thickness of the second silicon oxide layer 302, and the difference can be set to zero to eliminate the difference in height of the insulating layer introduced on the surface of the silicon wafer body), as shown in fig. 16.
(5) Then, the silicon nitride layer 321 is etched clean by a wet etching process (such as hot phosphoric acid) to expose the silicon boss surface of the cover plate silicon wafer 303, and the silicon boss surface is used as a cover plate silicon electrode leading-out window (i.e. a bonding metal/bulk silicon eutectic reaction interface), then, a bonding metal layer 301 (such as bonding medium metal Au or Al and the like in a silicon-based eutectic system of Au-Si, Al-Si and the like) on the bottom side of the cover plate silicon wafer is deposited, and photoetching corrosion is performed, and a device bottom side bonding metal region with a certain width is formed at a preset cover plate silicon body silicon electrode leading-out window (i.e. a bonding metal/bulk silicon eutectic reaction interface), as shown in fig. 17.
(6) The bottom side silicon oxide layer 302 of the cover silicon wafer 303 is patterned by photolithography and wet etching or dry etching (e.g., reactive ion etching RIE) to expose the designated bulk silicon region of the cover silicon wafer 303, and the exposed bulk silicon region of the cover silicon wafer 303 is etched by dry etching (e.g., deep reactive ion etching DRIE) or wet etching to form a cover cavity 316 with a certain depth, as shown in fig. 18.
(7) The micromechanical device structure 203 to be wafer-level packaged and the bonding metal layer of the cover plate packaging structure 303 are subjected to a face-to-face alignment bonding process (such as Au-Si, Al-Si, and other bonding metal/bulk silicon eutectic bonding), wherein the bonding metal 301 on the bottom side of the cover plate silicon wafer first performs eutectic reaction with the surfaces of the cover plate silicon bosses 315 and 311 to form a liquid phase, and then further performs eutectic reaction with the bonding metal layer 205 on the top side of the device silicon wafer, and the bonding metal layer 301 is in metal/semiconductor contact with the cover plate bulk silicon 303, and the bonding metal layer 205 is in metal/semiconductor contact with the device bulk silicon 203 and is converted into ohmic contact under the high temperature effect of the bonding process, so as to finally form a device packaging integral bonding structure of the micromechanical device structure and the cover plate packaging structure, as shown in fig. 19.
(8) A cover-top-side metal layer 304 (any metal capable of forming ohmic contact with silicon, such as Au, Al film, etc.) is deposited on top of the cover silicon wafer 303 of the device package integral bonding structure, and is subjected to photolithography etching, then further wet etching or dry etching is performed on the silicon region of the cover silicon wafer 303 exposed by the metal layer 304 to form an annular cover insulating trench 314, and the etching or etching will be terminated at the cover-bottom-side insulating layer (i.e., thermal silicon oxide layer) 302 corresponding to the bottom of the insulating trench 314, so as to form an independent cover-top-side silicon pillar vertical interconnect structure 313, and at the same time, an electrical signal interface region 312 of the cover-top-side metal layer 304 to the cover-top-side silicon pillar vertical interconnect structure 313 is formed, as shown in fig. 1.
(9) The above-mentioned fabrication of the micromechanical wafer-level package structure with the silicon pillar vertical interconnect is completed, in which the cover plate silicon pillar vertical interconnect 313 implements vertical extraction of electrical signals (device top-side metal layer 205) inside the device package through ohmic contacts formed between metal/semiconductor contacts on upper and lower sides thereof, and the ohmic contacts may be formed either during the high temperature process of the aforementioned bonding process or through a separate thermal treatment or annealing process after the bonding process.
The present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents and are included in the scope of the present invention.
Claims (9)
1. A silicon-based eutectic bonding structure is positioned between two silicon chips, and both the two silicon chips are provided with an insulating layer and a bonding metal layer; the surface height of the silicon boss is equal to or higher than the surface height of the insulating layer at the bottom of the silicon boss;
the surface of the silicon boss is covered by a metal reaction medium in the silicon-based eutectic bonding reaction, and the silicon boss structure is used as a silicon body reaction medium in the silicon-based eutectic bonding reaction.
2. A micromechanical device comprises a substrate unit and a device unit, wherein the substrate unit comprises a substrate silicon wafer, and the device unit comprises a device silicon wafer; the device is characterized in that the device silicon wafer is bonded and connected with the substrate silicon wafer through the silicon-based eutectic bonding structure of claim 1, an insulation groove is arranged on the device silicon wafer and positioned on the outer side of the silicon-based eutectic bonding structure, and the silicon-based eutectic bonding structure positioned in the insulation groove and a local area of the device silicon wafer form a silicon-based interconnection structure;
and the electrode of the substrate silicon wafer is led out to a device side metal layer on the outer side of the device silicon wafer through the bonding metal layer and the silicon boss structure of the silicon-based interconnection structure.
3. The micromechanical device according to claim 2, characterized in that the device silicon wafer is provided with a device movable structure obtained by etching through silicon bosses not covered with insulating layer and bonding metal layer.
4. The micromechanical device according to claim 3, wherein the device silicon wafer is provided with a device etch stop region located above the device insulating layer; and when the movable structure of the device is etched and released, etching is carried out in the etching stop area of the device, etching is stopped at the insulating layer of the device, an independent silicon island structure of different bulk silicon electrode leading-out areas of the device silicon wafer is formed, and the periphery of the independent silicon island structure is surrounded by an annular insulating groove formed by etching stop or etching penetration to form an independent silicon body electrical connection passage.
5. The micromechanical device of claim 2, wherein the top side of the device silicon wafer is sequentially provided with a device insulating layer and a device side metal layer, the device insulating layer is provided with a device top side insulating layer window, and the device side metal layer is in electrical contact with the device silicon wafer through the device top side insulating layer window.
6. A micromechanical packaging structure, comprising a micromechanical device and a cover plate packaging interconnection structure unit, wherein the cover plate packaging interconnection structure unit comprises a cover plate silicon wafer, and the cover plate silicon wafer is bonded and connected with a device silicon wafer of the micromechanical device through a silicon-based eutectic bonding structure according to claim 1; and the electrode of the device silicon wafer is led out to the metal layer on the top side of the cover plate silicon wafer through the silicon-based eutectic bonding structure.
7. The micromechanical package structure according to claim 6, wherein the cover silicon wafer and the cover top side metal layer are provided with insulation trenches surrounding the windows of the cover insulation layer, and the cover silicon wafer located inside the insulation trenches forms a silicon pillar vertical interconnection structure; and the cover plate insulating layer realizes the electrical isolation of the cover plate silicon chip outside the bonding metal layer and the silicon column vertical interconnection structure.
8. A method for manufacturing a micromechanical device, comprising the steps of:
(1) preparing a substrate silicon wafer, depositing a substrate insulating layer on the substrate silicon wafer, and carrying out photoetching corrosion on the substrate insulating layer to form a substrate insulating layer window which is used as an electrode leading-out window of the substrate silicon wafer;
(2) depositing a substrate side bonding metal layer on the top side of a substrate silicon wafer, performing photoetching corrosion, and forming a metal-semiconductor contact structure at the position of a substrate insulating layer window;
(3) preparing a device silicon wafer, depositing a device silicon nitride layer on the device silicon wafer, and photoetching and corroding or etching the device silicon nitride layer to form a silicon nitride window; the silicon nitride window is used as a silicon thermal oxidation area of the next step, and the rest device silicon nitride layer is used as a protective layer for forming a silicon boss of the next step;
(4) carrying out a high-temperature thermal oxidation process on a device silicon wafer containing a device silicon nitride layer pattern to form a device first silicon oxide layer; on the device silicon chip, the part which is not covered with the device silicon nitride layer is oxidized to form a device first silicon oxide layer, and the part which is covered with the device silicon nitride layer forms a silicon boss; the surface height of the first silicon oxide layer of the device is higher than that of the device silicon wafer covered with the silicon nitride layer of the device;
(5) etching a first silicon oxide layer of a device formed on a silicon wafer of the device by a wet etching process;
(6) performing secondary high-temperature thermal oxidation process on the device silicon wafer containing the device silicon nitride layer pattern to form a device second silicon dioxide layer serving as a device insulating layer at the bottom side of the device silicon wafer; the surface height of the device silicon wafer covered with the device silicon nitride layer is higher than or equal to the surface height of the second silicon dioxide layer of the device;
(7) corroding the silicon nitride layer of the device completely by a wet corrosion process to expose the surface of the silicon boss, wherein the silicon boss is used as a bottom electrode leading-out window and an etching release window of the silicon wafer of the device and a silicon plane in silicon-based eutectic reaction;
depositing a device side bonding metal layer on the bottom side of the device silicon wafer, performing photoetching corrosion, and forming a metal-semiconductor contact structure, an etching release window and a silicon-based eutectic bonding plane at a bottom side electrode leading-out window of the device silicon wafer;
(8) carrying out face-to-face alignment bonding process on the bonding metal sides of the device silicon wafer and the substrate silicon wafer to realize mechanical and electrical connection between the device silicon wafer and the substrate silicon wafer;
(9) depositing a device insulating layer on the top side of the device silicon wafer, and etching the device insulating layer to form a device top side insulating layer window and a top side bulk silicon etching exposure window which are used as top side electrode leading-out windows of the device silicon wafer;
(10) depositing a device side metal layer on the top side of the device silicon wafer, and etching the device side metal layer;
(11) photoetching and corroding the device silicon wafer at the top-side silicon etching exposure window, etching and penetrating the device silicon wafer to form a device movable structure, wherein the device movable structure is supported by a eutectic bonding structure corresponding to a silicon boss of the device silicon wafer; and simultaneously, etching is stopped at the device insulating layer at the bottom side of the device silicon wafer to form independent silicon island structures of different electrode lead-out areas.
9. A preparation method of a micromechanical packaging structure is characterized by comprising the following steps:
(1) preparing a cover plate silicon wafer, depositing a cover plate silicon nitride layer on the cover plate silicon wafer, and etching the cover plate silicon nitride layer to form a silicon nitride window; the silicon nitride window is used as a silicon thermal oxidation area of the next step, and the rest device silicon nitride layer is used as a protective layer for forming a silicon boss of the next step;
(2) carrying out a high-temperature thermal oxidation process on a cover plate silicon wafer containing a cover plate silicon nitride layer pattern to form a cover plate first silicon oxide layer; on the cover plate silicon chip, the part not covered with the cover plate silicon nitride layer is oxidized to form a cover plate first silicon oxide layer, the part covered with the cover plate silicon nitride layer forms a silicon boss, and the silicon boss respectively is an annular bonding seal ring structure and a silicon column interconnection bonding electrode leading-out structure; the surface height of the first silicon oxide layer of the cover plate is higher than that of the cover plate silicon wafer covered with the silicon nitride layer of the cover plate;
(3) etching a first silicon oxide layer of the cover plate formed by oxidizing the silicon wafer of the cover plate by a wet etching process;
(4) carrying out secondary high-temperature thermal oxidation process on the cover plate silicon wafer containing the cover plate silicon nitride layer pattern to form a cover plate second silicon dioxide layer serving as a cover plate insulating layer on the bottom side of the cover plate silicon wafer; the surface height of the cover plate silicon wafer covered with the cover plate silicon nitride layer is higher than or equal to the surface height of the second silicon dioxide layer of the cover plate;
(5) the cover plate silicon nitride layer is completely corroded by a wet corrosion process, the surface of the silicon boss is exposed and serves as a bottom electrode leading-out window of the cover plate silicon wafer;
depositing a cover plate side bonding metal layer on the bottom side of the cover plate silicon wafer, performing photoetching corrosion, and forming a metal and semiconductor contact structure at a bottom side electrode lead-out window of the cover plate silicon wafer;
(6) carrying out face-to-face alignment bonding process on the prepared cover plate silicon chip and a micro mechanical device to be wafer-level packaged to realize mechanical and electrical connection between a packaging structure and the micro mechanical device;
(7) depositing a cover plate top side metal layer on the top side of the cover plate silicon wafer, and etching the cover plate top side metal layer; etching the silicon area of the cover plate silicon wafer body exposed by the cover plate top side metal layer, stopping at the cover plate insulating layer and forming an annular cover plate insulating groove; the cover plate silicon wafer positioned on the inner side of the insulation groove forms an independent silicon column vertical interconnection structure, and the cover plate top side metal layer positioned on the inner side of the insulation groove forms an electric signal interface region;
(8) the preparation of the micromechanical wafer-level packaging structure with the vertically interconnected silicon pillars is completed.
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