CN113196008A

CN113196008A - DLL circuit, time difference amplification circuit, and range finding imaging device

Info

Publication number: CN113196008A
Application number: CN201980082186.0A
Authority: CN
Inventors: 加藤匠; 松川和生; 尾关俊明
Original assignee: Nuvoton Technology Corp Japan
Current assignee: Nuvoton Technology Corp Japan
Priority date: 2018-12-18
Filing date: 2019-12-17
Publication date: 2021-07-30
Anticipated expiration: 2039-12-17
Also published as: WO2020129947A1; JPWO2020129947A1; US20210344347A1; CN113196008B

Abstract

A DLL circuit (10) is provided with: a time difference amplification circuit (11) which amplifies a 1 st signal and a 2 nd signal to be input, that is, a time difference between an edge which is a change point of a logic level included in the 1 st signal and an edge which is a change point of a logic level included in the 2 nd signal, and outputs the obtained 1 st amplified signal and the 2 nd amplified signal; a phase comparison circuit (12) that calculates the phase difference between the 1 st and 2 nd amplified signals output from the time difference amplification circuit (11), and outputs a phase difference signal indicating the calculated phase difference; and a variable delay circuit (13) that delays the 2 nd signal by a delay amount that depends on the phase difference indicated by the phase difference signal output from the phase comparison circuit (12), and outputs the delayed signal.

Description

DLL circuit, time difference amplification circuit, and range finding imaging device

Technical Field

The present disclosure relates to a DLL (Delay-Locked Loop) circuit, a time difference amplification circuit used in the DLL circuit, and a range finding imaging apparatus including the DLL circuit.

Background

Patent document 1 discloses a DLL circuit suitable for a dram (dynamic Random Access memory). Here, the DLL circuit is a circuit that generates a signal of a desired phase using a clock signal supplied from the outside.

(Prior art document)

(patent document)

Patent document 1 Japanese unexamined patent application publication No. 2019-185841

Disclosure of Invention

Problems to be solved by the invention

The conventional technique disclosed in patent document 1 has a problem that it is difficult to adjust a minute phase difference.

Accordingly, an object of the present disclosure is to provide a DLL circuit, a time difference amplification circuit, and a range finding imaging device capable of adjusting a minute phase difference.

Means for solving the problems

A DLL (Delay-Locked Loop) circuit according to an aspect of the present disclosure includes: a time difference amplification circuit that performs amplification processing on a 1 st signal and a 2 nd signal that are input, that is, amplifies a time difference between an edge that is a change point of a logic level included in the 1 st signal and an edge that is a change point of a logic level included in the 2 nd signal, and outputs the resultant 1 st amplified signal and 2 nd amplified signal; a phase comparison circuit that calculates a phase difference between the 1 st amplified signal and the 2 nd amplified signal output from the time difference amplification circuit and outputs a phase difference signal indicating the calculated phase difference; and a variable delay circuit that delays the 2 nd signal and outputs the delayed signal, wherein a delay amount of the 2 nd signal depends on a phase difference indicated by the phase difference signal output from the phase comparison circuit.

A time difference amplifier circuit according to an aspect of the present disclosure is a time difference amplifier circuit provided in the DLL circuit.

A distance measurement imaging device according to an aspect of the present disclosure includes: a light receiving unit that performs photoelectric conversion; the DLL circuit described above; and a timing control circuit that gives the 2 nd signal to the DLL circuit, wherein the DLL circuit outputs the delayed signal to at least one of a light source driving circuit that drives a light source for distance measurement and an exposure driving circuit that drives the light receiving unit for exposure, and receives a feedback signal output from the at least one of the light source driving circuit and the exposure driving circuit as the 1 st signal.

Effects of the invention

The present disclosure provides a DLL circuit, a time difference amplification circuit, and a range finding imaging device capable of adjusting a minute phase difference.

Drawings

Fig. 1 is a block diagram showing a configuration of a general DLL circuit.

Fig. 2 is a diagram for explaining a problem in the general DLL circuit shown in fig. 1.

Fig. 3 is a block diagram showing the configuration of the DLL circuit according to embodiment 1.

Fig. 4 shows characteristic operations of the DLL circuit according to embodiment 1.

Fig. 5 is a block diagram showing a detailed configuration of a time difference amplification circuit provided in the DLL circuit according to embodiment 1.

Fig. 6 is a timing chart showing the operation of the time difference amplification circuit shown in fig. 5.

Fig. 7 shows on/off states of the 1 st to 6 th switches of the time difference amplification circuit in the periods t1 to t3 shown in fig. 6.

Fig. 8 is a block diagram showing the configuration of the distance measuring and imaging device according to embodiment 2.

Detailed Description

First, before explaining the DLL circuit according to the present disclosure, a general DLL circuit will be explained.

Fig. 1 is a block diagram showing a configuration of a general DLL circuit 100. The DLL circuit 100 is a circuit that generates a delayed signal delayed by a required phase with respect to an input clock signal, and the DLL circuit 100 includes a phase comparison circuit 101 and a variable delay circuit 102, the phase comparison circuit 101 compares a phase difference between the input clock signal and the delayed signal, and the variable delay circuit 102 delays the input clock signal by a delay amount that depends on the phase difference indicated by the phase difference signal output from the phase comparison circuit 101 and outputs the delayed signal.

The DLL circuit 100 having such a configuration generates a delayed signal that is synchronized with the input clock signal and is delayed by a desired phase with respect to the input clock signal.

However, the general DLL circuit 100 has a problem that it is difficult to adjust a minute phase difference.

Fig. 2 is a diagram for explaining a problem of the general DLL circuit 100 shown in fig. 1. Here, characteristics of the phase comparison circuit 101 included in the general DLL circuit 100 are shown. The horizontal axis represents the phase difference between the two signals input to the phase comparison circuit 101, and the vertical axis represents the phase difference signal (here, output pulse width) output from the phase comparison circuit 101.

It is desirable that the phase difference signal increases in proportion to the phase difference, but since there is a dead zone for the input of a slight phase difference in the phase comparison circuit 101, a phase difference signal showing zero is output for the input of a slight phase difference as shown in fig. 2. Thus, it is difficult to adjust a minute phase difference in the general DLL circuit 100.

Accordingly, an object of the present disclosure is to provide a DLL circuit, a time difference amplification circuit, and a distance measuring and imaging device that can adjust a minute phase difference.

Embodiments of a DLL circuit, a time difference amplification circuit, and a range finding imaging device according to the present disclosure will be described below with reference to the drawings. In addition, the embodiments to be described below are each a specific example showing the present disclosure. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components, driving timings, and the like shown in the following embodiments are merely examples, and the present disclosure is not limited thereto. Also, the drawings are not intended to be strictly schematic. In each drawing, a repetitive description will be omitted or simplified for substantially the same configuration.

(embodiment mode 1)

Fig. 3 is a block diagram showing the configuration of the DLL circuit 10 according to embodiment 1. The DLL circuit 10 is a circuit that generates a delayed signal delayed by a desired phase with respect to an input clock signal, and includes a time difference amplifier circuit 11, a phase comparator circuit 12, and a variable delay circuit 13.

The time difference amplification circuit 11 is a circuit that amplifies a time difference (i.e., a phase difference) between an edge that is a change point of a logic level included in the 1 st signal and an edge that is a change point of a logic level included in the 2 nd signal with respect to the 1 st signal (here, a delayed signal output from the DLL circuit 10) that is input and the 2 nd signal (here, an input clock signal), and outputs the 1 st amplified signal and the 2 nd amplified signal that are obtained. The output of the time difference amplifier circuit 11 is not necessarily formed by two physically independent signals (the 1 st amplified signal and the 2 nd amplified signal), and may be a single signal as long as it can represent the time difference after amplification. For example, the amplified time difference may be a signal shown during a rising edge and a falling edge.

The phase comparison circuit 12 is a circuit that calculates a phase difference between the 1 st amplified signal and the 2 nd amplified signal output from the time difference amplification circuit 11, and outputs a phase difference signal indicating the calculated phase difference. In the present embodiment, the phase difference signal is composed of two signals for causing the charge pump circuit 13a to function as a current provider and a current sink, respectively, as shown in fig. 3. The output of the phase comparison circuit 12 is not necessarily formed by two physically independent signals, and may be a single signal as long as the charge pump circuit 13a can be switched as a current provider and a current sink.

The variable delay circuit 13 is a circuit that delays the 2 nd signal by a delay amount depending on the phase difference indicated by the phase difference signal output from the phase comparison circuit 12, and outputs the delayed signal to the outside and the time difference amplification circuit 11. The variable delay circuit 13 is configured by a charge pump circuit 13a, a loop filter circuit 13b, and a delay adjustment circuit 13c, the charge pump circuit 13a outputs a current corresponding to a phase difference indicated by the phase difference signal output from the phase comparison circuit 101, the loop filter circuit 13b stores or discharges electricity in accordance with the current output from the charge pump circuit 13a, and the delay adjustment circuit 13c delays the 2 nd signal in accordance with the voltage output from the loop filter circuit 13 b.

The charge pump circuit 13a is configured by, for example, a current source functioning as a current provider and a switching element for turning on or off the current source, and a current source functioning as a current sink and a switching element for turning on or off the current source, in accordance with the phase difference signal (two signals) output from the phase comparison circuit 101.

The loop filter circuit 13b is configured by, for example, a capacitor that stores or discharges electric power in accordance with the electric current discharged and drawn by the charge pump circuit 13 a.

The delay adjustment circuit 13c is configured by, for example, a plurality of buffer amplifiers connected in multiple stages, and a variable current source that changes the current supplied to each of the plurality of buffer amplifiers in accordance with the voltage output from the loop filter circuit 13 b.

With the DLL circuit 10 according to the present embodiment having the above configuration, the time difference between the input 1 st signal and the input 2 nd signal is amplified in the time difference amplifying circuit 11, the phase difference signal indicating the phase difference between the 1 st amplified signal and the 2 nd amplified signal output from the time difference amplifying circuit 11 is output in the phase comparing circuit 12, and the 2 nd signal is delayed by the variable delay circuit 13 by a delay amount depending on the phase difference indicated by the phase difference signal output from the phase comparing circuit 12, is output to the outside as a delayed signal, and is fed back to the time difference amplifying circuit 11.

In this way, in the DLL circuit 10 according to the present embodiment, the time difference between two input signals is amplified in the time difference amplifying circuit 11, and then the amplified signals are input to the phase comparing circuit 12. Accordingly, even if the phase difference between the two input signals is small, the phase difference is enlarged beyond the dead zone of the phase comparison circuit 12, and the phase comparison is performed, so that the DLL circuit 10 capable of adjusting the small phase difference is realized as compared with the general DLL circuit 100 not including the time difference amplification circuit.

Fig. 4 shows characteristic operations of the DLL circuit 10 according to embodiment 1. That is, this diagram corresponds to fig. 2 illustrating a general DLL circuit 100. By the DLL circuit 10, the time difference between the two input signals is amplified in the time difference amplifying circuit 11. Therefore, as shown in fig. 4, in the phase comparison circuit 12, a phase difference signal corresponding to the minute phase difference (here, a pulse signal having a width corresponding to the phase difference) is output, that is, a phase difference signal corresponding to the amplified phase difference is output. Thus, even if the phase difference between the two input signals is small, the occurrence of a dead zone can be suppressed, and a delay corresponding to the phase difference can be reliably performed, thereby realizing the DLL circuit 10 capable of adjusting the small phase difference.

Fig. 5 is a block diagram showing a detailed configuration of the time difference amplification circuit 11 included in the DLL circuit 10 according to embodiment 1. The time difference amplification circuit 11 includes a plurality of current sources (a 1 st current source 30a, a 2 nd current source 31a, a 3 rd current source 30b, and a 4 th current source 31b), and a control circuit (a 1 st slew rate control circuit 20a and a 2 nd slew rate control circuit 20b) that switches between a large current mode in which at least two of the plurality of current sources are operated and a small current mode in which only one of the plurality of current sources is operated, according to a combination of logic levels of a 1 st signal and a 2 nd signal that are input.

More specifically, the 1 st slew rate control circuit 20a includes: 1

st inverters

21a and 22a, 1 st switch 23a, 2 nd switch 24a, 3 rd switch 25a, 1 st threshold setting circuit 26a, 1 st comparator 27a, and 1 st capacitor 28 a.

The 1

st inverters

21a and 22a are logic circuits that invert the logic level of the 1 st signal that is input.

The 1 st switch 23a is a switch turned on and off by the logic level of the 1 st signal, and has one end connected to the 3 rd switch 25a, the 1 st capacitor 28a, and the 1 st input terminal, i.e., the negative input terminal, of the 1 st comparator 27a, and the other end connected to the 2 nd switch 24 a.

The 2 nd switch 24a is turned on or off by the logic level of the output signal from the 2 nd inverter 22b (i.e., a signal obtained by inverting the logic level of the 2 nd signal) included in the 2 nd slew rate control circuit 20b, one end of the 2 nd switch 24a is connected to the 1 st current source 30a and the other end of the 1 st switch 23a, and the other end of the 2 nd switch 24a is connected to the 2 nd current source 31 a.

The 3 rd switch 25a is turned on or off by the logic level of the output signal from the 1 st inverter 21a, and one end of the 3 rd switch 25a is connected to the power supply potential VDD and the other end is connected to the 1 st capacitor 28a and the like. In the present embodiment, the 1 st switch 23a, the 2 nd switch 24a, and the 3 rd switch 25a are all turned on when a High, which is a logic level, is input.

The 1 st capacitor 28a is a capacitor having a capacity C, and has one end connected to the reference potential, the other end connected to the 1 st current source 30a via the 1 st switch 23a, and the 2 nd current source 31a via the 1 st switch 23a and the 2 nd switch 24 a.

The 1 st threshold setting circuit 26a is a voltage source that outputs a predetermined voltage Vth as a threshold voltage to the positive input terminal, which is the 2 nd input terminal of the 1 st comparator 27 a.

The 1 st comparator 27a compares the voltage of the 1 st capacitor 28a connected to the negative input terminal with a predetermined voltage Vth (i.e., threshold voltage) output from the 1 st threshold setting circuit 26a supplied to the positive input terminal, and outputs the comparison result as a 1 st amplified signal.

The 2 nd slew rate control circuit 20b includes: 2

nd inverters

21b and 22b, 4 th switch 23b, 5 th switch 24b, 6 th switch 25b, 2 nd threshold setting circuit 26b, 2 nd comparator 27b, and 2 nd capacitor 28 b.

The 2

nd inverters

21b and 22b are logic circuits that invert the logic level of the 2 nd signal that is input.

The 4 th switch 23b is a switch turned on or off by the logic level of the 2 nd signal, and has one end connected to the 6 th switch 25b, the 2 nd capacitor 28b, and the negative input terminal, which is the 1 st input terminal of the 2 nd comparator 27b, and the other end connected to the 5 th switch 24 b.

The 5 th switch 24b is turned on or off by the logic level of the output signal from the 1 st inverter 22a included in the 1 st slew rate control circuit 20a (i.e., a signal obtained by inverting the logic level of the 1 st signal), one end of the 5 th switch 24b is connected to the 3 rd current source 30b and the other end of the 4 th switch 23b, and the other end of the 5 th switch 24b is connected to the 4 th current source 31 b.

The 6 th switch 25b is turned on or off by the logic level of the output signal from the 2 nd inverter 21b, and one end of the 6 th switch 25b is connected to the power supply potential VDD and the other end is connected to the 2 nd capacitor 28b and the like. In the present embodiment, the 4 th switch 23b, the 5 th switch 24b, and the 6 th switch 25b are all turned on when a High is input as a logic level.

The 2 nd capacitor 28b is a capacitor having a capacity C, and one end of the 2 nd capacitor 28b is connected to the reference potential, and the other end is connected to the 3 rd current source 30b via the 4 th switch 23b and the 4 th current source 31b via the 4 th switch 23b and the 5 th switch 24 b.

The 2 nd threshold setting circuit 26b is a voltage source that outputs a predetermined voltage Vth as a threshold voltage to the positive input terminal that is the 2 nd input terminal of the 2 nd comparator 27 b.

The 2 nd comparator 27b compares the voltage of the 2 nd capacitor 28b connected to the negative input terminal with a predetermined voltage Vth (i.e., threshold voltage) supplied to the positive input terminal and output from the 2 nd threshold setting circuit 26b, and outputs the comparison result as a 2 nd amplified signal.

In the present embodiment, the output currents of the 1 st current source 30a and the 3 rd current source 30b are represented by i_SI represents the output current of each of the 2 nd current source 31a and the 4 th current source 31b_L。

Fig. 6 is a timing chart showing the operation of the time difference amplification circuit 11 shown in fig. 5. Fig. 6 (a) shows a voltage waveform of the 1 st signal, fig. 6 (b) shows a voltage waveform of the 2 nd signal, fig. 6 (c) shows a voltage waveform of the negative input terminal of the 1 st comparator 27a, fig. 6 (d) shows a voltage waveform of the negative input terminal of the 2 nd comparator 27b, fig. 6 (e) shows a voltage waveform of the output terminal (i.e., the 1 st amplified signal) of the 1 st comparator 27a, and fig. 6 (f) shows a voltage waveform of the output terminal (i.e., the 2 nd amplified signal) of the 2 nd comparator 27 b.

Fig. 7 is a diagram (table) showing on/off states of the 1 st switch 23a to the 6 th switch 25b of the time-difference amplification circuit 11 in the periods t1 to t3 shown in fig. 6.

As shown in fig. 6 (a) and (b), the logic level of the 1 st signal starts to change (from Low to High) first, and thereafter, the logic level of the 2 nd signal starts to change (from Low to High), and a positive phase difference occurs. That is, as shown in fig. 6 (a), the 1 st signal is Low during the period t1 and High after the period t 2. As shown in fig. 6 (b), the 2 nd signal is Low during the period t1 and the period t2, and High after the period t 3.

In this way, in the period t1, since both the 1 st signal and the 2 nd signal are Low, the 1 st switch 23a and the 4 th switch 23b are off, and the 2 nd switch 24a, the 3 rd switch 25a, the 5 th switch 24b, and the 6 th switch 25b are on, as shown in a period t1 of fig. 7.

In this way, in the 1 st slew rate control circuit 20a, since the 3 rd switch 25a is turned on and the 1 st switch 23a is turned off, the 1 st capacitor 28a is connected to the power supply potential VDD via the 3 rd switch 25a and is charged. Therefore, the voltage at the negative input terminal of the 1 st comparator 27a connected to the 1 st capacitor 28a becomes the power supply potential VDD ((c) of fig. 6). Accordingly, the 1 st comparator 27a outputs a Low level as a 1 st amplified signal because the voltage VDD at the negative input terminal is higher than the voltage Vth at the positive input terminal ((e) of fig. 6).

Similarly, in the 2 nd slew rate control circuit 20b, since the 6 th switch 25b is turned on and the 4 th switch 23b is turned off, the 2 nd capacitor 28b is connected to the power supply potential VDD via the 6 th switch 25b and is charged. Therefore, the voltage at the negative input terminal of the 2 nd comparator 27b connected to the 2 nd capacitor 28b becomes the power supply potential VDD ((d) of fig. 6). Accordingly, the 2 nd comparator 27b outputs a Low level as a 2 nd amplified signal because the voltage VDD at the negative input terminal is higher than the voltage Vth at the positive input terminal ((f) of fig. 6).

Next, in the period t2, since the 1 st signal becomes High, the 1 st switch 23a is turned on and the 3 rd switch 25a and the 5 th switch 24b are turned off (the other switches are maintained as they are) as shown in the period t2 in fig. 7.

In this way, in the 1 st slew rate control circuit 20a, since the 3 rd switch 25a is turned off and the 1 st switch 23a and the 2 nd switch 24a are turned on, the 1 st capacitor 28a is connected to the 1 st current source 30a and the 2 nd current source 31a (large current mode), and the total output current (i) of the 1 st current source 30a and the 2 nd current source 31a is set to be the total output current (i)_S+i_L) The discharge starts rapidly ((c) of fig. 6).

In the 2 nd slew rate control circuit 20b, since the states of the 6 th switch 25b and the 4 th switch 23b are maintained, the voltage of the negative input terminal of the 2 nd comparator 27b does not change ((d) of fig. 6), and the output voltage (the 2 nd amplified signal) of the 2 nd comparator 27b does not change ((f) of fig. 6).

Next, in the period t3, since the 2 nd signal becomes High, the 2 nd switch 24a and the 6 th switch 25b are turned off and the 4 th switch 23b is turned on (the other switches are maintained as they are) as shown in the period t3 in fig. 7.

Thus, in the 1 st slew rate control circuit 20a, since the 2 nd switch 24a becomes off,therefore, the 1 st capacitor 28a is switched to be connected to only the 1 st current source 30a (small current mode), and is switched to the output current (i) based on the 1 st current source 30a_S) The discharge is gentle ((c) of fig. 6). After that, when the voltage at the negative input terminal of the 1 st comparator 27a falls to a predetermined voltage Vth (threshold voltage at the positive input terminal), a High level is output from the 1 st comparator 27a as a 1 st amplified signal ((e) of fig. 6). In this way, from the period t2 to the period t3, the large current mode is switched to the small current mode (the 1 st current source 30a is kept on, and only the 2 nd current source 31a is turned off) in a continuous time, and therefore, the time difference can be amplified for a small input time difference.

In the 2 nd slew rate control circuit 20b, since the 6 th switch 25b is turned off, the 4 th switch 23b is turned on, and the 5 th switch 24b is kept off, the 2 nd capacitor 28b is connected to only the 3 rd current source 30b (low current mode), and the output current (i) by the 3 rd current source 30b starts (i.e., low current mode)_S) The discharge is gentle ((d) of fig. 6). After that, when the voltage at the negative input terminal of the 2 nd comparator 27b falls to a predetermined voltage Vth (threshold voltage at the positive input terminal), a High level is output from the 2 nd comparator 27b as a 2 nd amplified signal ((f) of fig. 6).

Thus, the 1 st signal and the 2 nd signal have a waveform in which the logic level changes (i.e., rises) by a very short period t2, and the 1 st capacitor 28a passes a large current mode (i.e., a current (i) flows through the 1 st slew rate control circuit 20a during the period t2_S+i_L) In addition, the 2 nd capacitor 28b is not discharged in the 2 nd slew rate control circuit 20 b. Then, in the following period t3, in the 1 st slew rate control circuit 20a and the 2 nd slew rate control circuit 20b, the 1 st capacitor 28a and the 2 nd capacitor 28b are respectively in the small current mode (i.e., in the current (i)_S) To perform a gentle discharge.

Therefore, the timing when the input voltage of the 1 st comparator 27a (i.e., the voltage of the negative input terminal) reaches the threshold voltage (i.e., the voltage Vth of the positive input terminal) and the timing when the input voltage of the 2 nd comparator 27b (i.e., the voltage of the negative input terminal) reaches the threshold voltage (i.e., the voltage of the positive input terminal) are both equal to each otherVoltage Vth) is larger than period t 2. In this way, the time difference (i.e., the output time difference Δ t) between the timing at which the 1 st amplified signal output from the 1 st comparator 27a becomes High and the timing at which the 2 nd amplified signal output from the 2 nd comparator 27b becomes High_out) The time period becomes a period t2 (input time difference Δ t)_in) Amplified time difference.

In the above example, although the positive phase difference in which the logic level of the 1 st signal is changed first and then the logic level of the 2 nd signal is changed is input, the negative phase difference in which the logic level of the 2 nd signal is changed first and then the logic level of the 1 st signal is changed may be input, and this is only a case in which the operation of the 1 st slew rate control circuit 20a and the operation of the 2 nd slew rate control circuit 20b are alternated, and the input time difference (i.e., the input phase difference) is amplified by performing the same processing. This is because the 1 st slew rate control circuit 20a and the 2 nd slew rate control circuit 20b basically have the same configuration.

Next, the characteristics of the time difference amplifier circuit 11 that performs the above operation will be quantitatively described.

As can be seen from fig. 6, when the input time difference (i.e., the time difference between the rising edges of the 1 st signal and the 2 nd signal, the period t2) is Δ tin and the output time difference (i.e., the time difference between the rising edges of the 1 st amplified signal and the 2 nd amplified signal) is Δ tout, the time difference amplification factor G is a ratio of Δ tin and Δ tout_tRepresented by the following formula 1.

[ numerical formula 1]

I.e. time difference amplification G_tIt can also be said that the discharge current (i) of the 1 st capacitor 28a in the large current mode_S+i_L) And discharge current (i) of the 1 st capacitor 28a and the 2 nd capacitor 28b in the small current mode_S) The ratio of (a) to (b).

Thus, the time difference magnification G_tIs determined by the ratio of the output currents of the two current sources. Therefore, the DLL circuit 10 including the time difference amplifier circuit 11 can perform high-resolution phase adjustment that is less susceptible to the temperature characteristic.

In equation 1, the input voltage (i.e., the voltage at the negative input terminal) of the 1 st comparator 27a is in the period t2 (i.e., the input time difference Δ t)_in) However, the case where the threshold voltage (i.e., the voltage Vth of the positive input terminal) is not reached, that is, the case where the input time difference is within the non-saturation region, is satisfied.

In contrast, the input voltage (i.e., the voltage at the negative input terminal) of the 1 st comparator 27a is in the period t2 (i.e., the input time difference Δ t)_in) When the time difference reaches the threshold voltage (i.e., the voltage Vth of the positive input terminal), that is, when the time difference of the input signal is in the saturation region, the time difference amplification factor G_tRepresented by the following formula 2.

[ numerical formula 2]

I.e. time difference amplification G_tBecomes dependent on the input time difference Δ t_inThe value of (c).

As can be seen from the above equations 1 and 2, the input voltage (i.e., the voltage at the negative input terminal) of the 1 st comparator 27a is within the period t2 (i.e., the input time difference Δ t)_in) Whether or not the voltage reaches the threshold voltage (i.e., the voltage Vth of the positive input terminal), the time difference amplification factor Gt becomes independent of the input time difference Deltat_inOr (equation 1) or depends on the input time difference Δ t_inThe value of (equation 2). Namely, the time difference amplification circuit 11 performs nonlinear amplification.

Here, as described above, the time difference amplification circuit 11 can operate with respect to the positive and negative input phase differences, and the input voltage (i.e., the voltage at the negative input terminal) of the 1 st comparator 27a is set to the input time difference Δ t (i.e., the input time difference Δ t) during the period t2_in) When the voltage reaches a threshold voltage (i.e., voltage Vth of positive input terminal), the line is connectedSex amplification. That is, when the following expression 3 is satisfied, linear amplification is performed based on the above expression 1.

[ numerical formula 3]

As is clear from equation 3, the threshold voltage Vth of the 1 st comparator 27a and the 2 nd comparator 27b is set by the 1 st threshold setting circuit 26a and the 2 nd threshold setting circuit 26b, and the input time difference range which is linearly amplified can be adjusted. Here, the input time difference range is a range of time differences in which the time difference amplification circuit 11 can amplify the time difference. The input time difference range can be said to be a value (i) depending on the current output from each of the plurality of current sources_SAnd i_L) To be determined.

As described above, the DLL circuit 10 according to the present embodiment includes: a time difference amplification circuit 11 that performs amplification processing on the input 1 st and 2 nd signals, that is, amplifies a time difference between an edge that is a change point of a logic level included in the 1 st signal and an edge that is a change point of a logic level included in the 2 nd signal, and outputs the resultant 1 st and 2 nd amplified signals; a phase comparison circuit 12 that calculates a phase difference between the 1 st amplified signal and the 2 nd amplified signal output from the time difference amplification circuit 11, and outputs a phase difference signal indicating the calculated phase difference; and a variable delay circuit 13 for delaying the 2 nd signal by a delay amount depending on the phase difference indicated by the phase difference signal outputted from the phase comparison circuit 12 and outputting the delayed signal.

Accordingly, the two input signals are amplified by the time difference amplification circuit 11 for a time difference and then input to the phase comparison circuit 12. Therefore, even if the phase difference between the two input signals is small, the phase difference is enlarged to the outside of the dead zone of the phase comparison circuit 12 and compared, and therefore, the DLL circuit 10 capable of adjusting the small phase difference is realized as compared with the general DLL circuit 100 not including the time difference amplification circuit.

In addition, the variable delay circuit 13 has: a charge pump circuit 13a that outputs a current corresponding to the phase difference; a loop filter circuit 13b that stores or discharges electric power in accordance with the current output from the charge pump circuit 13 a; and a delay adjusting circuit 13c for delaying the 2 nd signal in accordance with the voltage output from the loop filter circuit 13 b. In this way, the variable delay circuit 13 is realized to delay the 2 nd signal by a delay amount depending on the phase difference indicated by the phase difference signal output from the phase comparison circuit 12, and output the delayed signal.

The time difference amplifier circuit 11 includes a plurality of current sources (a 1 st current source 30a, a 2 nd current source 31a, a 3 rd current source 30b, and a 4 th current source 31b), and a control circuit (a 1 st slew rate control circuit 20a and a 2 nd slew rate control circuit 20b) that switches between a large current mode in which at least two of the plurality of current sources are operated and a small current mode in which only one of the plurality of current sources is operated, according to a combination of logic levels of a 1 st signal and a 2 nd signal. Accordingly, the time difference amplifier circuit 11 for amplifying the input time difference is realized by dynamically changing the number of current sources used.

The amplification factor based on the time difference of the time difference amplification circuit 11 and the input time difference range depend on the value (i) of the current output from each of the plurality of current sources_SAnd i_L) The input time difference range is determined as a range of time differences in which the time difference amplification circuit 11 can linearly amplify the time difference. Accordingly, the time difference amplification factor and the input time difference range of the time difference amplification circuit 11 can be set to desired values by the output currents of the plurality of current sources provided in the time difference amplification circuit 11.

The plurality of current sources include a 1 st current source 30a and a 2 nd current source 31a, the control circuit includes a 1 st slew rate control circuit 20a, the 1 st slew rate control circuit 20a includes a 1 st capacitor 28a, a 1 st switch 23a, and a 2 nd switch 24a, the 1 st switch 23a turns on or off the connection of the 1 st capacitor 28a with the 1 st current source 30a and the 2 nd current source 31a according to a logic level of a 1 st signal, and the 2 nd switch 24a switches whether or not the 2 nd current source 31a is operated according to a logic level of a 2 nd signal. Here, the 1 st slew rate control circuit 20a further includes a 1 st comparator 27a and a 3 rd switch 25a that switches on and off in accordance with the logic level of the 1 st signal, the 3 rd switch 25a, the 1 st capacitor 28a, and the 1 st input terminal (negative input terminal) of the 1 st comparator 27a are connected to one end of the 1 st switch 23a, one end of the 2 nd switch 24a and the 1 st current source 30a are connected to the other end of the 1 st switch 23a, and the 2 nd current source 31a is connected to the other end of the 2 nd switch 24 a.

Accordingly, since the 2 nd current source 31a is switched from on to off in a state where the 1 st current source 30a is turned on, and is switched from the large current mode to the small current mode, the current value can be smoothly reduced in a continuous time, and a minute time difference can be amplified, as compared with a switching method in which both current sources are turned on or off.

Then, the 1 st slew rate control circuit 20a further includes a 1 st threshold setting circuit 26a, and outputs a predetermined voltage to the 2 nd input terminal (positive input terminal) of the 1 st comparator 27 a. Accordingly, by setting the threshold voltage Vth of the 1 st comparator 27a, the input time difference range which is linearly amplified can be adjusted.

The plurality of current sources further includes a 3 rd current source 30b and a 4 th current source 31b, the control circuit further includes a 2 nd slew rate control circuit 20b, the 2 nd slew rate control circuit 20b includes a 2 nd capacitor 28b, a 4 th switch 23b, and a 5 th switch 24b, the 4 th switch 23b turns on or off the connection of the 2 nd capacitor 28b with the 3 rd current source 30b and the 4 th current source 31b according to the logic level of the 2 nd signal, and the 5 th switch 24b switches whether or not to operate the 4 th current source 31b according to the logic level of the 1 st signal. Here, the 2 nd slew rate control circuit 20b further includes a 2 nd comparator 27b and a 6 th switch 25b that performs on/off switching according to a logic level of the 2 nd signal, the 6 th switch 25b, the 2 nd capacitor 28b, and a 1 st input terminal (negative input terminal) of the 2 nd comparator 27b are connected to one end of a 4 th switch 23b, one end of a 5 th switch 24b and a 3 rd current source 30b are connected to the other end of the 4 th switch 23b, and a 4 th current source 31b is connected to the other end of the 5 th switch 24 b.

Accordingly, since the large current mode can be switched to the small current mode by switching the 4 th current source 31b from on to off with the 3 rd current source 30b in an on state, the current value can be smoothly reduced in a continuous time as compared with a switching method in which both current sources are switched on or off, and a minute time difference can be amplified.

The 2 nd slew rate control circuit 20b further includes a 2 nd threshold setting circuit 26b that outputs a predetermined voltage to the 2 nd input terminal (positive input terminal) of the 2 nd comparator 27 b. Accordingly, by setting the threshold voltage Vth of the 2 nd comparator 27b, the input time difference range which is linearly amplified can be adjusted.

(embodiment mode 2)

Fig. 8 is a block diagram showing the configuration of the distance measuring and imaging device 50 according to embodiment 2. The range-finding imaging apparatus 50 is an apparatus that generates a range image by imaging, and includes a DLL circuit 10a, a PLL (Phase-Locked Loop) circuit 51, a timing control circuit 52, a light receiving unit 53, an exposure drive circuit 54, a vertical scan circuit 55, a column AD converter 56, a signal processing circuit 57, and an output interface 58. In this figure, the light source 40 and the light source driving circuit 41 are also shown in conjunction with the distance measuring and imaging device 50.

The PLL circuit 51 supplies a clock synchronized with a clock input from the outside to the timing control circuit 52.

The timing control circuit 52 includes a light emission/exposure control unit 52a and an image pickup control unit 52b, the light emission/exposure control unit 52a operates in synchronization with a clock supplied from the PLL circuit 51, transmits and receives a horizontal drive signal HD and a vertical drive signal VD to and from the outside, and supplies a clock signal for controlling light emission and exposure to the DLL circuit 10a, and the image pickup control unit 52b supplies control signals to the vertical scanning circuit 55, the column AD converter 56, the signal processing circuit 57, and the output interface 58.

The DLL circuit 10a includes two DLL circuits 10 according to embodiment 1. One DLL circuit 10 outputs a clock signal for light emission output from the timing control circuit 52 as a 2 nd signal, a drive signal output from the light source drive circuit 41 as a 1 st signal, and a delayed signal as a light emission control signal to the light source drive circuit 41. The other DLL circuit 10 outputs the clock signal for exposure output from the timing control circuit 52 as the 2 nd signal, the exposure feedback signal output from the exposure drive circuit 54 as the 1 st signal, and the delayed signal as the exposure control signal to the exposure drive circuit 54.

The light source driving circuit 41 is a circuit for outputting a driving signal for causing the light source 40 to emit light to the light source 40 and the DLL circuit 10a in accordance with the light emission control signal output from the DLL circuit 10 a.

The light source 40 is an LED or the like, and emits light such as infrared light to an object to be measured when receiving a drive signal from the light source drive circuit 41.

The exposure driving circuit 54 is a circuit that supplies a driving signal for exposing the light receiving section 53 to the light receiving section 53 in accordance with an exposure control signal output from the DLL circuit 10a, and outputs the driving signal to the DLL circuit 10a as an exposure feedback signal.

The light receiving unit 53 is a pixel array in which pixels including light receiving elements are arranged in a two-dimensional manner.

The vertical scanning circuit 55 is a circuit that outputs a control signal for reading out signal charges accumulated in the pixels for each row of the light receiving sections 53.

The column AD converter 56 is a circuit configured by an a/D converter provided corresponding to each column of the light receiving section 53, and converts analog signal charges read from the pixels of the light receiving section 53 into digital values.

The signal processing circuit 57 is a processor, a memory, or the like, and temporarily stores the digital values output from the column AD converter 56, and calculates the distance to the subject for each pixel of the light receiving unit 53 by performing an operation for distance measurement, thereby generating a distance image. The distance may be calculated by, for example, a tof (time of flight) method, in which pulsed light is emitted from the light source 40, and the time until the reflected light returns is measured by the light receiving unit 53.

The output Interface 58 is an Interface circuit such as HDMI (High-Definition Multimedia Interface) for outputting the distance image generated by the signal processing circuit 57 to the outside.

In the distance measuring and imaging apparatus 50 according to the present embodiment having the above-described configuration, the light source driving circuit 41 is provided in the feedback loop (path for inputting the delayed signal as the 1 st signal) of the DLL circuit 10a, and the pulsed light from the light source 40 is continuously emitted with high timing accuracy in accordance with the fine phase difference adjustment. An exposure drive circuit 54 is provided in a feedback loop (a path for inputting the delayed signal as the 1 st signal) of the DLL circuit 10a, and exposure at the light receiving unit 53 is performed with high timing accuracy in accordance with a minute phase difference adjustment.

As described above, the distance measurement imaging device 50 according to the present embodiment includes: a light receiving unit 53 that performs photoelectric conversion, a DLL circuit 10a according to embodiment 1, and a timing control circuit 52 that gives a 2 nd signal to the DLL circuit 10a, and the DLL circuit 10a outputs a delayed signal to at least one of a light source driving circuit 41 that drives a light source for distance measurement and an exposure driving circuit 54 that drives the light receiving unit 53 for exposure, and receives a feedback signal output from at least one of the light source driving circuit and the exposure driving circuit as a 1 st signal.

Accordingly, since the DLL circuit 10a capable of adjusting a minute phase difference is used, the distance measurement imaging apparatus 50 capable of performing stable distance measurement with high accuracy can be realized.

The DLL circuit, the time difference amplification circuit, and the range finding imaging device according to the present disclosure have been described above based on embodiments 1 and 2, but the present disclosure is not limited to these embodiments. The present disclosure includes various modifications that may be made by those skilled in the art to the embodiments and other embodiments in which some of the components in the embodiments are combined, without departing from the scope of the present disclosure.

For example, in the above-described embodiment, the time difference amplification circuit 11 has two current sources for one slew rate control circuit, but is not limited thereto, and may have three or more current sources. The number of current sources used in the large current mode and the small current mode may be switched.

In the time difference amplifier circuit 11 of the above-described embodiment, the output currents of the 1 st current source 30a and the 3 rd current source 30b are i_SThe output currents of the 2 nd current source 31a and the 4 th current source 31b are i_LThe relationship between these two output currents may be i_S＝i_LMay also be i_S≠i_L. In either case, by using two current sources, a larger current can be output than in the case of using one current source.

In the above-described embodiment, the time difference amplification circuit 11 amplifies the time difference by discharging the electric charge previously charged in the capacitor by the current source, or conversely, amplifies the time difference by charging the capacitor previously held at a constant voltage by the current source.

In the time difference amplifying circuit 11, the 1 st threshold setting circuit 26a, and the 2 nd threshold setting circuit 26b in the above-described embodiment each output the threshold voltage Vth, but it is not necessary to output the same threshold voltage Vth, and the voltages output from the respective circuits may be set to desired values in consideration of the amplification factor with respect to the positive and negative phase differences. When both the 1 st threshold setting circuit 26a and the 2 nd threshold setting circuit 26b output the same threshold voltage, the 1 st threshold setting circuit 26a and the 2 nd threshold setting circuit 26b may be realized by a common threshold setting circuit.

In the time lag amplifier circuit 11 of the above-described embodiment, the capacitor is connected to the negative input terminal of the comparator, and the threshold setting circuit is connected to the positive input terminal, but the threshold setting circuit may be connected to the negative input terminal of the comparator, and the capacitor may be connected to the positive input terminal. Even in such a connection method, the logic of the amplified signal output from the comparator is merely inverted, and the information shown by the amplified signal does not change.

Industrial applicability

The DLL circuit, the time difference amplification circuit, and the range finding imaging apparatus according to the present disclosure can be applied to a wide range of applications such as an in-vehicle application, as the DLL circuit, the time difference amplification circuit, and the range finding imaging apparatus capable of adjusting a minute phase difference.

Description of the symbols

10. 10a, 100 DLL circuit

11 time difference amplifying circuit

12. 101 phase comparison circuit

13. 102 variable delay circuit

13a charge pump circuit

13b loop filter circuit

13c delay adjusting circuit

20a 1 st slew rate control circuit

21a, 22a 1 st inverter

23a 1 st switch

24a 2 nd switch

25a 3 rd switch

26a 1 st threshold setting circuit

27a 1 st comparator

28a 1 st capacitor

20b 2 nd slew rate control circuit

21b, 22b 2 nd inverter

23b 4 th switch

24b 5 th switch

25b 6 th switch

26b 2 nd threshold setting circuit

27b 2 nd comparator

28b 2 nd capacitor

30a 1 st Current Source

31a 2 nd current source

30b No. 3 Current Source

31b 4 th Current Source

40 light source

41 light source driving circuit

50 range finding camera device

51 PLL circuit

52 timing control circuit

52a light emission exposure control unit

52b image pickup control unit

53 light receiving part

54 exposure driving circuit

55 vertical scanning circuit

56-column AD converter

57 signal processing circuit

58 output interface

Claims

1. A DLL circuit, which is a Delay-Locked Loop,

the DLL circuit includes:

a time difference amplification circuit that performs amplification processing on a 1 st signal and a 2 nd signal that are input, that is, amplifies a time difference between an edge that is a change point of a logic level included in the 1 st signal and an edge that is a change point of a logic level included in the 2 nd signal, and outputs the resultant 1 st amplified signal and 2 nd amplified signal;

a phase comparison circuit that calculates a phase difference between the 1 st amplified signal and the 2 nd amplified signal output from the time difference amplification circuit and outputs a phase difference signal indicating the calculated phase difference; and

and a variable delay circuit for delaying the 2 nd signal and outputting the delayed signal, wherein the delay amount of the 2 nd signal depends on the phase difference indicated by the phase difference signal output from the phase comparison circuit.

2. The DLL circuit of claim 1,

the variable delay circuit has:

a charge pump circuit that outputs a current corresponding to the phase difference;

a loop filter circuit that stores or discharges electric power in accordance with the current output from the charge pump circuit; and

and a delay adjustment circuit for delaying the 2 nd signal according to the voltage output from the loop filter circuit.

3. The DLL circuit of claim 1 or 2,

the time difference amplification circuit includes:

a plurality of current sources; and

and a control circuit that switches between a large current mode in which at least two of the plurality of current sources are operated and a small current mode in which only one of the plurality of current sources is operated, according to a combination of logic levels of the 1 st signal and the 2 nd signal.

4. The DLL circuit of claim 3,

the amplification factor of the time difference based on the time difference amplification circuit and an input time difference range in which the time difference amplification circuit can linearly amplify the time difference are determined depending on the value of the current output from each of the plurality of current sources.

5. The DLL circuit of claim 3 or 4,

the plurality of current sources includes a 1 st current source and a 2 nd current source,

the control circuit includes a 1 st slew rate control circuit,

the 1 st slew rate control circuit comprises:

a 1 st capacitor;

a 1 st switch that turns on or off connection of the 1 st capacitor to the 1 st current source and the 2 nd current source according to a logic level of the 1 st signal; and

and a 2 nd switch for switching whether or not to operate the 2 nd current source according to a logic level of the 2 nd signal.

6. The DLL circuit of claim 5,

the 1 st slew rate control circuit further comprises:

a 1 st comparator; and

a 3 rd switch for switching ON/OFF according to the logic level of the 1 st signal,

the 1 st switch, the 1 st capacitor, and the 1 st input terminal of the 1 st comparator are connected at one end of the 1 st switch,

the other end of the 1 st switch is connected with one end of the 2 nd switch and the 1 st current source,

the other end of the 2 nd switch is connected with the 2 nd current source.

7. The DLL circuit of claim 6,

the 1 st slew rate control circuit further includes a 1 st threshold setting circuit that outputs a predetermined voltage to the 2 nd input terminal of the 1 st comparator.

8. The DLL circuit of any one of claims 3 to 7,

the plurality of current sources further includes a 3 rd current source and a 4 th current source,

the control circuit further comprises a 2 nd slew rate control circuit,

the 2 nd slew rate control circuit includes:

a 2 nd capacitor;

a 4 th switch for turning on or off the connection of the 2 nd capacitor to the 3 rd current source and the 4 th current source according to a logic level of the 2 nd signal; and

and a 5 th switch for switching whether or not to operate the 4 th current source according to a logic level of the 1 st signal.

9. The DLL circuit of claim 8, wherein the DLL circuit,

the 2 nd slew rate control circuit further comprises:

a 2 nd comparator; and

a 6 th switch for switching ON and OFF according to the logic level of the 2 nd signal,

the 6 th switch, the 2 nd capacitor, and the 1 st input terminal of the 2 nd comparator are connected to one end of the 4 th switch,

the other end of the 4 th switch is connected with one end of the 5 th switch and the 3 rd current source,

the other end of the 5 th switch is connected with the 4 th current source.

10. The DLL circuit of claim 9, wherein the voltage level of the voltage supply is greater than or equal to a predetermined voltage level,

the 2 nd slew rate control circuit further includes a 2 nd threshold setting circuit that outputs a prescribed voltage to the 2 nd input terminal of the 2 nd comparator.

11. A time difference amplification circuit provided in the DLL circuit as claimed in any one of claims 1 to 10.

12. A distance-measuring camera device is provided,

the distance measurement imaging device is provided with:

a light receiving unit that performs photoelectric conversion;

the DLL circuit of any one of claims 1 to 10; and

a timing control circuit that gives the 2 nd signal to the DLL circuit,

the DLL circuit outputs the delayed signal to at least one of a light source driving circuit for driving a light source for distance measurement and an exposure driving circuit for driving the light receiving unit for exposure, and receives a feedback signal output from the at least one as the 1 st signal.