CN113192543B - Sensitive amplifier - Google Patents
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- CN113192543B CN113192543B CN202110499651.XA CN202110499651A CN113192543B CN 113192543 B CN113192543 B CN 113192543B CN 202110499651 A CN202110499651 A CN 202110499651A CN 113192543 B CN113192543 B CN 113192543B
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
Abstract
The present disclosure provides a sense amplifier, which includes a reference current circuit, a comparison current circuit, a current mirror circuit, a phase inverter circuit, a first enable transistor and a clamp transistor 。 The first end of the reference current circuit is connected with the first end of the current mirror circuit, the second end of the reference current circuit is connected with the first end of the phase inverter circuit, the second end of the phase inverter circuit is connected with the second end of the current mirror circuit, the third end of the current mirror circuit is connected with the comparison current circuit, the fourth end of the current mirror circuit is connected with the first end of the clamping transistor, the second end of the clamping transistor is connected with the first end of the first enabling tube, and the second end of the first enabling tube is a bit line current input end; the reference current circuit outputs reference current under the condition of receiving a first control signal sent by the reference current control circuit; the comparison current circuit generates a comparison current when receiving a second control signal sent by the comparison current control circuit. The sensitive amplifier circuit has the advantages of simple structure and lower power consumption.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a sensitive amplifier.
Background
Nowadays, semiconductor memories are widely used in various electronic products, and a sense amplifier is an important component of the semiconductor memory and directly affects the read/write speed of the semiconductor memory.
With the increasing growth of industries related to Edge Computing (Edge Computing) application fields, such as Augmented reality (Augmented reality), auto-driven vehicles (auto vehicles), and unmanned planes (Drones), the requirements for read-write circuits of semiconductor memories are increasing. Therefore, how to design a sense amplifier with high precision, low power consumption and small area becomes a technical problem which needs to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above problems, the present invention provides a sense amplifier which overcomes or at least partially solves the above problems, and the technical solution is as follows:
a sense amplifier, comprising: the circuit comprises a reference current circuit, a comparison current circuit, a current mirror circuit, an inverter circuit, a first enabling tube and a clamping transistor;
the first end of the reference current circuit is connected with the first end of the current mirror circuit, the second end of the reference current circuit is connected with the first end of the inverter circuit, the second end of the inverter circuit is connected with the second end of the current mirror circuit, the third end of the current mirror circuit is connected with the comparison current circuit, the fourth end of the current mirror circuit is connected with the first end of the clamp transistor, the second end of the clamp transistor is connected with the first end of the first enable tube, and the second end of the first enable tube is a bit line current input end;
the reference current circuit outputs reference current under the condition of receiving a first control signal sent by the reference current control circuit;
the comparison current circuit generates a comparison current under the condition of receiving a second control signal sent by the comparison current control circuit.
Optionally, the reference current circuit comprises at least one reference current branch.
Optionally, the reference current branch includes a reference current generating transistor and a reference current enabling tube, and the reference current enabling tube performs a switching operation according to the first control signal, so that a reference current is generated at the reference current generating transistor.
Optionally, the comparison current circuit includes at least one comparison current branch.
Optionally, the comparison current branch includes a comparison current generating transistor and a comparison current enabling tube, the comparison current enabling tube performs a switching operation according to the second control signal, so that a reference signal is generated at the comparison current generating transistor, and the comparison current circuit generates the comparison current according to the reference signal at the comparison current generating transistor in the at least one comparison current branch.
Optionally, the current mirror circuit is configured to copy the comparison current generated by the comparison current circuit and output the comparison current through a fourth terminal of the current mirror circuit.
Optionally, the current mirror circuit is a cascode current mirror circuit.
Optionally, a connection between the current mirror circuit and the inverter circuit is connected to a power supply voltage.
Optionally, the reference current circuit is grounded.
Optionally, a current value of the comparison current is equal to or less than the bit line current.
By the above technical solution, the present disclosure provides a sense amplifier, including: the circuit comprises a reference current circuit, a comparison current circuit, a current mirror circuit, an inverter circuit, a first enabling tube and a clamping transistor. The first end of the reference current circuit is connected with the first end of the current mirror circuit, the second end of the reference current circuit is connected with the first end of the inverter circuit, the second end of the inverter circuit is connected with the second end of the current mirror circuit, the third end of the current mirror circuit is connected with the comparison current circuit, the fourth end of the current mirror circuit is connected with the first end of the clamp transistor, the second end of the clamp transistor is connected with the first end of the first enable tube, and the second end of the first enable tube is a bit line current input end; the reference current circuit outputs reference current under the condition of receiving a first control signal sent by the reference current control circuit; the comparison current circuit generates a comparison current under the condition of receiving a second control signal sent by the comparison current control circuit. According to the control method and the control device, the reference current control circuit controls the reference current circuit to output the reference current, and the comparison current control circuit outputs the comparison current, so that the comparison between the comparison current and the reference current can be dynamically controlled. Due to the fact that the number of current mirror circuits of the sensitive amplifier and the number of required reference currents are reduced, under the same accuracy, the sensitive amplifier is simple in circuit structure and low in power consumption.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a circuit connection diagram showing a sense amplifier in the related art in a case where the highest precision output high order is 2 BITs (BIT);
FIG. 2 is a circuit diagram of a sense amplifier according to the present disclosure;
FIG. 3 is a schematic diagram of a circuit structure of a sense amplifier provided by the present disclosure in a case where the highest precision output is 3 BITs high (BIT);
FIG. 4 shows a dynamic comparison diagram of the reference current and the comparison current in the comparison process of the sense amplifier provided by the present disclosure with the output result of "011";
fig. 5 shows functional waveform diagrams of signals in comparison process of the sense amplifier provided by the present disclosure, wherein the output result is "011".
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Fig. 1 is a schematic diagram of a circuit structure of a sense amplifier in the related art under the condition that the highest precision output high order is 2 BITs (BIT), and the operating principle is as follows: after the enable signal SAEN is turned on, a negative feedback consisting of an operational amplifier Clamp _ mirror applies a Clamp voltage Vclp to the Clamp transistor 01, and since the bit line voltage is fixed by the Clamp transistor 01, a constant bit line current IBL is formed on the bit line, and the bit line current IBL is copied by the current mirror circuit 02 and compared with a reference current (the reference currents Iref0, Iref1, and Iref2 shown in fig. 1) generated by a reference signal, and when the bit line current IBL is greater than the reference current, a logic "0" is output from the output terminal DOUT of the sense amplifier in the related art, and otherwise, a logic "1" is output.
As can be seen in conjunction with fig. 1, since the sense amplifier in the related art needs to set a reference current for discrimination between reference currents for comparison with the bit line current two times in succession. For example: the reference current used by the higher-precision bit of the previous stage is 4 μ a, the reference current used by the lower-precision bit of the previous stage is the current-precision bit, and the reference current used by the current-precision bit is 3 μ a, so that the reference current needed to be set for distinguishing in the related art can be 3.5 μ a. Therefore, the number R of reference currents required for the sense amplifier in the related art is related to the highest-precision output high bit O by: r is 2 O 1, i.e. the number of required reference currents grows exponentially with the higher the highest precision output.
When the required highest-precision output high bit is larger, the number of required reference currents in the circuit of the sense amplifier in the related art is exponentially increased, and the number of current mirror circuits is exponentially increased, so that the circuit structure of the sense amplifier is more complex as the highest-precision output high bit is larger. The more current mirror circuits cause the more bit line currents to be duplicated, which results in large power consumption of the sense amplifier in the related art.
As shown in fig. 2, a schematic circuit structure of a sense amplifier provided in an embodiment of the present disclosure includes: the circuit comprises a reference current circuit 100, a comparison current circuit 200, a current mirror circuit 300, an inverter circuit 400, a first enabling tube 500 and a clamping transistor 600.
The first terminal of the reference current circuit 100 is connected to the first terminal of the current mirror circuit 300, the second terminal of the reference current circuit 100 is connected to the first terminal of the inverter circuit 400, the second terminal of the inverter circuit 400 is connected to the second terminal of the current mirror circuit 300, the third terminal of the current mirror circuit 300 is connected to the comparison current circuit 200, the fourth terminal of the current mirror circuit 300 is connected to the first terminal of the clamp transistor 600, the second terminal of the clamp transistor 600 is connected to the first terminal of the first enable transistor 500, and the second terminal of the first enable transistor 500 is a bit line current input terminal.
Optionally, the first enable transistor 500 is a sense amplifier enable transistor, and mainly generates a sense amplifier enable signal.
The reference current circuit 100 outputs a reference current in case of receiving a first control signal transmitted by a reference current control circuit.
It will be appreciated that the reference current circuit 100 is electrically connected to a reference current control circuit.
Optionally, the reference current circuit 100 includes at least one reference current branch.
Optionally, the reference current branch includes a reference current generating transistor and a reference current enabling tube, and the reference current enabling tube performs a switching operation according to the first control signal, so that the reference current generating transistor generates the reference current. It is understood that the magnitude of the reference current at the reference current generating transistor may be controlled by the first control signal.
It should be noted that, in the reference current circuit 100 of the sense amplifier provided in the embodiment of the present disclosure, the magnitude of the reference current generated by each reference current branch is controlled by the control signal sent by the reference current control circuit, and the magnitude of the reference current used by the current high-precision bit is limited by the comparison result between the previous-stage comparison current used by the previous-stage high-precision bit of the current high-precision bit and the previous-stage reference current, so that there is no need to set a reference current for distinguishing. For example: the current reference current used by the current high-precision position is 4 muA, and the reference current control circuit sends out a control signal to control the current reference current to be 4 muA. Therefore, in the sense amplifier provided by the embodiment of the present disclosure, the number of the reference current branches in the reference current circuit 100 is equal to the maximum precision high-order number of the sense amplifier. The number of reference current branches is equal to the number of reference currents. Namely, the relationship between the number R of reference currents required by the sense amplifier provided by the present disclosure and the highest-precision output high bit O is: r is O.
As can be seen from this, compared with the sense amplifier in the related art, the sense amplifier provided by the embodiment of the present disclosure requires a smaller number of reference currents when the value of the highest-precision output high bit is larger. For example: when the highest-precision output high order is 2 bits, the number of reference currents of the sense amplifier provided by the embodiment of the present disclosure is 2, and the number of reference currents required by the sense amplifier in the related art is 3. When the highest-precision output high order is 4 bits, the number of reference currents of the sense amplifier provided by the embodiment of the present disclosure is 4, and the number of reference currents of the sense amplifier in the related art is 15. When the highest-precision output high order is 6 bits, the number of reference currents of the sense amplifier provided by the embodiment of the present disclosure is 6, and the number of reference currents of the sense amplifier in the related art is 63. In summary, the sense amplifier provided by the embodiment of the present disclosure reduces a circuit area compared to a sense amplifier in the related art, so that the sense amplifier provided by the embodiment of the present disclosure has a simpler circuit structure, and reduces the number of reference currents, thereby reducing power consumption.
Optionally, the reference current circuit 100 is grounded.
The comparison current circuit 200 generates a comparison current upon receiving a second control signal sent by the comparison current control circuit.
Optionally, the comparison current circuit 200 includes at least one comparison current branch.
Optionally, the comparison current branch includes a comparison current generating transistor and a comparison current enabling transistor, the comparison current enabling transistor performs a switching operation according to the second control signal, so that a reference signal is generated at the comparison current generating transistor, and the comparison current circuit 200 generates the comparison current according to the reference signal at the comparison current generating transistor in the at least one comparison current branch.
It should be noted that, since the comparison current circuit 200 in the sense amplifier provided by the embodiment of the present disclosure does not need to generate the lowest-level precision high-order current in the reference current circuit 100, the number of comparison current branches in the sense amplifier provided by the embodiment of the present disclosure is equal to the number of reference current branches minus 1.
Since the sense amplifier provided by the embodiment of the present disclosure can control the magnitude of the comparison current output by the comparison current circuit 200 by the comparison current control circuit, the comparison current can be dynamically controlled to be compared with the reference current.
It is understood that a person skilled in the art may design specific structural connections of the reference current control circuit and the comparison current control circuit, and the disclosure does not limit the circuit structures of the reference current control circuit and the comparison current control circuit.
Optionally, the current mirror circuit 300 is configured to copy the comparison current generated by the comparison current circuit 200 and output the comparison current through a fourth terminal of the current mirror circuit 300.
Optionally, the current mirror circuit 300 is a cascode current mirror circuit.
Optionally, a connection between the current mirror circuit 300 and the inverter circuit 400 is connected to a power supply voltage.
Optionally, a current value of the comparison current is equal to or smaller than the bit line current.
In an alternative implementation, the sense amplifier provided by the embodiment of the present disclosure uses one current mirror circuit 300 for comparing the comparison current with the reference current for a plurality of times, and therefore the number of the current mirror circuits 300 of the sense amplifier provided by the embodiment of the present disclosure does not increase with the increase of the value of the highest-precision output high bit. The sense amplifier provided by the embodiment of the present disclosure can use the current mirror circuits 300 with the number of 1 to meet the requirement of comparing current replica outputs under the condition of high-order output with the highest precision.
In the case where the comparative current is larger than the reference current, the inverter circuit 400 outputs a logical value "0". In the case where the comparison current is smaller than the reference current, the inverter circuit 400 outputs a logical value "1". The embodiment of the present disclosure compares the comparison current with the reference current by time-sharing, so that the inverter circuit 400 may output a logic value corresponding to the comparison result according to time-sharing. For example: when the sense amplifier provided by the present disclosure outputs a high BIT (BIT) of 4 at the highest precision, the inverter circuit 400 needs to output a logic value 4 times.
To facilitate an intuitive understanding of the sense amplifier provided by the present disclosure, the following description is made in conjunction with fig. 3: fig. 3 is a schematic circuit diagram of a sense amplifier provided by the present disclosure in a case where the highest precision output high BIT is 3 BITs (BIT).
The reference current circuit 100 of the sense amplifier provided by the present disclosure includes 3 reference current branches, namely a first reference current branch, a second reference current branch and a third reference current branch, under the condition that the highest precision output high order is 3 BITs (BIT). The first reference current branch comprises a first reference current generation transistor and a first reference current enable tube. The second reference current branch comprises a second reference current generation transistor and a second reference current enable tube. The third reference current branch comprises a third reference current generation transistor and a third reference current enable tube.
The first reference current enabling tube controls the on/off of the self enabling tube according to a control signal DSEN [0] output by the received reference current control circuit, so that the reference current generated by the first reference current generating transistor is Iref 0. The second reference current enable tube controls the on/off of the self enable tube according to a control signal DSEN [1] output by the received reference current control circuit, so that the reference current generated by the second reference current generation transistor is Iref 1. The third reference current enabling tube controls the on/off of the self enabling tube according to a control signal DSEN [2] output by the received reference current control circuit, so that the reference current generated by the third reference current generating transistor is Iref 2. It is understood that the reference current control circuit may output control signals DSEN [0], DSEN [1] and DSEN [2] as first control signals to the reference current circuit 100 to cause each of the reference current branches in the reference current circuit 100 to generate a reference current. The magnitude of the reference current in each reference current branch is determined by a control signal sent to the reference current enable tube in each reference current branch by the reference current control circuit.
The comparison current circuit 200 of the sense amplifier provided by the present disclosure under the condition that the highest precision output high BIT is 3 BITs (BIT) includes 2 comparison current branches, which are a first comparison current branch and a second comparison current branch, respectively. The first comparison current branch comprises a first comparison current generation transistor and a first comparison current enable tube. The second comparison current branch comprises a second comparison current generation transistor and a second comparison current enable tube.
The first comparison current enable tube controls the on/off of the self enable tube according to a control signal DSW [1] output by the received comparison current control circuit, so that the first comparison current generation transistor generates a reference signal ref 0. The second comparison current enable tube controls the on/off of the self enable tube according to the control signal DSW [2] output by the receiving comparison current control circuit, so that the second comparison current generation transistor generates the reference signal ref 1. The comparison current circuit 200 generates a comparison current Idata according to a reference signal ref0 and a reference signal ref 1. It is understood that the comparison current control circuit can output the control signals DSW [1] and DSW [2] to the comparison current circuit 200 as the second control signal, so that the comparison current generation transistors in the respective comparison current branches of the comparison current circuit 200 generate the corresponding reference signals to output the comparison currents.
It will be appreciated that the reference signal ref in each of the comparison current branches of the comparison circuit is related to the reference current used, and that the control signal DSW determines the comparison current Idata that is ultimately output. The reference signal ref is used to determine the magnitude of the current generated by the comparison current branch. The control signal DSW is used to control the opening and closing of the corresponding comparison current branch, thereby affecting the magnitude of the finally output comparison current Idata.
As shown in fig. 3, IBL is the bit line current, RD _ ENDD is the sense amplifier enable signal,
vclp is a clamp voltage applied to the clamp transistor 600 for the sense amplifier enable signal after 180 degrees phase inversion. The current mirror circuit 300 copies the comparison current Idata generated by the comparison current circuit 200 and outputs the comparison current Idata, and the output direction is shown by an arrow. VDD is the supply voltage and DOUT is the output of inverter circuit 400.
It can be understood that, when the sense amplifier provided by the present disclosure outputs a high-order BIT of 4 BITs (BIT) with the highest precision, on the basis of the circuit structure of the sense amplifier shown in fig. 3, it is sufficient to add one comparison current branch to the comparison current circuit 200 and one reference current branch to the reference current circuit 100. The circuit structure of the sense amplifier can be obtained under the condition that the BIT (BIT) with other values is output with the highest precision.
In the working process of the sense amplifier provided by the embodiment of the disclosure, when the logic value of the highest-precision high bit is determined, the magnitude of the comparison current used for comparing with the reference current is equal to the magnitude of the bit line current.
In the working process of the sense amplifier provided by the embodiment of the disclosure, when a logic value of a current high-precision bit except for a highest-precision high bit is determined, it is assumed that a previous-stage comparison current used by a previous-stage high-precision bit is compared with a previous-stage reference current, and if a comparison result shows that the previous-stage comparison current is smaller than the previous-stage reference current, the current comparison current used for comparing the current high-precision bit with the current reference current is equal to the previous-stage comparison current in magnitude. If the comparison result is that the upper-stage comparison current is larger than the upper-stage reference current, the current comparison current used for comparing with the current reference current under the current high precision is equal to the value obtained by subtracting the upper-stage reference current from the upper-stage comparison current. For example: and under the condition that the comparison result is that the upper-stage comparison current is greater than the upper-stage reference current, the control signal DSW is used for controlling the disconnection of the comparison current enabling tube of the comparison current branch with high current precision, so that the current comparison current under the high current precision is the value obtained by subtracting the upper-stage reference current from the upper-stage comparison current.
When the sense amplifier provided by the present disclosure operates, since the reference current is not all directly compared with the bit line current copied by the current mirror circuit 300, the sense amplifier provided by the present disclosure supports the comparison between the reference current and the comparative current, which is smaller than the bit line current, and thus the power consumption of the sense amplifier provided by the present disclosure is lower than that of the sense amplifier in the related art.
It should be noted that the comparison current may be equal to the reference current in a theoretical environment, but since in a practical application scenario, there may be a small disturbance in the circuit, the disturbance may cause the comparison result of the comparison current and the reference current to be unequal.
In order to facilitate understanding of the working flow of the sense amplifier provided by the embodiment of the present disclosure, based on the circuit structure of the sense amplifier shown in fig. 3 in the case that the highest precision output high order BIT is 3 BITs (BIT), the working flow of the sense amplifier provided by the embodiment of the present disclosure is described by the following examples:
at workAt first, the first comparison current Idata 1 Equal to the bit line current IBL, the first comparison current Idata 1 When Idata is compared with the first reference current Iref0 1 When the current is smaller than Iref0, the logic value of the highest precision high bit output by the inverter circuit 400 is "0" and the second comparison current Idata 2 Is equal to Idata 1 . Comparing the second comparison current Idata 2 When comparing with the second reference current Iref1, Idata 2 When the output voltage is larger than Iref1, the logic value of the second highest bit of the inverter circuit 400 is "1" and the third comparison current Idata 3 Is equal to Idata 2 Iref1 is subtracted. Comparing the third comparison current with a third reference current Iref2 when Idata 3 If the value is greater than Iref2, the logic value of the lowest precision high bit output by inverter circuit 400 is "1", and the final output result of the sense amplifier is "011". Based on the sense amplifier shown in fig. 3, fig. 4 is a schematic diagram illustrating a dynamic comparison of a reference current and a comparison current in a comparison process of the sense amplifier provided by the present disclosure with an output result of "011". S8 to S1 indicate that the bit line current IBL increases in sequence, the dotted lines at both ends are the reference current, the solid arrows are the bit line current, and the dashed arrows are the comparative current. Fig. 5 is a functional waveform diagram of signals in a comparison process of the sense amplifier provided by the present disclosure, wherein the output result is "011".
At the start of operation, the first comparative current Idata 1 Equal to the bit line current IBL, the first comparison current Idata 1 When comparing with the first reference current Iref0, Idata 1 When the output voltage is larger than Iref0, the logic value of the highest-precision high-bit output by the inverter circuit 400 is obtained as "1" and the second comparison current Idata 2 Is equal to Idata 1 Iref0 is subtracted. Comparing the second comparison current Idata 2 When Idata is compared with the second reference current Iref1 2 When the output voltage is smaller than Iref1, the logic value of the second highest bit of the inverter circuit 400 is "0" and the third comparison current Idata 3 Equal to Idata 2 . Comparing the third comparison current with a third reference current Iref2 when Idata 3 When the output voltage is larger than Iref2, logic with the lowest precision and high bit output by the inverter circuit 400 is obtainedAnd the edit value is 1, the final output result of the sensitive amplifier is 101.
At the start of operation, the first comparative current Idata 1 Equal to the bit line current IBL, a first comparison current Idata 1 When comparing with the first reference current Iref0, Idata 1 When the output voltage is larger than Iref0, the logic value of the highest-precision high-bit output by the inverter circuit 400 is obtained as "1" and the second comparison current Idata 2 Is equal to Idata 1 Iref0 is subtracted. Comparing the second comparison current Idata 2 When comparing with the second reference current Iref1, Idata 2 When the output voltage is larger than Iref1, the logic value of the second highest bit of the inverter circuit 400 is "1" and the third comparison current Idata 3 Is equal to Idata 2 Iref1 is subtracted. Comparing the third comparison current with a third reference current Iref2 when Idata 3 When the output voltage is smaller than Iref2, the logic value of the lowest precision high bit output by the inverter circuit 400 is "0", and the final output result of the sense amplifier is "110".
The present disclosure provides a sense amplifier, comprising: the current-sharing circuit comprises a reference current circuit 100, a comparison current circuit 200, a current mirror circuit 300, an inverter circuit 400, a first enable transistor 500 and a clamp transistor 600. A first terminal of the reference current circuit 100 is connected to a first terminal of the current mirror circuit 300, a second terminal of the reference current circuit 100 is connected to a first terminal of the inverter circuit 400, a second terminal of the inverter circuit 400 is connected to a second terminal of the current mirror circuit 300, a third terminal of the current mirror circuit 300 is connected to the comparison current circuit 200, a fourth terminal of the current mirror circuit 300 is connected to a first terminal of the clamp transistor 600, a second terminal of the clamp transistor 600 is connected to a first terminal of the first enable transistor 500, and a second terminal of the first enable transistor 500 is a bit line current input terminal; the reference current circuit 100 outputs a reference current under the condition of receiving a first control signal sent by a reference current control circuit; the comparison current circuit 200 generates a comparison current upon receiving a second control signal sent by the comparison current control circuit. According to the present disclosure, the reference current control circuit 100 is controlled to output the reference current, and the comparison current control circuit outputs the comparison current, so that the comparison between the comparison current and the reference current can be dynamically controlled. Since the number of current mirror circuits 300 of the sense amplifier and the number of required reference currents are reduced, the circuit structure of the sense amplifier provided by the present disclosure is simple and the power consumption is lower with the same precision.
It is to be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
The above are merely examples of the present disclosure, and are not intended to limit the present disclosure. Various modifications and variations of this disclosure will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement or the like made within the spirit and principle of the present disclosure should be included in the scope of the claims of the present disclosure.
Claims (10)
1. A sense amplifier, comprising: the circuit comprises a reference current circuit, a comparison current circuit, a current mirror circuit, an inverter circuit, a first enabling tube and a clamping transistor;
the first end of the reference current circuit is connected with the first end of the current mirror circuit, the second end of the reference current circuit is connected with the first end of the inverter circuit, the second end of the inverter circuit is connected with the second end of the current mirror circuit, the third end of the current mirror circuit is connected with the comparison current circuit, the fourth end of the current mirror circuit is connected with the first end of the clamp transistor, the second end of the clamp transistor is connected with the first end of the first enable tube, and the second end of the first enable tube is a bit line current input end;
the reference current circuit outputs reference current under the condition of receiving a first control signal sent by the reference current control circuit;
the comparison current circuit generates a comparison current under the condition of receiving a second control signal sent by the comparison current control circuit.
2. The sense amplifier of claim 1 wherein the reference current circuit comprises at least one reference current branch.
3. The sense amplifier of claim 2, wherein the reference current branch comprises a reference current generating transistor and a reference current enable transistor, and the reference current enable transistor is turned on and off according to the first control signal, so that a reference current is generated at the reference current generating transistor.
4. The sense amplifier of claim 1 wherein the comparison current circuit comprises at least one comparison current branch.
5. The sense amplifier of claim 4, wherein the comparison current branch comprises a comparison current generation transistor and a comparison current enable transistor, the comparison current enable transistor is turned on and off according to the second control signal, so that a reference signal is generated at the comparison current generation transistor, and the comparison current circuit generates the comparison current according to the reference signal at the comparison current generation transistor in the at least one comparison current branch.
6. The sense amplifier of claim 5, wherein the current mirror circuit is configured to copy the comparison current generated by the comparison current circuit and output the comparison current through a fourth terminal of the current mirror circuit.
7. The sense amplifier of claim 1, wherein the current mirror circuit is a cascode current mirror circuit.
8. The sense amplifier of claim 1, wherein a junction of the current mirror circuit and the inverter circuit is connected to a supply voltage.
9. The sense amplifier of claim 1 wherein the reference current circuit is grounded.
10. The sense amplifier of claim 1, wherein the comparison current has a current value equal to or less than the bit line current.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820056A (en) * | 2011-06-07 | 2012-12-12 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit for phase change memorizer |
| CN102890955A (en) * | 2011-07-21 | 2013-01-23 | 中国科学院微电子研究所 | Sensitive amplifier used for large-scale flash memory |
| CN103325414A (en) * | 2013-05-21 | 2013-09-25 | 清华大学 | RRAM memory read circuit |
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| ITVA20040021A1 (en) * | 2004-05-04 | 2004-08-04 | St Microelectronics Srl | SENSING AMPLIFIER FOR READING A NON VOLATILE MEMORY CELL |
| US7535783B2 (en) * | 2007-10-01 | 2009-05-19 | International Business Machines Corporation | Apparatus and method for implementing precise sensing of PCRAM devices |
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| CN102820056A (en) * | 2011-06-07 | 2012-12-12 | 中国科学院上海微系统与信息技术研究所 | Data readout circuit for phase change memorizer |
| CN102890955A (en) * | 2011-07-21 | 2013-01-23 | 中国科学院微电子研究所 | Sensitive amplifier used for large-scale flash memory |
| CN103325414A (en) * | 2013-05-21 | 2013-09-25 | 清华大学 | RRAM memory read circuit |
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| A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning;Yuxin Zhang 等;《2021 IEEE International Symposium on Circuits and Systems (ISCAS)》;20210427;全文 * |
| Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory;Linfang Wang 等;《2021 IEEE International Symposium on Circuits and Systems (ISCAS)》;20210427;全文 * |
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| CN113192543A (en) | 2021-07-30 |
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