CN113191113A - Power consumption optimization method and system based on register transmission level and related components - Google Patents
Power consumption optimization method and system based on register transmission level and related components Download PDFInfo
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Abstract
The application discloses a power consumption optimization method, a system and related components based on register transmission level, wherein the power consumption optimization method comprises the following steps: acquiring a to-be-optimized architecture of a register transmission level; performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result; analyzing a simulation result in a preset scene mode by using preset analysis software to obtain a redundancy inversion report and a clock gating efficiency report; and determining the position where the logic and the clock gating of the redundant upset do not conform to expectation by using the redundant upset report and the clock gating efficiency report, and optimizing the architecture to be optimized. According to the method and the device, pre-simulation is carried out on the framework to be optimized, the positions where the logic of redundancy overturning and the clock gating do not accord with expectation are directly analyzed and optimized by using a simulation report, and the redundancy power consumption point is accurately found, so that rapid optimization can be carried out, and the time consumption for power consumption optimization is obviously shortened.
Description
Technical Field
The invention relates to the field of chip system architecture design, in particular to a power consumption optimization method and system based on register transmission level and related components.
Background
With the progress of the process, the design of the system architecture becomes more complex, the problem of power consumption is more and more obvious, and how to reduce the power consumption becomes the central importance of the chip development at the present stage. In large-scale ASIC (Application Specific Integrated Circuit) design, an RTL (Register Transfer Level) Level design process determines power consumption of at least 80% of the entire system, and this power consumption cannot be reduced by means of a synthesis tool or a back-end process.
At present, the main means for solving the problem of RTL level power consumption comprises modifying an RTL architecture or modifying a code style, mainly finding a module with overhigh power consumption or a code writing method for preventing tool optimization according to a comprehensive result to modify, and then integrating to check whether the power consumption is optimized. The whole modification period is long in time consumption and not friendly to project planning, and the power consumption after modification cannot be guaranteed to achieve the expected optimization effect after each modification, and the modification may need to be repeated for many times.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a method, a system and related components for power consumption optimization based on register transmission level. The specific scheme is as follows:
a power consumption optimization method based on register transmission level comprises the following steps:
acquiring a to-be-optimized architecture of a register transmission level;
performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result;
analyzing the simulation result in the preset scene mode by using preset analysis software to obtain a redundancy reversal report and a clock gating efficiency report;
and determining the position where the logic and the clock gating of the redundant overturning do not conform to the expectation by utilizing the redundant overturning report and the clock gating efficiency report, and optimizing the architecture to be optimized.
Preferably, the preset scene mode includes a functional scene mode and a built-in self-test scene mode.
Preferably, the process of performing pre-simulation on the architecture to be optimized in the preset scene mode to obtain a simulation result includes:
and under a preset scene mode, performing pre-simulation on the architecture to be optimized, recording a waveform file, and taking the waveform file as a simulation result.
Preferably, the process of analyzing the simulation result in the preset scene mode by using preset analysis software to obtain a redundancy inversion report and a clock gating efficiency report includes:
and configuring the preset scene mode in preset analysis software, and loading the simulation result into the preset analysis software so that the preset analysis software performs pseudo-comprehensive processing on the architecture to be optimized to obtain a redundancy inversion report and a clock gating efficiency report.
Preferably, the pseudo-synthesis processing is specifically conversion of a register transmission level to a netlist.
Preferably, the power consumption optimization method further includes:
analyzing the simulation result in the preset scene mode by using the preset analysis software to obtain a signal turnover rate distribution report;
determining report data in the signal slew rate distribution report; the report data is as follows: the report data with the duration being preset duration and the highest inversion frequency in the signal turnover rate distribution report;
and carrying out power consumption analysis on the architecture to be optimized by utilizing the report data.
Preferably, the process of analyzing the power consumption of the architecture to be optimized by using the report data includes:
calculating average power consumption according to the report data, and taking the average power consumption as the maximum power consumption of the architecture to be optimized in the preset scene mode;
and analyzing the voltage drop condition of the framework to be optimized by utilizing the maximum power consumption.
Correspondingly, the application also discloses a power consumption optimization system based on register transmission level, which comprises:
the architecture obtaining module is used for obtaining the architecture to be optimized of the transmission level of the register;
the simulation module is used for performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result;
the analysis module is used for analyzing the simulation result in the preset scene mode by utilizing preset analysis software to obtain a redundancy inversion report and a clock gating efficiency report;
and the action module is used for determining the position where the logic of the redundancy overturning and the clock gating do not accord with the expectation by utilizing the redundancy overturning report and the clock gating efficiency report, and optimizing the architecture to be optimized.
Correspondingly, this application still discloses a power consumption optimization device based on register transmission level, includes:
a memory for storing a computer program;
a processor for implementing the steps of the register transfer level based power consumption optimization method according to any one of the above when executing the computer program.
Accordingly, the present application also discloses a readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the register transfer level based power consumption optimization method according to any of the above.
The application discloses a power consumption optimization method based on register transmission level, which comprises the following steps: acquiring a to-be-optimized architecture of a register transmission level; performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result; analyzing the simulation result in the preset scene mode by using preset analysis software to obtain a redundancy reversal report and a clock gating efficiency report; and determining the position where the logic and the clock gating of the redundant overturning do not conform to the expectation by utilizing the redundant overturning report and the clock gating efficiency report, and optimizing the architecture to be optimized. According to the method and the device, pre-simulation is carried out on the framework to be optimized, the positions where the logic of redundancy overturning and the clock gating do not accord with expectation are directly analyzed and optimized by using a simulation report, and the redundancy power consumption point is accurately found, so that rapid optimization can be carried out, and the time consumption for power consumption optimization is obviously shortened.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flowchart illustrating steps of a power consumption optimization method based on register transmission levels according to an embodiment of the present invention;
FIG. 2a is a block diagram illustrating a structure of a specific architecture to be optimized according to an embodiment of the present invention;
FIG. 2b is a diagram illustrating an optimized structure distribution of a specific architecture to be optimized according to an embodiment of the present invention;
fig. 3 is a structural distribution diagram of a power consumption optimization system based on register transmission level in an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, the main means for solving the problem of RTL level power consumption comprises modifying an RTL architecture or modifying a code style, mainly finding a module with overhigh power consumption or a code writing method for preventing tool optimization according to a comprehensive result to modify, and then integrating to check whether the power consumption is optimized. The whole modification period is long in time consumption and not friendly to project planning, and the power consumption after modification cannot be guaranteed to achieve the expected optimization effect after each modification, and the modification may need to be repeated for many times.
According to the method and the device, pre-simulation is carried out on the framework to be optimized, the positions where the logic of redundancy overturning and the clock gating do not accord with expectation are directly analyzed and optimized by using a simulation report, and the redundancy power consumption point is accurately found, so that rapid optimization can be carried out, and the time consumption for power consumption optimization is obviously shortened.
The embodiment of the invention discloses a power consumption optimization method based on register transmission level, which is shown in figure 1 and comprises the following steps:
s1: acquiring a to-be-optimized architecture of a register transmission level;
s2: performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result;
the preset scene modes include, but are not limited to, a functional scene mode and a built-In Self-Test (built-In Self-Test) scene mode, and In addition to the two scene modes, other typical scene modes commonly used by the architecture to be optimized can be selected.
Specifically, the implementation of the step includes: and under a preset scene mode, performing pre-simulation on the architecture to be optimized, recording a waveform file, and taking the waveform file as a simulation result.
S3: analyzing a simulation result in a preset scene mode by using preset analysis software to obtain a redundancy inversion report and a clock gating efficiency report;
specifically, the implementation of the step includes: and configuring a preset scene mode in preset analysis software, and loading a simulation result into the preset analysis software so that the preset analysis software performs pseudo-comprehensive processing on the architecture to be optimized to obtain a redundancy inversion report and a clock gating efficiency report.
It can be understood that, in this embodiment, the preset analysis software may generally select powerPro software, the configured preset scene mode is the configured powerPro environment in the preset analysis software, and the simulation result corresponding to the preset scene mode is loaded into the preset analysis software, which performs pseudo-synthesis processing on the architecture to be optimized, where the pseudo-synthesis is specifically conversion from a register transmission level to a netlist.
S4: and determining the position where the logic and the clock gating of the redundant upset do not conform to expectation by using the redundant upset report and the clock gating efficiency report, and optimizing the architecture to be optimized.
Specifically, the logic of redundancy inversion in the architecture to be optimized can be determined through the redundancy inversion report, and the logic of redundancy inversion specifically refers to the logic which should not be inverted but is always inverted in the original design so as to generate redundancy power consumption; the undesirable locations of clock gating in the architecture to be optimized can be determined by clock gating efficiency (CLK gating efficiency) reporting, where undesirable primarily includes missed clock gating or clock gating gains that are undesirable.
Specifically, taking 32-bit data as an example, only the low 16-bit data in the 32-bit data after mux selection is adopted by other signals, and the remaining high 16-bit data is not used, and if the architecture to be optimized is designed to transmit all the 32-bit data signals to the mux, redundancy of the high 16-bit data and redundant power consumption along with the generated redundancy are inevitably generated, and at this time, the flip logic is also the logic for flipping the redundancy determined in the embodiment.
In addition to the above exceptions, the working states of the same architecture to be optimized in different preset scene modes may also be affected, for example, it is usually designed that all the works of the built-in self-test scene mode are in an idle state when the architecture to be optimized is expected to work in the functional scene mode, so that it can be ensured that the built-in self-test scene mode does not affect the power consumption statistics in the functional scene mode, but the actual architecture to be optimized is difficult to clearly distinguish the two modes, taking fig. 2a as an example, the same clock CLK is simultaneously provided to the built-in self-test scene mode working module BIST unit and the functional scene mode working module function unit, and when the clock CLK works in the functional scene mode, the built-in self-test scene mode working module BIST unit may generate redundancy inversion to the clock CLK. Similar redundancy inversion causes large power consumption, which cannot be optimized in the signoff (timing analysis is performed on the whole chip to ensure that the expected frequency is reached) stage of the architecture to be optimized, so that the actual power consumption measurement of the whole chip is large and exceeds the expected power consumption. By using the optimization method in this embodiment, the logic of redundancy inversion in fig. 2a, that is, the starting branch point of the built-in self-test scene mode and the functional scene mode, may be determined, and then optimization is performed, as shown in fig. 2b, a clock inversion mechanism mux1 and mux2 are added to the starting branch point, when the BIST mode signal is 0, that is, the architecture to be optimized is configured as the functional scene mode, the corresponding working module function unit operates, and the clock CLK only provides a clock for the working module function unit of the functional scene mode, thereby solving the problem that the clock of the BIST unit is still inverted in the functional scene mode.
The application discloses a power consumption optimization method based on register transmission level, which comprises the following steps: acquiring a to-be-optimized architecture of a register transmission level; performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result; analyzing the simulation result in the preset scene mode by using preset analysis software to obtain a redundancy reversal report and a clock gating efficiency report; and determining the position where the logic and the clock gating of the redundant overturning do not conform to the expectation by utilizing the redundant overturning report and the clock gating efficiency report, and optimizing the architecture to be optimized. According to the method and the device, pre-simulation is carried out on the framework to be optimized, the positions where the logic of redundancy overturning and the clock gating do not accord with expectation are directly analyzed and optimized by using a simulation report, and the redundancy power consumption point is accurately found, so that rapid optimization can be carried out, and the time consumption for power consumption optimization is obviously shortened.
The embodiment of the invention discloses a specific power consumption optimization method based on register transmission level, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme. Specifically, the power consumption optimization method further includes:
analyzing a simulation result in a preset scene mode by using preset analysis software to obtain a signal turnover rate distribution report;
determining report data in a signal turnover rate distribution report; the reported data are: the report data with the duration being preset duration and the highest inversion frequency in the signal turnover rate distribution report;
and carrying out power consumption analysis on the architecture to be optimized by utilizing the report data.
Further, the process of analyzing the power consumption of the architecture to be optimized by using the report data includes:
calculating average power consumption according to the report data, and taking the average power consumption as the maximum power consumption of the architecture to be optimized in a preset scene mode;
and analyzing the voltage drop condition of the architecture to be optimized by utilizing the maximum power consumption.
It can be understood that in the voltage drop IR drop analysis, scene and timing selection of analysis data are very important, and if the analysis data is incomplete or does not correspond to the maximum power consumption, the analysis result is too optimistic and cannot reflect the actual voltage drop condition, and the frequency of the chip after the chip back test is not expected and the chip cannot work normally. Therefore, in the embodiment, a time period with violent inversion is found as report data of power consumption analysis by using a signal inversion rate distribution report obtained by preset analysis software, and the corresponding power consumption is the maximum power consumption required in voltage drop analysis. The preset time of the report data of the section is used for calculating the average power consumption of the report data, if the preset time is too long, the power consumption is too small, and if the preset time is too short, the power consumption is too large, so that 100 periods can be selected as the preset time based on the rule of stable operation of a conventional chip.
And on the basis of the preset duration, selecting a part with the highest signal turnover frequency in the whole signal turnover rate distribution report as report data by taking the signal turnover frequency proportion as a selection basis.
Correspondingly, the present application also discloses a power consumption optimization system based on register transmission level, as shown in fig. 3, including:
the architecture obtaining module 1 is used for obtaining a to-be-optimized architecture of a register transmission level;
the simulation module 2 is used for performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result;
the analysis module 3 is used for analyzing a simulation result in a preset scene mode by using preset analysis software to obtain a redundancy inversion report and a clock gating efficiency report;
and the action module 4 is used for determining the position where the logic and the clock gating of the redundant upset do not accord with the expectation by utilizing the redundant upset report and the clock gating efficiency report, and optimizing the architecture to be optimized.
According to the embodiment of the application, pre-simulation is carried out on the framework to be optimized, the positions where the logic of redundancy overturning and the clock gating do not accord with expectation are directly analyzed and optimized by using the simulation report, and the redundant power consumption point is accurately found, so that rapid optimization can be carried out, and the time consumption for power consumption optimization is obviously shortened.
In some specific embodiments, the preset scene mode includes a functional scene mode and a built-in self-test scene mode.
In some specific embodiments, the simulation module 2 is specifically configured to:
and under a preset scene mode, performing pre-simulation on the architecture to be optimized, recording a waveform file, and taking the waveform file as a simulation result.
In some specific embodiments, the analysis module 3 is specifically configured to:
and configuring the preset scene mode in preset analysis software, and loading the simulation result into the preset analysis software so that the preset analysis software performs pseudo-comprehensive processing on the architecture to be optimized to obtain a redundancy inversion report and a clock gating efficiency report.
In some specific embodiments, the pseudo-synthesis process is specifically a register transfer level to netlist conversion.
In some specific embodiments, the analysis module 3 is further configured to analyze the simulation result in the preset scene mode by using the preset analysis software to obtain a signal turnover rate distribution report; the action module 4 is further configured to determine report data in the signal turnover rate distribution report; the report data is as follows: the report data with the duration being preset duration and the highest inversion frequency in the signal turnover rate distribution report; the action module 4 is further configured to perform power consumption analysis on the architecture to be optimized by using the report data.
In some specific embodiments, the action module 4 is specifically configured to calculate an average power consumption according to the report data, and use the average power consumption as a maximum power consumption of the architecture to be optimized in the preset scene mode; and analyzing the voltage drop condition of the framework to be optimized by utilizing the maximum power consumption.
Correspondingly, the application also discloses a power consumption optimization device based on the register transmission level, which comprises a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the steps of:
acquiring a to-be-optimized architecture of a register transmission level;
performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result;
analyzing the simulation result in the preset scene mode by using preset analysis software to obtain a redundancy reversal report and a clock gating efficiency report;
and determining the position where the logic and the clock gating of the redundant overturning do not conform to the expectation by utilizing the redundant overturning report and the clock gating efficiency report, and optimizing the architecture to be optimized.
According to the embodiment of the application, pre-simulation is carried out on the framework to be optimized, the positions where the logic of redundancy overturning and the clock gating do not accord with expectation are directly analyzed and optimized by using the simulation report, and the redundant power consumption point is accurately found, so that rapid optimization can be carried out, and the time consumption for power consumption optimization is obviously shortened.
In some specific embodiments, the preset scene mode includes a functional scene mode and a built-in self-test scene mode.
In some specific embodiments, when the processor executes the computer subprogram stored in the memory, the following steps may be specifically implemented:
and under a preset scene mode, performing pre-simulation on the architecture to be optimized, recording a waveform file, and taking the waveform file as a simulation result.
In some specific embodiments, when the processor executes the computer subprogram stored in the memory, the following steps may be specifically implemented:
and configuring the preset scene mode in preset analysis software, and loading the simulation result into the preset analysis software so that the preset analysis software performs pseudo-comprehensive processing on the architecture to be optimized to obtain a redundancy inversion report and a clock gating efficiency report.
In some specific embodiments, the pseudo-synthesis process is specifically a register transfer level to netlist conversion.
In some specific embodiments, when the processor executes the computer subprogram stored in the memory, the following steps may be specifically implemented:
analyzing the simulation result in the preset scene mode by using the preset analysis software to obtain a signal turnover rate distribution report;
determining report data in the signal slew rate distribution report; the report data is as follows: the report data with the duration being preset duration and the highest inversion frequency in the signal turnover rate distribution report;
and carrying out power consumption analysis on the architecture to be optimized by utilizing the report data.
In some specific embodiments, when the processor executes the computer subprogram stored in the memory, the following steps may be specifically implemented:
calculating average power consumption according to the report data, and taking the average power consumption as the maximum power consumption of the architecture to be optimized in the preset scene mode;
and analyzing the voltage drop condition of the framework to be optimized by utilizing the maximum power consumption.
Further, embodiments of the present application also disclose a readable storage medium, where the readable storage medium includes Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art. The readable storage medium has stored therein a computer program which, when executed by a processor, performs the steps of:
a power consumption optimization method based on register transmission level comprises the following steps:
acquiring a to-be-optimized architecture of a register transmission level;
performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result;
analyzing the simulation result in the preset scene mode by using preset analysis software to obtain a redundancy reversal report and a clock gating efficiency report;
and determining the position where the logic and the clock gating of the redundant overturning do not conform to the expectation by utilizing the redundant overturning report and the clock gating efficiency report, and optimizing the architecture to be optimized.
According to the embodiment of the application, pre-simulation is carried out on the framework to be optimized, the positions where the logic of redundancy overturning and the clock gating do not accord with expectation are directly analyzed and optimized by using the simulation report, and the redundant power consumption point is accurately found, so that rapid optimization can be carried out, and the time consumption for power consumption optimization is obviously shortened.
In some specific embodiments, the preset scene mode includes a functional scene mode and a built-in self-test scene mode.
In some specific embodiments, when executed by a processor, the computer sub-program stored in the readable storage medium may specifically implement the following steps:
and under a preset scene mode, performing pre-simulation on the architecture to be optimized, recording a waveform file, and taking the waveform file as a simulation result.
In some specific embodiments, when executed by a processor, the computer sub-program stored in the readable storage medium may specifically implement the following steps:
and configuring the preset scene mode in preset analysis software, and loading the simulation result into the preset analysis software so that the preset analysis software performs pseudo-comprehensive processing on the architecture to be optimized to obtain a redundancy inversion report and a clock gating efficiency report.
In some specific embodiments, the pseudo-synthesis process is specifically a register transfer level to netlist conversion.
In some specific embodiments, when executed by a processor, the computer sub-program stored in the readable storage medium may further specifically implement the following steps:
analyzing the simulation result in the preset scene mode by using the preset analysis software to obtain a signal turnover rate distribution report;
determining report data in the signal slew rate distribution report; the report data is as follows: the report data with the duration being preset duration and the highest inversion frequency in the signal turnover rate distribution report;
and carrying out power consumption analysis on the architecture to be optimized by utilizing the report data.
In some specific embodiments, when executed by a processor, the computer sub-program stored in the readable storage medium may specifically implement the following steps:
calculating average power consumption according to the report data, and taking the average power consumption as the maximum power consumption of the architecture to be optimized in the preset scene mode;
and analyzing the voltage drop condition of the framework to be optimized by utilizing the maximum power consumption.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The method, the system and the related components for power consumption optimization based on register transmission level provided by the invention are introduced in detail, a specific example is applied in the text to explain the principle and the implementation mode of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A power consumption optimization method based on register transmission level is characterized by comprising the following steps:
acquiring a to-be-optimized architecture of a register transmission level;
performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result;
analyzing the simulation result in the preset scene mode by using preset analysis software to obtain a redundancy reversal report and a clock gating efficiency report;
and determining the position where the logic and the clock gating of the redundant overturning do not conform to the expectation by utilizing the redundant overturning report and the clock gating efficiency report, and optimizing the architecture to be optimized.
2. The power consumption optimization method of claim 1, wherein the preset scenario modes comprise a functional scenario mode and a built-in self test scenario mode.
3. The power consumption optimization method according to claim 1, wherein the process of performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result comprises:
and under a preset scene mode, performing pre-simulation on the architecture to be optimized, recording a waveform file, and taking the waveform file as a simulation result.
4. The power consumption optimization method according to claim 3, wherein the process of analyzing the simulation result in the preset scene mode by using preset analysis software to obtain a redundancy inversion report and a clock gating efficiency report includes:
and configuring the preset scene mode in preset analysis software, and loading the simulation result into the preset analysis software so that the preset analysis software performs pseudo-comprehensive processing on the architecture to be optimized to obtain a redundancy inversion report and a clock gating efficiency report.
5. The power consumption optimization method of claim 4, wherein the pseudo-synthesis process is specifically a register transfer level to netlist conversion.
6. The power consumption optimization method according to any one of claims 1 to 5, further comprising:
analyzing the simulation result in the preset scene mode by using the preset analysis software to obtain a signal turnover rate distribution report;
determining report data in the signal slew rate distribution report; the report data is as follows: a section of report data with the duration being preset duration and the turnover frequency being the highest in the signal turnover rate distribution report;
and carrying out power consumption analysis on the architecture to be optimized by utilizing the report data.
7. The power consumption optimization method according to claim 6, wherein the process of analyzing the power consumption of the architecture to be optimized by using the report data comprises:
calculating average power consumption according to the report data, and taking the average power consumption as the maximum power consumption of the architecture to be optimized in the preset scene mode;
and analyzing the voltage drop condition of the framework to be optimized by utilizing the maximum power consumption.
8. A power consumption optimization system based on register transfer levels, comprising:
the architecture obtaining module is used for obtaining the architecture to be optimized of the transmission level of the register;
the simulation module is used for performing pre-simulation on the architecture to be optimized in a preset scene mode to obtain a simulation result;
the analysis module is used for analyzing the simulation result in the preset scene mode by utilizing preset analysis software to obtain a redundancy inversion report and a clock gating efficiency report;
and the action module is used for determining the position where the logic of the redundancy overturning and the clock gating do not accord with the expectation by utilizing the redundancy overturning report and the clock gating efficiency report, and optimizing the architecture to be optimized.
9. A power consumption optimization device based on register transfer levels, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the register transfer level based power consumption optimization method according to any one of claims 1 to 7 when executing the computer program.
10. A readable storage medium, having stored thereon a computer program which, when executed by a processor, carries out the steps of the register transfer level based power consumption optimization method according to any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080127001A1 (en) * | 2006-11-28 | 2008-05-29 | Fujitsu Limited | Power consumption analyzing method and computer- readable storage medium |
| US20120274354A1 (en) * | 2011-04-26 | 2012-11-01 | Renesas Electronics Corporation | Logic circuit design method, logic design program, and semiconductor integrated circuit |
| CN105095607A (en) * | 2015-09-15 | 2015-11-25 | 浪潮(北京)电子信息产业有限公司 | Optimization method for netlist logic redundancies in ASIC design and optimization system for netlist logic redundancy in ASIC design |
| CN106527575A (en) * | 2016-10-21 | 2017-03-22 | 东南大学—无锡集成电路技术研究所 | Activity similarity based trigger grouping clock gating method |
| CN108880562A (en) * | 2017-05-11 | 2018-11-23 | 珠海格力电器股份有限公司 | Cyclic redundancy check circuit and its method, apparatus and chip, electronic equipment |
| CN108897652A (en) * | 2018-07-03 | 2018-11-27 | 中国人民解放军国防科技大学 | Error positioning method and system based on RT L level power consumption analysis |
-
2021
- 2021-06-03 CN CN202110620291.4A patent/CN113191113B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080127001A1 (en) * | 2006-11-28 | 2008-05-29 | Fujitsu Limited | Power consumption analyzing method and computer- readable storage medium |
| US20120274354A1 (en) * | 2011-04-26 | 2012-11-01 | Renesas Electronics Corporation | Logic circuit design method, logic design program, and semiconductor integrated circuit |
| CN105095607A (en) * | 2015-09-15 | 2015-11-25 | 浪潮(北京)电子信息产业有限公司 | Optimization method for netlist logic redundancies in ASIC design and optimization system for netlist logic redundancy in ASIC design |
| CN106527575A (en) * | 2016-10-21 | 2017-03-22 | 东南大学—无锡集成电路技术研究所 | Activity similarity based trigger grouping clock gating method |
| CN108880562A (en) * | 2017-05-11 | 2018-11-23 | 珠海格力电器股份有限公司 | Cyclic redundancy check circuit and its method, apparatus and chip, electronic equipment |
| CN108897652A (en) * | 2018-07-03 | 2018-11-27 | 中国人民解放军国防科技大学 | Error positioning method and system based on RT L level power consumption analysis |
Non-Patent Citations (2)
| Title |
|---|
| 李杰等: "基于功能仿真的RTL级低功耗优化", 《现代电子技术》 * |
| 郑国鹏等: "基于门控时钟的寄存器传输级功耗优化", 《电子技术》 * |
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