CN113190480A - Data transmission method and device, electronic equipment and computer readable storage medium - Google Patents
Data transmission method and device, electronic equipment and computer readable storage medium Download PDFInfo
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- CN113190480A CN113190480A CN202110745795.9A CN202110745795A CN113190480A CN 113190480 A CN113190480 A CN 113190480A CN 202110745795 A CN202110745795 A CN 202110745795A CN 113190480 A CN113190480 A CN 113190480A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
Abstract
The embodiment of the invention relates to a data transmission method, a data transmission device, electronic equipment and a computer readable storage medium, wherein the method comprises the following steps: partitioning a preset memory area to obtain a plurality of memory partitions; when peripheral data transmitted by peripheral equipment are received, the peripheral data are stored in one memory block; polling a plurality of memory blocks, and acquiring the peripheral data stored in the memory blocks which are currently inquired in the polling process. Therefore, the data transmission efficiency between the CPU and the peripheral equipment can be improved, and the time delay can be reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of data processing, in particular to a data transmission method and device, electronic equipment and a computer readable storage medium.
Background
The Programmable logic device is a hardware carrier for specifically realizing the established functions and technical indexes of an electronic application system through an Electronic Design Automation (EDA) technology, and an Field Programmable Gate Array (FPGA) is one of main devices for realizing the method, and has the characteristics of direct user facing, great flexibility and universality, convenience in use, rapid hardware testing and realization and the like. Based on this, FPGAs are widely used in a variety of data processing scenarios.
For example, with the development of modern financial technology, the delay requirement on market and transaction systems is higher and higher, and the use of the FPGA for processing market and transaction data becomes a mainstream trend. Furthermore, the FPGA, as a peripheral device of the computer, needs to perform data exchange and synchronization operations with a Central Processing Unit (CPU), and the real-time performance of data exchange and synchronization between them is one of the key factors of market and transaction system delay.
Therefore, how to improve the efficiency of data exchange and synchronization between the peripheral device and the computer CPU becomes a technical problem to be solved urgently.
Disclosure of Invention
In view of this, in order to solve the technical problem of how to improve the efficiency of data exchange and synchronization between the peripheral device and the CPU of the computer, embodiments of the present invention provide a data transmission method, an apparatus, an electronic device, and a computer-readable storage medium.
In a first aspect, an embodiment of the present invention provides a data transmission method, where the method includes:
partitioning a preset memory area to obtain a plurality of memory partitions;
when peripheral data transmitted to a target end by peripheral equipment is received, storing the peripheral data in one memory block;
and controlling the target terminal to poll a plurality of memory blocks, and acquiring the peripheral data stored in the memory blocks which are currently polled in the polling process.
In one possible embodiment, the method further comprises:
and applying a large page mechanism for a large page of the memory with a set size from the physical memory to serve as the preset memory area.
In a possible embodiment, the partitioning the preset memory area to obtain a plurality of memory partitions includes:
and partitioning the preset memory area according to the specified block size to obtain a plurality of memory partitions.
In one possible embodiment, the method further comprises:
and sending the physical address of the memory area to the peripheral equipment so that the peripheral equipment sends the peripheral data to the memory area according to the physical address.
In a possible embodiment, the storing peripheral data in one of the memory partitions when peripheral data transmitted by a peripheral device is received includes:
and when receiving peripheral data transmitted to the memory area by the peripheral equipment in a DMA transmission mode, storing the peripheral data in one memory block.
In a possible embodiment, the storing peripheral data in one of the memory partitions when peripheral data transmitted by a peripheral device is received includes:
and circularly storing the received peripheral data transmitted by the peripheral equipment in one memory block according to the arrangement sequence of the memory blocks in the memory area.
In one possible embodiment, the method further comprises:
setting each memory block to comprise a block head and a block body, wherein the block head is used for storing the initial address and the offset of the block body, and the block body is used for storing the peripheral data;
after said storing said peripheral data in one of said memory partitions, said method further comprises:
writing the data length of the peripheral data as the offset into the block head of the memory block;
the acquiring the peripheral data stored in the currently queried memory partition includes:
acquiring a starting address and an offset stored in a block head of the memory block which is inquired currently;
and acquiring the peripheral data from the corresponding block according to the acquired starting address and the acquired offset.
In one possible embodiment, the block header is further configured to store a data transmission flag, where the data transmission flag indicates whether peripheral data in a corresponding block has been transmitted;
the acquiring the peripheral data stored in the currently queried memory partition includes:
acquiring a data transmission mark stored in a block head of the memory block which is inquired currently;
and if the acquired data transmission mark represents that the peripheral equipment data in the corresponding block is not transmitted, acquiring the peripheral equipment data stored in the memory block inquired currently.
In one possible embodiment, after the obtaining the peripheral data stored in the currently queried memory partition, the method further includes:
and updating the data transmission marks stored in the block heads of the memory blocks which are inquired currently, wherein the updated data transmission marks represent that the peripheral data in the corresponding blocks are transmitted.
In one possible embodiment, after the storing the peripheral data in one of the memory blocks, the method further includes:
and updating the data transmission marks stored in the block heads of the memory blocks which are inquired currently, wherein the updated data transmission marks represent that peripheral data in the corresponding blocks are not transmitted.
In one possible embodiment, the peripheral device is a field programmable gate array chip FPGA; the target end is a CPU.
In a second aspect, an embodiment of the present invention provides a data transmission apparatus, where the apparatus includes:
the block dividing module is used for dividing a preset memory area into a plurality of memory blocks;
the storage module is used for storing the peripheral data in one memory block when receiving the peripheral data transmitted to a target end by peripheral equipment;
and the polling module is used for controlling the target terminal to poll a plurality of memory blocks and acquiring the peripheral data stored in the memory blocks which are currently inquired in the polling process.
In a third aspect, an embodiment of the present invention provides an electronic device, including:
a memory for storing a computer program;
a processor for executing the computer program stored in the memory, and when the computer program is executed, implementing the method of any of the first aspects above.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program implements the method according to any one of the first aspect.
According to the technical scheme provided by the embodiment of the invention, the preset memory area is partitioned to obtain the plurality of memory partitions, when the peripheral data transmitted by the peripheral equipment are received, the peripheral data are stored in one memory partition, the plurality of memory partitions are polled, and the peripheral data stored in the memory partition inquired currently are obtained in the polling process, so that the peripheral data transmitted by the peripheral equipment are obtained by the CPU, in addition, in the data transmission process, the CPU can directly obtain the peripheral data from the memory partitions in a polling mode, and the register of the peripheral equipment does not need to be read to obtain the storage address of the peripheral data in the memory area, therefore, compared with the prior art, the data transmission efficiency can be improved, and the time delay is reduced.
Drawings
Fig. 1 is a schematic view of an application scenario of a data transmission method according to an embodiment of the present invention;
fig. 2 is a flowchart of an embodiment of a data transmission method according to an embodiment of the present invention;
fig. 3 is a flowchart of another data transmission method according to an embodiment of the present invention;
fig. 4 is a flowchart of another data transmission method according to an embodiment of the present invention;
fig. 5 is a flowchart of another data transmission method according to an embodiment of the present invention;
fig. 6 is a block diagram of an embodiment of a data transmission apparatus according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a schematic view of an application scenario of a data transmission method according to an embodiment of the present invention is provided. The application scenario shown in fig. 1 includes a device 10, where the device 10 includes an FPGA 101, a CPU 102, and a memory area 103. It should be noted that the above-described components included in the apparatus 10 are only exemplary, and in practice, other components may be included in the apparatus 10.
The device 10 may be a terminal or a server, which is not specifically limited in this embodiment of the present invention. When the device 10 is a terminal, it may be a variety of electronic devices having a display screen and supporting data transfer, including but not limited to smart phones, tablets, laptop portable computers, desktop computers, and the like.
In an exemplary application scenario, the FPGA 101 serves as a core processing module for transaction quotation and transaction data, but as a peripheral device of the device 10, it needs to perform data exchange and synchronous operation with the CPU 102. In this application scenario, there are two ways in the prior art to transmit data of the FPGA 101 (hereinafter referred to as peripheral data) to the CPU 102:
in the first mode, after the FPGA 101 writes the peripheral data into the memory area 103, the storage address of the peripheral data in the memory area 103 is written into an FPGA register (not shown), and the CPU 102 is notified in an interrupt manner to read the peripheral data from the memory area 103. Since the CPU 102 does not know the storage address of the peripheral data in the memory area 103, the CPU 102 accesses the FPGA register to obtain the storage address of the peripheral data in the memory area 103, and then reads the peripheral data from the memory area 103 based on the obtained storage address.
In the second mode, after the FPGA 101 writes the peripheral data into the memory area 103, the storage address of the peripheral data in the memory area 103 is written into the FPGA register. The CPU 102 then periodically accesses the FPGA registers to determine if the peripheral data is readable. When acquiring the storage address from the FPGA register, the CPU 102 reads peripheral data from the memory area 103 based on the acquired storage address.
In the first mode, the FPGA 101 notifies the CPU 102 to read the peripheral data from the memory area 103 in an interrupt manner, so that the normal operation of the CPU 102 is affected; in the second mode, because the CPU 102 needs to periodically access the FPGA register, the CPU 102 needs to frequently switch from the user mode to the kernel mode, and meanwhile, because the FPGA register and the memory area 103 are located on different memory blocks, the CPU 102 can read the peripheral data only by accessing the FPGA register and the memory area 103 located on different memory blocks, which may generate a large time delay.
Based on this, the embodiment of the present invention provides a data transmission method, and by applying the data transmission method provided by the embodiment of the present invention in the application scenario, not only data (hereinafter referred to as peripheral data) of the FPGA 101 can be transmitted to the CPU 102, but also data transmission efficiency can be improved, and time delay can be reduced.
The data transmission method provided by the present invention will be explained in detail by the following specific embodiments, which are not intended to limit the embodiments of the present invention.
Referring to fig. 2, a flowchart of an embodiment of a data transmission method according to an embodiment of the present invention is provided. As an embodiment, the method may be applied to the application scenario shown in fig. 1, that is, the data transmission scenario between the peripheral device and the CPU. Here, the peripheral device is, for example, the FPGA 101 illustrated in fig. 1. As shown in fig. 2, the method may include the steps of:
The memory area is, for example, the memory area 103 illustrated in fig. 1.
In the embodiment of the invention, the preset memory area can be partitioned according to the specified block size to obtain a plurality of memory partitions. This means that the size of each memory block is the prescribed block size. It should be noted that, in practice, there may be a case where the last memory partition is smaller than the specified block size, and this is not strictly limited in the embodiment of the present invention.
Furthermore, as an embodiment, the entire memory region may be partitioned in the above manner. As another embodiment, a part of the area in the memory area may be determined as a reserved area, and only according to the above manner, the area in the memory area other than the reserved area is blocked, and the reserved area may be used for other purposes, or when the number of the memory blocks is insufficient, the reserved area is continuously blocked, which is not limited in this embodiment of the present invention.
The peripheral device is, for example, the FPGA 101 illustrated in fig. 1, and the target is, for example, the CPU 102 illustrated in fig. 1.
As an embodiment, the peripheral device may transmit peripheral data to the Memory area by a DMA (Direct Memory Access) transmission method. The DMA is an interface technology for directly exchanging data with the system memory without the CPU, and the CPU does not participate in the transfer operation at all, so that the operations of fetching instructions, fetching numbers, sending numbers, and the like of the CPU are omitted.
And when receiving peripheral data transmitted by the peripheral equipment, storing the peripheral data in one memory block obtained by the division. Specifically, in the embodiment of the present invention, the received peripheral data transmitted by the peripheral device may be cyclically stored in one memory partition according to the arrangement order of the plurality of memory partitions in the memory area.
For example, assume that 10 memory blocks are obtained in step 201, when peripheral data transmitted by a peripheral device is received for the first time, the peripheral data is stored in the first memory block, when peripheral data transmitted by the peripheral device is received for the second time, the peripheral data is stored in the second memory block, when peripheral data transmitted by the peripheral device is received for the third time, the peripheral data is stored in the third memory block, when peripheral data transmitted by the peripheral device is received for the tenth time, the peripheral data is stored in the tenth memory block, when peripheral data transmitted by the peripheral device is received for the eleventh time, the peripheral data is stored in the first memory block, when peripheral data transmitted by the peripheral device is received for the twelfth time, the peripheral data is stored in the second memory block, and so on.
In the embodiment of the invention, a CPU on the equipment can poll a plurality of memory blocks. As can be understood by those skilled in the art, polling refers to sequentially inquiring each memory block, and based on this, in the polling process, the CPU acquires the peripheral data stored in the currently inquired memory block every time the CPU inquires one memory block. Therefore, the CPU obtains the peripheral data transmitted to the CPU by the peripheral equipment.
According to the technical scheme provided by the embodiment of the invention, the preset memory area is partitioned to obtain the plurality of memory partitions, when the peripheral data transmitted by the peripheral equipment are received, the peripheral data are stored in one memory partition, the plurality of memory partitions are polled, and the peripheral data stored in the memory partition inquired currently are obtained in the polling process, so that the peripheral data transmitted by the peripheral equipment are obtained by the CPU, in addition, in the data transmission process, the CPU can directly obtain the peripheral data from the memory partitions in a polling mode, and the register of the peripheral equipment does not need to be read to obtain the storage address of the peripheral data in the memory area, therefore, compared with the prior art, the data transmission efficiency can be improved, and the time delay is reduced.
Referring to fig. 3, a flowchart of another data transmission method according to an embodiment of the present invention is provided. The process shown in fig. 3 may include the following steps based on the process shown in fig. 2:
The large page mechanism, as the name implies, may define a maximum page size of 1GB in addition to a standard 4KB size page, which can greatly reduce the number of mapping tables loaded by the kernel, so that by enabling the large page mechanism, the system only needs to process fewer page mapping tables, thereby reducing the overhead of accessing/maintaining them.
In practice, during system startup, a large page mechanism may be used to apply for a large page of a memory with a set size from a physical memory as a preset memory area, and the memory area applied in this way may also be referred to as a large page memory. Furthermore, the large-page memory is physically continuous, and has a certain acceleration effect on large-page memory access.
The set size is, for example, 8KB, 16KB, 24KB, 1GB, etc., which is not limited in the embodiments of the present invention.
In the embodiment of the invention, after the memory area is applied from the physical memory, the physical address of the applied memory area is sent to the peripheral equipment, so that the peripheral equipment can transmit peripheral data to the memory area according to the physical address.
Here, the physical address of the memory area may be, for example, a start address and an end address of the memory area, or a start address and an offset.
And step 303, partitioning the preset memory area to obtain a plurality of memory partitions.
For the detailed description of steps 303 to 305, reference may be made to the description of the embodiment shown in fig. 2, which is not repeated herein.
According to the technical scheme provided by the embodiment of the invention, the preset memory area is partitioned to obtain the plurality of memory partitions, when the peripheral data transmitted by the peripheral equipment are received, the peripheral data are stored in one memory partition, the plurality of memory partitions are polled, and the peripheral data stored in the memory partition inquired currently are obtained in the polling process, so that the peripheral data transmitted by the peripheral equipment are obtained by the CPU, in addition, in the data transmission process, the CPU can directly obtain the peripheral data from the memory partitions in a polling mode, and the register of the peripheral equipment does not need to be read to obtain the storage address of the peripheral data in the memory area, therefore, compared with the prior art, the data transmission efficiency can be improved, and the time delay is reduced. Furthermore, the memory area is obtained by applying from the physical memory through a large-page mechanism, so that the data transmission quantity can be increased, and the transmission efficiency of peripheral equipment for transmitting peripheral data to the memory area can be improved.
Referring to fig. 4, a flowchart of another data transmission method according to an embodiment of the present invention is provided. The process shown in fig. 4 may include the following steps based on the process shown in fig. 2 or fig. 3:
And 402, partitioning the preset memory area to obtain a plurality of memory partitions.
In step 403, each memory partition is set to include a block header and a block body.
In the embodiment of the invention, each memory block is set to comprise a block head and a block body, wherein the block head is used for storing the initial address and the offset of the block body, and the block body is used for storing peripheral data.
Generally, the size of the block head is smaller than the size of the block.
As described in step 403, in the embodiment of the present invention, after the peripheral data is stored in one memory block, the data length of the peripheral data is written in the block header of the memory block as an offset, and further, in the polling process, every time one memory block is polled, the start address and the offset stored in the block header of the memory block that is currently polled are obtained, and the peripheral data is obtained from the corresponding block according to the obtained start address and the obtained offset.
According to the technical scheme provided by the embodiment of the invention, a plurality of memory blocks are obtained by partitioning a preset memory area, when peripheral data transmitted by peripheral equipment are received, the peripheral data are stored in one memory block, a plurality of memory blocks are polled, and the peripheral data stored in the memory block inquired currently are obtained in the polling process, so that the peripheral data transmitted by the peripheral equipment are obtained by a CPU (central processing unit), and in the data transmission process, the CPU can directly obtain the storage address of the peripheral data from the memory blocks in a polling mode to further obtain the peripheral data, and the storage address of the peripheral data in the memory area is not required to be read by a register of the peripheral equipment, so that the data transmission efficiency can be improved and the time delay is reduced compared with the prior art.
Referring to fig. 5, a flowchart of another embodiment of a data transmission method according to an embodiment of the present invention is provided. The process shown in fig. 5 may include the following steps based on any one of the processes shown in fig. 2 to 4:
And 505, writing the data length of the peripheral data as an offset into a block header of the memory block.
For the detailed description of the steps 501 to 505, reference may be made to the related description in the flows shown in fig. 2 to 4, which is not described herein again.
In an embodiment of the present invention, the block header further stores a data transmission flag, where the data transmission flag is used to represent whether peripheral data in the corresponding block is transmitted. Here, the block head of the corresponding block index data transmission mark belongs to the block in the memory block; transferred refers to a block transfer from memory to the CPU.
Based on this, when receiving the peripheral data transmitted by the peripheral device, after storing the peripheral data in one memory block, the data transmission flag stored in the block header of the memory block queried currently is updated, and the updated data transmission flag represents that the peripheral data in the corresponding block is not transmitted.
And step 508, if the acquired data transmission flag indicates that the peripheral device data in the corresponding block is not transmitted, acquiring the peripheral device data stored in the currently inquired memory block.
In the embodiment of the invention, in the polling process, when inquiring about one memory block, the data transmission mark stored in the block head of the memory block inquired at present is firstly obtained, and when the obtained data transmission mark represents that the peripheral equipment data in the corresponding block is not transmitted, the peripheral equipment data stored in the memory block inquired at present is obtained. Through the processing, the CPU can be prevented from repeatedly acquiring the peripheral data stored in the same memory block.
For other detailed descriptions of steps 507-508, refer to the related descriptions in the flows shown in fig. 2-4, which are not repeated herein.
Similar to the theory described above, after acquiring the peripheral data stored in the currently queried memory block, the data transmission flag stored in the block header of the currently queried memory block is updated, and the updated data transmission flag represents that the peripheral data in the corresponding block has been transmitted.
According to the technical scheme provided by the embodiment of the invention, the preset memory area is partitioned to obtain the plurality of memory partitions, when the peripheral data transmitted by the peripheral equipment are received, the peripheral data are stored in one memory partition, the plurality of memory partitions are polled, and the peripheral data stored in the memory partition inquired currently are obtained in the polling process, so that the peripheral data transmitted by the peripheral equipment are obtained by the CPU, in addition, in the data transmission process, the CPU can directly obtain the peripheral data from the memory partitions in a polling mode, and the register of the peripheral equipment does not need to be read to obtain the storage address of the peripheral data in the memory area, therefore, compared with the prior art, the data transmission efficiency can be improved, and the time delay is reduced.
Corresponding to the embodiment of the data transmission method, the invention also provides an embodiment of a data transmission device.
Referring to fig. 6, a block diagram of an embodiment of a data transmission apparatus according to an embodiment of the present invention is provided. As shown in fig. 6, the apparatus includes: a block module 61, a storage module 62 and a polling module 63.
The block dividing module 61 is configured to divide a preset memory area into blocks to obtain a plurality of memory blocks;
the storage module 62 is configured to store peripheral data in one memory partition when the peripheral data transmitted to a target end by a peripheral device is received;
and the polling module 63 is configured to control the target terminal to poll a plurality of memory blocks, and in the polling process, obtain the peripheral data stored in the memory block that is currently queried.
In a possible embodiment, the device further comprises (not shown in the figures):
and the application module is used for applying a memory large page with a set size from a physical memory by adopting a large page mechanism as the preset memory area.
In a possible implementation, the blocking module 61 is specifically configured to:
and partitioning the preset memory area according to the specified block size to obtain a plurality of memory partitions.
In a possible embodiment, the device further comprises (not shown in the figures):
and the address sending module is used for sending the physical address of the memory area to the peripheral equipment so that the peripheral equipment sends the peripheral data to the memory area according to the physical address.
In a possible implementation, the storage module 62 is specifically configured to:
and when receiving peripheral data transmitted to the memory area by the peripheral equipment in a DMA transmission mode, storing the peripheral data in one memory block.
In a possible implementation, the storage module 62 is specifically configured to:
and circularly storing the received peripheral data transmitted by the peripheral equipment in one memory block according to the arrangement sequence of the memory blocks in the memory area.
In a possible embodiment, the device further comprises (not shown in the figures):
the setting module is used for setting each memory block to comprise a block head and a block body, wherein the block head is used for storing the initial address and the offset of the block body, and the block body is used for storing the peripheral data;
an offset write-in module, configured to write a data length of the peripheral data into a block header of one of the memory blocks as the offset after the peripheral data is stored in the memory block;
the polling module 63 is specifically configured to:
acquiring a starting address and an offset stored in a block head of the memory block which is inquired currently; and acquiring the peripheral data from the corresponding block according to the acquired starting address and the acquired offset.
In one possible embodiment, the block header is further configured to store a data transmission flag, where the data transmission flag indicates whether peripheral data in a corresponding block has been transmitted;
the polling module 63 is specifically configured to:
acquiring a data transmission mark stored in a block head of the memory block which is inquired currently; and if the acquired data transmission mark represents that the peripheral equipment data in the corresponding block is not transmitted, acquiring the peripheral equipment data stored in the memory block inquired currently.
In a possible embodiment, the device further comprises (not shown in the figures):
the first updating module is configured to update the data transmission flag stored in the block header of the currently queried memory block after the peripheral data stored in the currently queried memory block is obtained, where the updated data transmission flag represents that the peripheral data in the corresponding block has been transmitted.
In a possible embodiment, the device further comprises (not shown in the figures):
and after the peripheral data is stored in one of the memory blocks, updating the data transmission flag stored in the block header of the currently queried memory block, where the updated data transmission flag indicates that the peripheral data in the corresponding block is not transmitted.
In one possible embodiment, the peripheral device is a field programmable gate array FPGA chip, and the target terminal is a CPU.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, where the electronic device 700 shown in fig. 7 includes: at least one processor 701, memory 702, at least one network interface 704, and other user interfaces 703. The various components in the electronic device 700 are coupled together by a bus system 705. It is understood that the bus system 705 is used to enable communications among the components. The bus system 705 includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for clarity of illustration the various busses are labeled in figure 7 as the bus system 705.
The user interface 703 may include, among other things, a display, a keyboard, or a pointing device (e.g., a mouse, trackball, touch pad, or touch screen, among others.
It is to be understood that the memory 702 in embodiments of the present invention may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be a Read-only memory (ROM), a programmable Read-only memory (PROM), an erasable programmable Read-only memory (erasabprom, EPROM), an electrically erasable programmable Read-only memory (EEPROM), or a flash memory. The volatile memory may be a Random Access Memory (RAM) which functions as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (staticiram, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (syncronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM ), Enhanced Synchronous DRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and direct memory bus RAM (DRRAM). The memory 702 described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
In some embodiments, memory 702 stores the following elements, executable units or data structures, or a subset thereof, or an expanded set thereof: an operating system 7021 and application programs 7022.
The operating system 7021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The application 7022 includes various applications, such as a media player (MediaPlayer), a Browser (Browser), and the like, for implementing various application services. Programs that implement methods in accordance with embodiments of the present invention can be included within application program 7022.
In the embodiment of the present invention, the processor 701 is configured to execute the method steps provided by the method embodiments by calling a program or an instruction stored in the memory 702, specifically, a program or an instruction stored in the application 7022, for example, and includes:
partitioning a preset memory area to obtain a plurality of memory partitions;
when peripheral data transmitted to a target end by peripheral equipment is received, storing the peripheral data in one memory block;
and the control target terminal polls a plurality of the memory blocks and acquires the peripheral data stored in the memory blocks which are polled currently in the polling process.
In one possible embodiment, the method further comprises:
and applying a large page mechanism for a large page of the memory with a set size from the physical memory to serve as the preset memory area.
In a possible embodiment, the partitioning the preset memory area to obtain a plurality of memory partitions includes:
and partitioning the preset memory area according to the specified block size to obtain a plurality of memory partitions.
In one possible embodiment, the method further comprises:
and sending the physical address of the memory area to the peripheral equipment so that the peripheral equipment sends the peripheral data to the memory area according to the physical address.
In a possible embodiment, the storing peripheral data in one of the memory partitions when peripheral data transmitted by a peripheral device is received includes:
and when receiving peripheral data transmitted to the memory area by the peripheral equipment in a DMA transmission mode, storing the peripheral data in one memory block.
In a possible embodiment, the storing peripheral data in one of the memory partitions when peripheral data transmitted by a peripheral device is received includes:
and circularly storing the received peripheral data transmitted by the peripheral equipment in one memory block according to the arrangement sequence of the memory blocks in the memory area.
In one possible embodiment, the method further comprises:
setting each memory block to comprise a block head and a block body, wherein the block head is used for storing the initial address and the offset of the block body, and the block body is used for storing the peripheral data;
after said storing said peripheral data in one of said memory partitions, said method further comprises:
writing the data length of the peripheral data as the offset into the block head of the memory block;
the acquiring the peripheral data stored in the currently queried memory partition includes:
acquiring a starting address and an offset stored in a block head of the memory block which is inquired currently;
and acquiring the peripheral data from the corresponding block according to the acquired starting address and the acquired offset.
In one possible embodiment, the block header is further configured to store a data transmission flag, where the data transmission flag indicates whether peripheral data in a corresponding block has been transmitted;
the acquiring the peripheral data stored in the currently queried memory partition includes:
acquiring a data transmission mark stored in a block head of the memory block which is inquired currently;
and if the acquired data transmission mark represents that the peripheral equipment data in the corresponding block is not transmitted, acquiring the peripheral equipment data stored in the memory block inquired currently.
In one possible embodiment, after the obtaining the peripheral data stored in the currently queried memory partition, the method further includes:
and updating the data transmission marks stored in the block heads of the memory blocks which are inquired currently, wherein the updated data transmission marks represent that the peripheral data in the corresponding blocks are transmitted.
In one possible embodiment, after the storing the peripheral data in one of the memory blocks, the method further includes:
and updating the data transmission marks stored in the block heads of the memory blocks which are inquired currently, wherein the updated data transmission marks represent that peripheral data in the corresponding blocks are not transmitted.
In one possible embodiment, the peripheral device is a field programmable gate array chip FPGA; the target end is a CPU.
The method disclosed in the above embodiments of the present invention may be applied to the processor 701, or implemented by the processor 701. The processor 701 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be implemented by integrated logic circuits of hardware or instructions in the form of software in the processor 701. The processor 701 may be a general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software elements in the decoding processor. The software elements may be located in ram, flash, rom, prom, or eprom, registers, among other storage media that are well known in the art. The storage medium is located in the memory 702, and the processor 701 reads the information in the memory 702 and performs the steps of the above method in combination with the hardware thereof.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented by means of units performing the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
The electronic device provided in this embodiment may be the electronic device shown in fig. 7, and may perform all the steps of the data transmission method shown in fig. 2 to 5, so as to achieve the technical effect of the data transmission method shown in fig. 2 to 5, and for brevity, it is not described herein again.
The embodiment of the invention also provides a computer readable storage medium. The storage medium herein stores one or more programs. Among others, the storage medium may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, a hard disk, or a solid state disk; the memory may also comprise a combination of memories of the kind described above.
When one or more programs in the storage medium are executable by one or more processors, the data transmission method executed on the electronic device side is realized.
The processor is used for executing the data transmission program stored in the memory to realize the following steps of the data transmission method executed on the electronic equipment side:
partitioning a preset memory area to obtain a plurality of memory partitions;
when peripheral data transmitted to a target end by peripheral equipment is received, storing the peripheral data in one memory block;
and the control target terminal polls a plurality of the memory blocks and acquires the peripheral data stored in the memory blocks which are polled currently in the polling process.
In one possible embodiment, the method further comprises:
and applying a large page mechanism for a large page of the memory with a set size from the physical memory to serve as the preset memory area.
In a possible embodiment, the partitioning the preset memory area to obtain a plurality of memory partitions includes:
and partitioning the preset memory area according to the specified block size to obtain a plurality of memory partitions.
In one possible embodiment, the method further comprises:
and sending the physical address of the memory area to the peripheral equipment so that the peripheral equipment sends the peripheral data to the memory area according to the physical address.
In a possible embodiment, the storing peripheral data in one of the memory partitions when peripheral data transmitted by a peripheral device is received includes:
and when receiving peripheral data transmitted to the memory area by the peripheral equipment in a DMA transmission mode, storing the peripheral data in one memory block.
In a possible embodiment, the storing peripheral data in one of the memory partitions when peripheral data transmitted by a peripheral device is received includes:
and circularly storing the received peripheral data transmitted by the peripheral equipment in one memory block according to the arrangement sequence of the memory blocks in the memory area.
In one possible embodiment, the method further comprises:
setting each memory block to comprise a block head and a block body, wherein the block head is used for storing the initial address and the offset of the block body, and the block body is used for storing the peripheral data;
after said storing said peripheral data in one of said memory partitions, said method further comprises:
writing the data length of the peripheral data as the offset into the block head of the memory block;
the acquiring the peripheral data stored in the currently queried memory partition includes:
acquiring a starting address and an offset stored in a block head of the memory block which is inquired currently;
and acquiring the peripheral data from the corresponding block according to the acquired starting address and the acquired offset.
In one possible embodiment, the block header is further configured to store a data transmission flag, where the data transmission flag indicates whether peripheral data in a corresponding block has been transmitted;
the acquiring the peripheral data stored in the currently queried memory partition includes:
acquiring a data transmission mark stored in a block head of the memory block which is inquired currently;
and if the acquired data transmission mark represents that the peripheral equipment data in the corresponding block is not transmitted, acquiring the peripheral equipment data stored in the memory block inquired currently.
In one possible embodiment, after the obtaining the peripheral data stored in the currently queried memory partition, the method further includes:
and updating the data transmission marks stored in the block heads of the memory blocks which are inquired currently, wherein the updated data transmission marks represent that the peripheral data in the corresponding blocks are transmitted.
In one possible embodiment, after the storing the peripheral data in one of the memory blocks, the method further includes:
and updating the data transmission marks stored in the block heads of the memory blocks which are inquired currently, wherein the updated data transmission marks represent that peripheral data in the corresponding blocks are not transmitted.
In one possible embodiment, the peripheral device is a field programmable gate array chip FPGA; the target end is a CPU.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (14)
1. A method of data transmission, the method comprising:
partitioning a preset memory area to obtain a plurality of memory partitions;
when peripheral data transmitted to a target end by peripheral equipment is received, storing the peripheral data in one memory block;
and controlling the target terminal to poll a plurality of memory blocks, and acquiring the peripheral data stored in the memory blocks which are currently polled in the polling process.
2. The method of claim 1, further comprising:
and applying a large page mechanism for a large page of the memory with a set size from the physical memory to serve as the preset memory area.
3. The method of claim 1, wherein the partitioning the preset memory partition to obtain a plurality of memory partitions comprises:
and partitioning the preset memory area according to the specified block size to obtain a plurality of memory partitions.
4. The method of claim 2, further comprising:
and sending the physical address of the memory area to the peripheral equipment so that the peripheral equipment sends the peripheral data to the memory area according to the physical address.
5. The method of claim 1, wherein storing peripheral data in one of the memory partitions upon receiving the peripheral data transmitted by a peripheral device comprises:
and when receiving peripheral data transmitted to the memory area by the peripheral equipment in a DMA transmission mode, storing the peripheral data in one memory block.
6. The method of claim 1, wherein storing peripheral data in one of the memory partitions upon receiving the peripheral data transmitted by a peripheral device comprises:
and circularly storing the received peripheral data transmitted by the peripheral equipment in one memory block according to the arrangement sequence of the memory blocks in the memory area.
7. The method of claim 1, further comprising:
setting each memory block to comprise a block head and a block body, wherein the block head is used for storing the initial address and the offset of the block body, and the block body is used for storing the peripheral data;
after said storing said peripheral data in one of said memory partitions, said method further comprises:
writing the data length of the peripheral data as the offset into the block head of the memory block;
the acquiring the peripheral data stored in the currently queried memory partition includes:
acquiring a starting address and an offset stored in a block head of the memory block which is inquired currently;
and acquiring the peripheral data from the corresponding block according to the acquired starting address and the acquired offset.
8. The method of claim 7, wherein the chunk header is further configured to store a data transfer flag, the data transfer flag characterizing whether peripheral data in a corresponding chunk has been transferred;
the acquiring the peripheral data stored in the currently queried memory partition includes:
acquiring a data transmission mark stored in a block head of the memory block which is inquired currently;
and if the acquired data transmission mark represents that the peripheral equipment data in the corresponding block is not transmitted, acquiring the peripheral equipment data stored in the memory block inquired currently.
9. The method of claim 8, wherein after said obtaining said peripheral data stored in said currently queried memory partition, said method further comprises:
and updating the data transmission marks stored in the block heads of the memory blocks which are inquired currently, wherein the updated data transmission marks represent that the peripheral data in the corresponding blocks are transmitted.
10. The method of claim 8, wherein after said storing said peripheral data in one of said memory partitions, said method further comprises:
and updating the data transmission marks stored in the block heads of the memory blocks which are inquired currently, wherein the updated data transmission marks represent that peripheral data in the corresponding blocks are not transmitted.
11. The method of claim 1, wherein the peripheral device is a Field Programmable Gate Array (FPGA) chip; the target end is a Central Processing Unit (CPU).
12. A data transmission apparatus, characterized in that the apparatus comprises:
the block dividing module is used for dividing a preset memory area into a plurality of memory blocks;
the storage module is used for storing the peripheral data in one memory block when receiving the peripheral data transmitted to a target end by peripheral equipment;
and the polling module is used for controlling the target terminal to poll a plurality of memory blocks and acquiring the peripheral data stored in the memory blocks which are currently inquired in the polling process.
13. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing a computer program stored in the memory, and when executed, implementing the method of any of the preceding claims 1-11.
14. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method of any one of the preceding claims 1 to 11.
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| US7549038B1 (en) * | 2002-09-30 | 2009-06-16 | Palm, Inc. | Method and system for determining memory chunk location using chunk header information |
| CN107870879A (en) * | 2016-09-23 | 2018-04-03 | 中国移动通信有限公司研究院 | A kind of data-moving method, accelerator board, main frame and data-moving system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7549038B1 (en) * | 2002-09-30 | 2009-06-16 | Palm, Inc. | Method and system for determining memory chunk location using chunk header information |
| CN107870879A (en) * | 2016-09-23 | 2018-04-03 | 中国移动通信有限公司研究院 | A kind of data-moving method, accelerator board, main frame and data-moving system |
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