CN113190475B - Secondary cache controller structure - Google Patents
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- CN113190475B CN113190475B CN202110501000.XA CN202110501000A CN113190475B CN 113190475 B CN113190475 B CN 113190475B CN 202110501000 A CN202110501000 A CN 202110501000A CN 113190475 B CN113190475 B CN 113190475B
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
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Abstract
The invention discloses a two-level cache controller structure, and belongs to the field of storage. The write function of a mode configuration function register to a memory protection page attribute register is added in the structure of the secondary cache controller, when the storage space is configured as the cache, the corresponding page attribute register is automatically configured to close the write permission of the physical address of the cache, and the phenomenon that the wrong data is read when the cache data is hit due to the writing of the physical address is avoided. And the circuit resource is saved, the delay of the write operation of the CPU is reduced, the Debug is facilitated, and the reliability of the system is improved.
Description
Technical Field
The invention relates to the technical field of storage, in particular to a two-level cache controller structure.
Background
After the DSP architecture introduces VLIW (Very Long Instruction Word) and SIMD (Single Instruction Multiple Data) technologies, the performance is developed rapidly; the improvement of the memory access speed has gradually failed to meet the requirements of the CPU, and becomes a bottleneck restricting the performance improvement. The appearance of a high-speed small-capacity memory Cache between a main memory and a CPU solves the problem of speed mismatching of a DSP processor and an external memory. The upper layer software usually reuses data from the same or adjacent memory locations in a short time, and caching the data into the cache can improve the running speed.
To achieve maximum performance, most of the data in the cache is available for a short time and is later evicted due to new data being written. When frequently used data and functions are cached, cache jitter exists between the frequently used data and other cached data, under the condition, the data can be prepared in the SRAM at any time, and therefore the performance of the DSP can be greatly improved by using a mode of combining the cache and the SRAM.
Under different design requirements and application occasions, various design technologies of the cache have great influence on the hit rate and consistency of the cache, and how to design and realize a reasonable and efficient secondary cache controller is a subject worthy of research.
Disclosure of Invention
The invention aims to provide a two-level cache controller structure to solve the problems in the background art.
In order to solve the technical problem, the invention provides a two-level cache controller structure, which comprises eight functional modules:
the freezing function module is used for closing the read-write distribution function of the secondary cache controller;
the off-chip cache module closes off the off-chip data caching function and closes the read-write allocation function of the cache when the cache is not hit;
the bandwidth management module is used for realizing bus arbitration among the multiple host devices, when the multiple devices send requests simultaneously, the multiple devices are selected to execute according to a preset priority sequence, the host with the high priority preferentially accesses, and the device with the low priority works when the maximum waiting time is reached;
the consistency operation module comprises a block consistency operation circuit and a global consistency operation circuit; when an important event occurs, the global cache operates the synchronous cache and the system;
the mode configuration module changes the ratio of the cache and the SRAM by configuring a relevant register and influences the hit rate of the cache;
the L2 TAG SRAM circuit stores the label bit and the flag bit information of the secondary cache controller;
the L1D TAG SRAM replica circuit stores the TAG bit and flag bit information of L1D, and screens the interception of L1D when the DMA operates the secondary cache controller;
and the memory protection module improves the robustness of the system.
Optionally, the bandwidth management module includes:
the DSP arbitrates the control register, control the priority and maximum waiting time of CPU operation;
an IDMA arbitration control register for controlling the priority and the maximum waiting time of the IDMA operation;
an SDMA arbitration control register for controlling the priority and the maximum waiting time of the SDMA operation;
and the user consistency arbitration control register controls the priority and the maximum waiting time of the consistency operation.
Optionally, the global consistency operation circuit synchronizes the cache and the system; the block coherency operation circuit targets block data, which is defined by a base address and a word size in an associated memory mapped register.
Optionally, when the cache works and the register data of the mode configuration module is changed, the mode configuration module automatically writes back and invalidates the content in the cache to a low-level storage, so as to prevent data loss; meanwhile, a page attribute register corresponding to the physical address of the cache is configured, the write permission of the physical address of the cache is closed, and the phenomenon that wrong data is read when cache data is hit due to the writing of the physical address is avoided; meanwhile, the cache capacity is changed, and the hit rate of the cache is influenced.
Optionally, each page attribute register controls a storage space of the secondary cache controller, and the number of the page attribute registers is set to be appropriate according to the size of a storage body of the secondary cache controller.
Optionally, when the secondary cache controller performs dirty bit replacement operation, the dirty data is written into the victim buffer, then the newly allocated data is written, and subsequent write-back to the low-level memory is performed in the background, so that performance loss is reduced.
Optionally, the memory protection module includes a memory protection page attribute register, a memory protection fault register, and a memory protection lock register;
the memory protection fault register comprises a memory protection fault address register, a memory protection fault state register and a memory protection fault zero clearing register; the memory protection fault address register records fault address information, the memory protection fault state register records the ID and the operation content of the fault operation host, and the memory protection fault clear register clears the information of the memory protection fault address register and the memory protection fault state register;
the memory protection lock register comprises a memory lock enabling register, four memory protection key registers, a memory protection lock command register and a memory protection lock state register; the memory protection lock register selectively stores the key according to the requirement;
the attribute register of the memory protection page is used for controlling the access authority of an administrator mode and a user mode when the SRAM is operated.
Optionally, the secondary cache controller is connected to L1D through a snoop circuit, the victim buffer circuit stores victim data, and the write buffer circuit stores write information in the absence of write loss of L1D, so as to reduce delay of the DSP core.
In the structure of the secondary cache controller provided by the invention, the writing function of the mode configuration function register to the memory protection page attribute register is added, when the storage space is configured as the cache, the corresponding page attribute register is automatically configured to close the writing authority of the physical address of the cache, and the reading error data when the cache data is hit due to the writing of the physical address is avoided. And the circuit resource is saved, the delay of the write operation of the CPU is reduced, the Debug is facilitated, and the reliability of the system is improved.
Drawings
FIG. 1 is a schematic diagram of a two-level cache controller according to the present invention;
FIG. 2 is a schematic diagram of a locking process flow of the secondary cache controller;
FIG. 3 is a schematic diagram of an unlocking process flow of the secondary cache controller;
FIG. 4 is a schematic diagram of SRAM access in the secondary cache controller;
FIG. 5 is a flow chart of the secondary cache controller processing an L1D write miss operation;
FIG. 6 is a flow chart of the operation of the two-level cache controller processing a L1D read miss.
Detailed Description
The following describes a two-level cache controller structure according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a secondary cache controller structure, which is connected with L1D through a monitoring circuit, a victim buffer circuit stores sacrificial data, and a write buffer circuit stores write information under the condition of L1D write loss, so that the delay of a DSP core is reduced; the structure of the two-level cache controller (i.e., L2) is shown in FIG. 1, and comprises:
and the freezing function module closes the read-write distribution function of the secondary cache controller, but does not influence the read-write hit operation and consistency operation of the cache of the secondary cache controller, and does not influence the function of the SRAM of the secondary cache controller.
And the off-chip cache module closes the off-chip data caching function and closes the read-write allocation function of the cache when the cache is not hit.
The bandwidth management module comprises a DSP arbitration control register, an IDMA arbitration control register, an SDMA arbitration control register and a user consistency arbitration control register; the DSP arbitration control register controls the priority and the maximum waiting time of the CPU operation; the IDMA arbitration control register controls the priority and the maximum waiting time of the IDMA operation; the SDMA arbitration control register controls the priority and the maximum waiting time of the SDMA operation; the user consistency arbitration control register controls the priority and the maximum waiting time of consistency operation; the bus arbitration among the multiple host devices is realized, when the multiple devices send requests simultaneously, the multiple devices select execution according to a preset priority order, the host with high priority can access preferentially, and the device with low priority can work when the maximum waiting time is reached.
And the consistency operation module comprises a block consistency operation circuit and a global consistency operation circuit. When a significant event occurs, for example: task conversion, mode change, or storage protection mechanism change, etc., the global cache operation can synchronize the cache with the system. The block coherency operation circuit is similar to the global coherency operation circuit, but only for block data, the block is defined by a base address and a word size in an associated memory mapped register.
And the mode configuration module changes the ratio of the cache and the SRAM by configuring a relevant register and influences the hit rate of the cache. Under the condition that the cache works, when the data of the register in the mode configuration module is changed, the mode configuration module can automatically write the content in the cache back to the low-level storage and make the content invalid, so that the data loss is prevented. And meanwhile, a page attribute register corresponding to the physical address of the cache is configured, the write permission of the physical address of the cache is closed, and wrong data is prevented from being read when the cache hits. Each page attribute register controls the storage space of the secondary cache controller, and the number of the page attribute registers is set to be proper according to the size of a storage body of the secondary cache controller.
And the L2 TAG SRAM circuit stores the label bit and the flag bit information of the secondary cache controller.
L1D TAG SRAM replica circuit, the label bit and the flag bit information of storage L1D, when DMA is operated to second grade cache controller, the screening is to L1D's interception, blocks unnecessary interception, makes the interception operation who reaches L1D all effective, reduces excessive interception, improves work efficiency.
And the monitoring circuit is used for writing data written by the DMA into the secondary cache controller and also writing the data into the L1D if the DMA writes into the secondary cache controller and the L1D hits. If the DMA carries out read operation on the secondary cache controller, the L1D hits and is dirty, the data of the L1D is directly read to the DMA, otherwise, the data of the secondary cache controller is read to the DMA.
In the victimbuffer circuit, when the secondary cache controller performs dirty bit replacement operation, dirty data is written into the victimbuffer circuit, then newly allocated data is written, and subsequent write-back low-level memory operation is performed in the background, so that performance loss is reduced.
The memory protection module comprises a memory protection page attribute register and a memory protection fault register, and a memory protection lock register is added, so that the robustness of the system is further improved. The memory protection fault register comprises a memory protection fault address register, a memory protection fault state register and a memory protection fault zero clearing register; the memory protection fault address register records fault address information, the memory protection fault state register records ID and operation content of a fault operation host, and the memory protection fault clear register clears information of the memory protection fault address register and the memory protection fault state register. The memory protection lock register comprises a memory lock enabling register, four memory protection key registers, a memory protection lock command register and a memory protection lock state register; the memory protection lock register selectively stores the key according to the requirement; the attribute register of the memory protection page is used for controlling the access authority of an administrator mode and a user mode when the SRAM is operated.
The secondary cache controller uses a mode of combining cache and SRAM, and a memory protection module is added for improving the reliability of the system. When the DMA carries the secondary cache controller, in order to maintain the consistency of the system, a snoop circuit and an L1D TAG SRAM replica circuit need to be added between the secondary cache controller and L1D. Under the condition that a cache mode is opened, an L2 TAG SRAM circuit is needed to judge the hit state and the flag bit information of a secondary cache controller, if the SRAM of the secondary cache controller is not hit, if and only if the secondary cache controller is not in a freezing mode and the off-chip cache function is opened, the secondary cache controller can perform allocation work, if each path of cache of the secondary cache controller is used at the moment, one path of data which is most frequently used needs to be evicted, and when the data is dirty, the data can be written into a vim buffer circuit. When changing off-chip data, consistency operation is needed to keep consistency between the on-chip data and the off-chip data.
Preferably, the snooping circuit between the L1P and the secondary cache controller is deleted, the CPU can only load programs from the L1P, and cannot perform write operation, and the deletion of the snooping circuit saves resources.
Preferably, a write buffer circuit is added between the L1D and the secondary cache controller, and under the condition of write miss of the L1D, data is queued in a write buffer, and the buffer avoids idling of a CPU in the case of write miss, thereby improving the working efficiency.
Referring to FIG. 2, the attribute register of the memory protection page is locked. Firstly, the memory protection lock status register is in an unlocked state by default, the memory lock enabling register is opened, then the keys are sequentially input into the memory protection key register, the input data is used as an unlocking key, the input times are only one time, finally, the memory protection lock command register is used for configuring the lock into a locked state, and at the moment, the locking step is completed. When the locking operation is completed, the memory protection lock state register can be automatically changed into 1, which indicates that the memory protection lock state register is in a locking state at the moment and closes the write permission of the page attribute register of the secondary cache controller. If the above steps are not performed, the locking will fail.
Preferably, the memory protection lock key register can store the required key digits according to requirements, and redundant keys do not need to be stored, so that resources are saved.
And unlocking the attribute register of the memory protection page. Firstly, the memory protection lock state register is in a locking state, the memory protection lock enable register is opened, then the key is input into the memory protection key register 1, the input data is used for unlocking comparison, when the input data is the same as the input data of the memory protection key register 1 during locking, whether the input data of the memory protection key register 2 is the same as the input data of the memory protection key register 2 during locking is compared, when the input data is the same as the input data of the memory protection key register 1 during locking, the key is input into the memory protection key register 2 and the memory protection key register 3, finally, the memory protection lock command register is configured to be in an unlocking state, and at this time, the unlocking step is completed. When the unlocking operation is finished, the memory protection lock state register can be automatically changed into 0, which indicates that the memory protection lock state register is in an unlocked state at the moment, and the write permission of the page attribute register of the secondary cache controller is opened. When the unlocking procedure is different, the fault information is recorded in the memory protection fault-related register, please refer to fig. 3.
Referring to FIG. 4, the steps of SRAM operation in the secondary cache controller are understood. When a CPU or other host operates a secondary cache controller, it is necessary to first read the setting of the attribute register of the corresponding memory protection page, when the operation authority is open, an SRAM in the secondary cache controller can normally operate, and when the authority is closed, it is possible to record failure information in a register related to a memory protection failure.
Preferably, the address of the fault operation is written into a memory protection fault address register, the content of the fault operation and the ID of the fault operation host are written into a memory protection fault state register, the memory protection fault state register and the memory protection fault address register are used for assisting the Debug, and after the Debug function is completed, 1 is written into an internal protection fault zero clearing register to clear the memory protection fault information, so that the fault after recording is facilitated. Wherein 1 is the effective functional bit information of the memory protection fault clear register. When the last bit of the register is written in 1, the information of the fault address register and the fault state register can be cleared, and when 0 is written in, the fault zero clearing register does not work and cannot clear the fault information.
Preferably, each page attribute register controls a certain storage space of the secondary cache controller, and the number of the page attribute registers is set appropriately according to the size of a storage body of the secondary cache controller.
Referring to FIG. 5, in the case of an L1D write miss, the operation of the secondary cache controller is performed. The second-level cache controller needs to judge whether the second-level cache controller hits or not firstly, if the second-level cache controller hits, the second-level cache controller directly performs write operation, otherwise, whether the second-level cache controller is in a freezing mode or not needs to be checked, if the second-level cache controller is in the freezing mode, the write operation is directly performed on the low-level memory, otherwise, whether a cache function is opened in an off-chip storage register needs to be checked, when the cache controller is opened, data of the low-level memory can be written into the second-level cache controller firstly, then the data written in by the CPU is written into the second-level cache controller, the data read from the off-chip just before is covered, and if the cache controller is not opened, the data can be written into the off-chip directly.
Referring to FIG. 6, in the case of a read miss of L1D, the operation of the secondary cache controller is performed. The secondary cache controller needs to judge whether the secondary cache controller hits or not firstly, if so, the secondary cache controller directly performs reading operation, otherwise, whether the secondary cache controller is in a freezing mode or not needs to be checked firstly, if so, the secondary cache controller directly performs reading operation on the low-level memory, and does not perform operation on the secondary cache controller. Otherwise, whether the off-chip storage register opens the cache function needs to be checked, when the off-chip storage register opens the cache function, the data of the low-level memory can be written into the second-level cache controller and transmitted to the upper-level cache, if the off-chip storage register does not open the cache function, the data of the low-level memory is directly read, and the second-level cache controller does not operate.
In summary, the present invention provides an efficient control method for a secondary cache controller, in which a write function of a mode configuration function register to a memory protection page attribute register is added, when a storage space is configured as a cache, a page attribute register corresponding to a physical address of the cache is automatically rewritten, and a write permission of the physical address of the cache is closed. And the wrong data read when cache data hit caused by the writing of the physical address is avoided. The memory protection module is used for protecting the memory of the secondary cache controller, so that the influence of code behavior on a data structure is reduced, and illegal access information is provided to help Debug.
The freeze mode allows real-time applications on various portions of code (e.g., interrupt handlers) to limit the amount of data evicted from the secondary cache controller, thereby increasing the hit rate of the secondary cache controller. Keeping the L1D TAG copy allows screening of DMA operations, preventing excessive snooping of L1D. The mode of the secondary cache controller can be changed during working, the hit rate is improved under different application conditions, and before the change, the data in the cache is written back and invalidated to the low-level memory, so that the data loss is prevented.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (6)
1. A two-level cache controller structure is characterized by comprising eight functional modules:
the freezing function module is used for closing the read-write distribution function of the secondary cache controller;
the off-chip cache module closes off the off-chip data caching function and closes the read-write allocation function of the cache when the cache is not hit;
the bandwidth management module is used for realizing bus arbitration among the multiple host devices, when the multiple devices send requests simultaneously, the multiple devices are selected to execute according to a preset priority sequence, the host with the high priority preferentially accesses, and the device with the low priority works when the maximum waiting time is reached;
the consistency operation module comprises a block consistency operation circuit and a global consistency operation circuit; when an important event occurs, the global cache operates the synchronous cache and the system;
the mode configuration module changes the ratio of the cache and the SRAM by configuring a relevant register and influences the hit rate of the cache;
the L2 TAG SRAM circuit stores the label bit and the flag bit information of the secondary cache controller;
the L1D TAG SRAM replica circuit stores the TAG bit and flag bit information of L1D, and screens the interception of L1D when the DMA operates the secondary cache controller;
the memory protection module is used for improving the robustness of the system;
under the condition that the cache works, when the register data of the mode configuration module is changed, the mode configuration module can automatically write back and invalidate the contents in the cache to a low-level storage, so that the data loss is prevented; meanwhile, a page attribute register corresponding to the physical address of the cache is configured, the write permission of the physical address of the cache is closed, and the phenomenon that wrong data is read when cache data is hit due to the writing of the physical address is avoided; meanwhile, the capacity of the cache is changed, and the hit rate of the cache is influenced;
the memory protection module comprises a memory protection page attribute register, a memory protection fault register and a memory protection lock register; the memory protection fault register comprises a memory protection fault address register, a memory protection fault state register and a memory protection fault zero clearing register; the memory protection fault address register records fault address information, the memory protection fault state register records the ID and the operation content of the fault operation host, and the memory protection fault clear register clears the information of the memory protection fault address register and the memory protection fault state register;
the memory protection lock register comprises a memory lock enabling register, four memory protection key registers, a memory protection lock command register and a memory protection lock state register; the memory protection lock register selectively stores the key according to the requirement;
the attribute register of the memory protection page is used for controlling the access authority of an administrator mode and a user mode when the SRAM is operated.
2. The two-level cache controller architecture of claim 1, wherein the bandwidth management module comprises:
the DSP arbitrates the control register, control the priority and maximum waiting time of CPU operation;
an IDMA arbitration control register for controlling the priority and the maximum waiting time of the IDMA operation;
an SDMA arbitration control register for controlling the priority and the maximum waiting time of the SDMA operation;
and the user consistency arbitration control register controls the priority and the maximum waiting time of the consistency operation.
3. The secondary cache controller architecture of claim 1, wherein the global coherency operation circuit synchronizes a cache and a system; the block coherency operation circuit targets block data, which is defined by a base address and a word size in an associated memory mapped register.
4. The secondary cache controller structure of claim 1, wherein each page attribute register controls a storage space of the secondary cache controller, and the number of page attribute registers is set to be appropriate according to the size of a storage bank of the secondary cache controller.
5. The secondary cache controller architecture of claim 1, wherein when the secondary cache controller performs the dirty bit replacement operation, dirty data is written to a victim buffer first, then newly allocated data is written, and subsequent write back to the low-level memory is performed in the background, reducing performance loss.
6. The secondary cache controller architecture of claim 1, wherein the secondary cache controller is connected to L1D through a snoop circuit, a victim buffer circuit stores victim data, and a write buffer circuit stores write information in the event of a write miss in L1D, reducing latency of the DSP core.
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| EP0987625A2 (en) * | 1998-09-01 | 2000-03-22 | Texas Instruments Incorporated | Microprocessor with a plurality of functional units and cache levels |
| CN102012872A (en) * | 2010-11-24 | 2011-04-13 | 烽火通信科技股份有限公司 | Level two cache control method and device for embedded system |
| CN102567256A (en) * | 2011-12-16 | 2012-07-11 | 龙芯中科技术有限公司 | Processor system, as well as multi-channel memory copying DMA accelerator and method thereof |
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| EP0987625A2 (en) * | 1998-09-01 | 2000-03-22 | Texas Instruments Incorporated | Microprocessor with a plurality of functional units and cache levels |
| CN102012872A (en) * | 2010-11-24 | 2011-04-13 | 烽火通信科技股份有限公司 | Level two cache control method and device for embedded system |
| CN102567256A (en) * | 2011-12-16 | 2012-07-11 | 龙芯中科技术有限公司 | Processor system, as well as multi-channel memory copying DMA accelerator and method thereof |
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