CN113190473A

CN113190473A - Cache data management method and medium based on energy collection nonvolatile processor

Info

Publication number: CN113190473A
Application number: CN202110483538.2A
Authority: CN
Inventors: 王艳; 房贺年; 邓霞; 李先睿
Original assignee: Guangzhou University
Current assignee: Guangzhou University
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2021-07-30
Anticipated expiration: 2041-04-30
Also published as: CN113190473B

Abstract

The invention discloses a cache data management method and medium based on an energy collection nonvolatile processor, which comprises the steps of firstly carrying out logic partitioning on an MLC STT-RAM of a nonvolatile memory to form a soft block and a hard block; setting a data state machine aiming at a soft block obtained after a volatile memory SRAM block and a nonvolatile memory are logically partitioned; based on the size relation between the NVP energy surplus Q and the high energy threshold and the low energy threshold, a final management method is determined, wherein the final management method comprises the processes of executing cache management, executing pre-backup and backup, and the cache management method is managed according to the hit position and the read-write operation of the target block TB, so that data with read sensitivity is loaded in a soft block as much as possible, and data with write sensitivity is distributed in an SRAM block as much as possible.

Description

Cache data management method and medium based on energy collection nonvolatile processor

Technical Field

The invention relates to the technical field of data backup, in particular to a cache data management method and medium based on an energy collection nonvolatile processor.

Background

The rapid development of the 5G wireless communication technology and the internet of things technology enables wearable portable mobile devices and implantable devices with high performance and small volume to have a new trend in the fields of internet and many industries, such as medical treatment and health monitoring, environmental monitoring and traffic control, and the attention and demand of the wearable portable mobile devices and implantable devices are continuously improved. Wearable devices have a complex operating environment and the requirement of portability, making large size and heavy batteries no longer an ideal energy source. Furthermore, the disadvantage of the frequent need for battery charging makes it no longer suitable for new embedded devices operating in complex and diverse environments. Self-powered systems therefore have come to light, including ambient energy harvesting power sources or data collection devices that capture energy from the surrounding environment through energy harvesting and conversion techniques. The energy source may be solar energy, thermal energy, wind energy, radio frequency, piezoelectric, etc. However, ambient environmental changes are often difficult to predict, which results in an unstable energy supply. Therefore, systems employing conventional volatile processors lose current computing schedules when power is lost, require restarting the system to perform computations when power is restored, and frequent shut-downs and restarts place a significant additional burden on the limited power budget.

Currently, many scholars have proposed a nonvolatile processor (NVP) to solve the above-mentioned problems. In NVP, nonvolatile memory (NVM) is embedded on the processor as a backup cache. The nonvolatile processor system can backup data in the volatile memory and the current calculation progress to the nonvolatile memory when the power is off, and obtain the calculation state and the data saved when the power is off from the backup when the power is restored, so that the system is ensured to be quickly restored and continuously executed. Among the emerging NVM technologies, spin transfer torque magnetic memory (STT-RAM) is a promising memory technology due to its higher storage density, competitive read time, and lower leakage power consumption. The STT-RAM may operate in Single Level Cell (SLC) or multi-level cell (MLC) mode. In NVP, many scholars are dedicated to research on optimizing the backup process to improve the system performance and reduce the system energy consumption on the premise of ensuring the successful backup.

Backup optimization is mainly focused on data backup in a main memory and a nonvolatile cache, and most of the existing backup technologies adopt an instant backup technology, namely, when a system is powered off, backup is performed immediately, and even if energy is recovered immediately, backup operation is required, so that backup redundancy and unnecessary recovery rollback operation are caused, a large amount of energy is wasted, and energy burden is increased.

Disclosure of Invention

The first purpose of the present invention is to overcome the disadvantages and shortcomings of the prior art, and to provide a cache data management method based on an energy-harvesting nonvolatile processor, which can improve the system performance on the premise of fully utilizing the cache space and ensuring the success of backup, and effectively reduce the backup redundancy and reduce the backup overhead.

The invention also provides a cache data management device based on the energy collection nonvolatile processor.

A third object of the present invention is to provide a storage medium.

It is a fourth object of the invention to provide a computing device.

The first purpose of the invention is realized by the following technical scheme: a cache data management method based on an energy collection nonvolatile processor is characterized in that the cache of the nonvolatile processor is a mixed cache based on a nonvolatile memory, and comprises a volatile memory SRAM and a nonvolatile memory MLC STT-RAM; the method comprises the following steps:

carrying out logical partitioning on an MLC STT-RAM of a nonvolatile memory, and forming a soft block and a hard block after the logical partitioning;

setting an n-bit register for each volatile memory SRAM block and nonvolatile soft block, wherein each cache block correspondingly comprises 2ⁿA state, when the cache block starts to enter the cache, the initial state is S₀Entering the next state every time a transition time T elapses, and if a read or write access operation occurs, resetting the state of the cache block to the initial state S₀Otherwise, if at (2)ⁿ-1) x T, no access operation occurs on the cache block, and the cache block will reach

State and hold this state until the cache block is accessed or replaced;

acquiring NVP energy residual quantity Q, and comparing the energy residual quantity Q with a high energy threshold value theta 1 and a low energy threshold value theta 2, wherein:

if the energy residual quantity Q is larger than the high energy threshold value theta 1, performing cache management, including performing the following exchange operation according to the data state and the hit position of the target block TB and the read-write operation of the target block TB:

exchanging a target block TB with the read operation times cold value exceeding a threshold value C in the SRAM block with a soft block with the maximum write operation times heat value;

exchanging a target block TB with the write operation frequency heat value exceeding a threshold value H in soft with an SRAM block with the maximum read operation frequency cold value;

transferring the target block TB in the hard to an SRAM or soft block, and if the SRAM and the soft are full, exchanging the target block TB with the block with the largest data state in the SRAM and soft blocks;

will be in the SRAM data state

Migrating the data block to a hard block;

if the energy remaining quantity Q is smaller than or equal to a high energy threshold value theta 1 and larger than a low energy threshold value theta 2, performing pre-backup, determining the number of hard blocks to be cleared according to the number of dirty SRAM blocks, judging whether the hard blocks to be cleared are dirty hard blocks or not, and backing up data in the dirty hard blocks in a main memory;

if the energy residual quantity Q is less than or equal to the low energy threshold value theta 2, executing backup of the dirty SRAM blocks, and backing up the dirty SRAM blocks into the hard blocks of the clear data;

and when the energy is recovered, namely when the call comes in, immediately stopping backup and recovering execution.

Preferably, before logical partitioning, in each MLC STT-RAM block, 1/2 is soft bit, 1/2 is hard bit, when the MLC STT-RAM is logically partitioned, every two adjacent physical blocks are coupled, and each MLC STT-RAM block is a soft block or a hard block, wherein the number of the soft blocks is the same as that of the hard blocks.

Preferably, when performing cache management, the following process is further included: when the target block TB is not hit, firstly judging whether a space exists in an SRAM block and a soft block;

if yes, the target block TB enters a corresponding position;

if not, searching the block with the maximum data state in the SRAM block and the soft block and then replacing; and determines whether the hard block is full,

if not, writing the replaced block of the SRAM block or soft block into an empty hard block;

if the block is full, acquiring a hard block with the current most prior data stored, and determining whether the hard block is a dirty block;

if yes, removing the data in the hard block and writing the removed data back to a main memory, then writing the replaced block of the SRAM block or soft block into the hard block, and updating the time for storing the data into the hard block;

if not, the data in the hard block is removed, then the block with the replaced SRAM block or soft block is written into the hard block, and the time for storing the data into the hard is updated.

Preferably, the state values increase sequentially for each SRAM block and soft block from the initial state to the last state.

Furthermore, when performing cache management, setting a cold value and a threshold value C for each SRAM block, and recording the number of times of data reading operation in the SRAM block through the cold value; setting heat values and threshold values H for each soft block, and recording the times of data write operation in the soft blocks through the heat values; and acquiring the states of each SRAM block and each soft block;

the specific process of cache management is as follows:

step 1, initializing variable values, including initializing cold values of each SRAM block and heat values of each soft block;

step 2, accessing the cache, inquiring whether the target block TB is hit, if so, executing the step 3, otherwise, executing the step 7;

and 3, executing the following block exchange operation according to the hit position of the target block TB and the read-write operation of the target block TB:

when the target block TB is positioned in the SRAM block and a read operation occurs, executing the step 4;

when the target block TB is located in the soft block and the write operation occurs, executing the step 5;

when the target block TB is located in the hard block, step 6 is executed;

will be in the SRAM data state

Migrating the data block to a hard block;

and 4, adding 1 to the cold value of the SRAM block where the target block TB is located, judging whether the cold value reaches a threshold value C or not, if so, exchanging the target block TB in the SRAM block with the soft block with the largest heat value of the write operation times, initializing the cold value of the SRAM block and the heat value of the soft block after exchanging, and setting the states of the SRAM block and the soft block as S₀；

Step 5, adding 1 to the heat value of the soft block where the target block is located, judging whether the heat value reaches a threshold value H, and if so, exchanging the target block TB in the soft with the SRAM block with the largest cold value; after the exchange, initializing the cold value of the SRAM block and the heat value of the soft block, and setting the states of the SRAM block and the soft block as S₀；

Step 6, transferring the target block TB in the hard to an SRAM or soft block, and if the SRAM and the soft are full, exchanging the target block TB with the block with the largest data state, namely the largest state value, in the SRAM and soft blocks; when the block with the maximum data state is the SRAM, the target block TB is exchanged into the SRAM block, the cold value of the SRAM block is initialized, and the state of the SRAM block is set to be S₀(ii) a When the block with the maximum state value is a soft block, the target block TB is switched to the soft block, and the heat value of the soft block is initialized, wherein the state of the soft block is set to S₀；

Step 7, firstly judging whether a space exists in the SRAM block and the soft block;

if yes, the target block TB enters a corresponding position;

if not, searching the block with the maximum data state, namely the maximum state value, in the SRAM block and the soft block, then replacing, initializing the cold value or the heat value corresponding to the SRAM block or the soft block with the maximum state value, and setting the state as S₀(ii) a And determines whether the hard block is full,

Further, when the backup is performed with the remaining amount of energy Q equal to or less than the low energy threshold θ 2, the interval time Re _ time from the power-off to the recovery is defined according to the retention time, and the size of the time t at which the remaining amount of energy Q equal to or less than the low energy threshold θ 2 occurs is determined, wherein:

when the time t is less than the interval time Re _ time, the dirty SRAM blocks with the state values from large to small are backed up in sequence within the time range from the occurrence of the energy surplus Q being less than or equal to the low energy threshold value theta 2 to the energy recovery, namely, the power is obtained, and the backup is stopped when the energy recovery is supplied;

when the time t is greater than the interval time Re _ time, backup is performed for all dirty SRAM blocks.

Preferably, the high energy threshold θ 1 is: θ 1 — e1+ e2, and the low energy threshold θ 2 is: θ 2 ═ e 2; wherein e1 is the energy consumption required for successfully backing up all dirty SRAM blocks, and e2 is the energy consumption required for backing up all SRAM blocks into hard;

e1＝num_hard×write_energy_to_main_memory；

where num _ hard is the number of hard blocks, write _ energy _ to _ main _ memory represents the energy consumption to write the hard blocks to main memory;

e2＝num_SRAM×write_energy_to_hard；

where num _ SRAM is the number of SRAM blocks and write _ energy _ to _ hard represents the energy consumption to write an SRAM block to hard.

The second purpose of the invention is realized by the following technical scheme: a cache data management device based on an energy collection nonvolatile processor, wherein the cache of the nonvolatile processor is a mixed cache based on a nonvolatile memory, and comprises a volatile memory SRAM and a nonvolatile memory MLC STT-RAM; the device comprises:

a partitioning module: the system comprises a nonvolatile MLC STT-RAM, a soft block and a hard block, wherein the STT-RAM is used for carrying out logical partitioning on the nonvolatile MLC STT-RAM, and the soft block and the hard block are formed after the logical partitioning;

a data state machine setting module used for setting n-bit registers for each volatile memory SRAM block and nonvolatile soft block, each cache block correspondingly comprises 2ⁿA state, when the cache block starts to enter the cache, the initial state is S₀Entering the next state every time a transition time T elapses, and if a read or write access operation occurs, resetting the state of the cache block to the initial state S₀Otherwise, if at (2)ⁿ-1) x T, no access operation occurs on the cache block, and the cache block will reach

State and hold this state until the cache block is accessed or replaced;

the comparison module is used for acquiring the NVP energy surplus Q and comparing the energy surplus Q with a high energy threshold value theta 1 and a low energy threshold value theta 2;

the cache management module is used for executing cache management when the energy surplus Q is larger than a high energy threshold value theta 1, and comprises the following steps of executing exchange operation according to the hit position of the target block TB and the read-write operation of the target block TB:

the method comprises the steps that a target block TB with the read operation times cold value exceeding a threshold value C in an SRAM block and a soft block with the maximum write operation times heat value are exchanged;

the SRAM switching method comprises the steps that a target block TB with the write operation times heat value exceeding a threshold value H in soft is exchanged with an SRAM block with the read operation times cold value being maximum;

the method is used for transferring a target block TB located in the hard to an SRAM or soft block, and if the SRAM and the soft are full, the target block TB is exchanged with a block with the largest data state in the SRAM and soft blocks;

for placing data in SRAM in the state of

Migrating the data block to a hard block;

the pre-backup module is used for executing pre-backup when the energy surplus Q is less than or equal to a high energy threshold value theta 1 and greater than a low energy threshold value theta 2, determining the number of hard blocks to be cleared according to the number of dirty SRAM blocks, judging whether the hard blocks to be cleared are dirty hard blocks or not, and backing up data in the dirty hard blocks in a main memory;

and the backup module is used for executing backup of the dirty SRAM blocks when the energy surplus Q is less than or equal to the low energy threshold theta 2, backing up the dirty SRAM blocks into the hard blocks for clearing the data, backing up the data in the dirty hard blocks into the main memory, and immediately stopping the backup and restoring the execution when the energy is restored, namely the incoming call is received.

The third purpose of the invention is realized by the following technical scheme: a storage medium stores a program that, when executed by a processor, implements a cache data management method based on an energy harvesting nonvolatile processor according to a first object of the present invention.

The fourth purpose of the invention is realized by the following technical scheme: a computing device comprises a processor and a memory for storing processor executable programs, and when the processor executes the programs stored in the memory, the cache data management method based on the energy collection nonvolatile processor achieves the first object of the invention.

Compared with the prior art, the invention has the following advantages and effects:

(1) according to the cache data management method based on the energy collection nonvolatile processor, firstly, logic partitioning is carried out on a nonvolatile memory MLC STT-RAM, so that a soft block and a hard block are formed after the logic partitioning; setting a data state machine aiming at the volatile SRAM block and the nonvolatile soft block obtained after partitioning; and determining a final management method based on the size relation between the NVP energy surplus Q and the high energy threshold value theta 1 and the low energy threshold value theta 2, wherein the final management method comprises the processes of executing cache management, executing pre-backup and backup. The cache management method includes that soft blocks formed after MLC STT-RAM logic partitioning participate in data caching, cache space is increased, cache hit rate is improved, in addition, data migration replacement is carried out according to hit positions and read-write operations of target blocks TB, read-sensitive data are loaded in the soft blocks as much as possible after execution, and write-sensitive data are distributed in SRAM blocks as much as possible. Therefore, the execution of the cache management can effectively improve the performance and reduce the energy consumption. Before entering a backup stage, a pre-backup scheme is executed, a hard space serving as a buffer area is cleared, and preparation is made for a possible backup stage later, so that successful backup work can be effectively realized when the residual energy is too low. Therefore, the method can improve the system performance on the premise of fully utilizing the cache space and ensuring the backup success.

(2) In the cache data management method based on the energy collection nonvolatile processor, when cache hit and miss occur replacement in the cache management process, if the SRAM and soft have no space, the block with the largest data state is selected for replacement, and the replaced block is temporarily stored in the hard buffer area.

(3) In the cache data management method based on the energy collection nonvolatile processor, the cache management method is executed under the condition of sufficient residual energy, the space of the MLC STT-RAM is fully utilized, the system performance is ensured, the energy consumption is reduced, and particularly after the MLC STT-RAM is logically partitioned, the write delay of the soft block is about half of that of the hard block, so the soft block is more suitable for data caching, but the write delay of the soft block is still higher than that of the SRAM, therefore, the method provided by the invention has two aspects from the aspects of performance and energy consumption: first, the read sensitive data should be loaded in the soft block as much as possible, with the SRAM containing most of the write sensitive data. Secondly, when the cache miss occurs replacement, the density of the hard block in the MLC STT-RAM can be utilized to use the hard block as a buffer area to temporarily store the replaced data instead of directly writing the replaced data back to the main memory, and the communication overhead between the cache and the main memory is reduced.

In addition, to identify cache behavior, the method of the present invention sets a variable cold for each SRAM block to indicate the number of times a read operation occurs, and a variable heat for each soft block after MLC STT-RAM logical partitioning to record a reset to state S due to a write operation₀In order to ensure that more read sensitive data are loaded into a soft block of an MLC STT-RAM, the method sets a threshold value C for the variable cold, and if a target block TB accessing the cache is positioned in an SRAM block and read operation occurs, the value of the cold of the block is increased by 1; if the value of cold is equal to the threshold value C, the block should be swapped with the soft block with the largest heat value, and the corresponding variables cold and heat of the two blocks are set to 0, and the status is set to S₀. Similarly, to ensure that more write operations occur in the SRAM, we set a threshold H for the variable heat, when the target block TB is in the soft block and a write operation occurs, its heat value increases by 1, when the heat value reaches a predetermined threshold H, this means that a write operation frequently occurs in the soft block, so this block is swapped with the SRAM block with the largest cold value, and the swapped cold and heat are reset to 0, and the state is set to S₀. If a cache hit occurs in a hard block, the block will be migrated to either an SRAM block or a soft block. If neither the SRAM nor soft block has room to load the block, we will select the block with the largest state to swap and change the corresponding variable and state values. When cache hit loss occurs, according to a mapping replacement strategy, if the SRAM and soft have no space, the block with the maximum state value is selected for replacement, and the replaced block is replacedTemporarily stored in a hard buffer. If the hard buffer is full, we select the hard block where the current most prior data is stored to hold the replacement block, if the hard block is a dirty block, where the culled data is written to main memory.

(4) The invention relates to a cache data management method based on an energy collection nonvolatile processor, which comprises the steps of before logic partitioning, coupling adjacent physical blocks in each MLC STT-RAM block, wherein 1/2 is a soft bit, 1/2 is a hard bit, when logic partitioning is carried out on the MLC STT-RAM, obtaining that each MLC STT-RAM block is a soft block or a hard block, and obtaining the same quantity of soft blocks and hard blocks after logic partitioning of the MLC STT-RAM on the basis of the soft bits and the hard bits. The space of the device is fully utilized.

(5) In the cache data management method based on the energy collection nonvolatile processor, after the backup stage is started, the interval time Re _ time from power failure to recovery is defined according to the retention time, and the size of the time t when the energy surplus Q is smaller than the low energy threshold theta 2 is judged, wherein: when the time t is less than the interval time Re _ time, only the dirty SRAM block with a larger state value needs to be backed up; when the time t is greater than the interval time Re _ time, backup is performed for all dirty SRAM blocks. Therefore, the method of the invention reduces redundancy and overhead of backup by sensing the data state and the possibility of energy recovery in the backup stage.

Drawings

FIG. 1 is a flow chart of a method for cache data management based on an energy harvesting non-volatile processor according to the present invention.

FIG. 2 is a schematic diagram of the structure of a cache set model in the method of the present invention.

FIG. 3 is a schematic diagram of MLC STT-RAM logical partition in the method of the present invention.

FIG. 4 is a schematic diagram of data state identification in the method of the present invention.

FIG. 5 is a flow chart of the cache management implementation of the method of the present invention.

Detailed Description

The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited thereto.

Example 1

The embodiment discloses a cache data management method based on an energy collection nonvolatile processor, wherein a cache constructed by the nonvolatile processor is a hybrid cache based on a nonvolatile memory, and the nonvolatile processor comprises a hybrid cache (cache) and a nonvolatile main memory (main memory). In this architecture, the register file can be fully backed up by non-volatile flip-flop (NVFF) technology, and the hybrid cache consists of volatile memory (SRAM) and non-volatile memory (MLC STT-RAM). As shown in fig. 1, the method of the present embodiment includes the steps of:

and step S1, carrying out logical partitioning on the MLC STT-RAM of the nonvolatile memory, and forming a soft block and a hard block after the logical partitioning.

The size of each MLC STT-RAM block is 2 times that of each SRAM block. Prior to logical partitioning, in each MLC STT-RAM block, 1/2 is the soft bit and 1/2 is the hard bit. When the MLC STT-RAM is logically partitioned, adjacent physical blocks are coupled, and each MLC STT-RAM block is a large soft block or a large hard block, the number of the large soft blocks is the same as that of the large hard blocks, and the large soft blocks and the large hard blocks comprise m/2 large soft blocks and m/2 large hard blocks, wherein m is the number of the MLC STT-RAM blocks. Thus, in the N-way set associative mapping shown in FIG. 2, each cache set contains N/2SRAM blocks, N/2 MLC STT-RAM blocks after logical partitioning, N/4 large soft blocks and N/4 large hard blocks after logical partitioning of the N/2 MLC STT-RAM blocks, each large soft block can be divided into two soft blocks with the same size as the SRAM blocks, i.e., one soft block and one SRAM block are equal in size, each large hard block can be divided into two hard blocks with the same size as the SRAM blocks, i.e., one hard block and one SRAM block are equal in size, so the N/2 STT-RAM blocks after logical partitioning comprise N/2 soft blocks and N/2 hard blocks, as shown in FIG. 2. As shown in FIG. 3, the hard/soft logical partition is explained by taking 4-way set associative as an example, given a physical block with a capacity of 64B, which contains 256 MLC STT-RAM memory cells, wherein the hard bits and the soft bits are half of each, the logical partition couples adjacent physical blocks (Line0 and Line1, Line2 and Line3), and the new MLC STT-RAM block is formed as a pure soft block or hard block. For read operations, the delay before and after MLC STT-RAM logic is almost equivalent to SRAM. For write operations, after implementing logical partitioning, the write latency of the soft block is about 50% of the original MLC STT-RAM, while the hard block is about 14% slower than the original MLC CSTT-RAM due to coupling breaks. Based on this, soft blocks after logical partitioning are more suitable for data caching, and hard blocks can also be reasonably used for improving system performance and providing space for backup in NVP.

Step S2, for each SRAM block and soft block, introducing a data state mechanism based on application feature retention time, specifically as follows:

setting an n-bit register for each cache block comprising a volatile SRAM block and a nonvolatile soft block, wherein each cache block correspondingly comprises 2ⁿA state, the state of each cache block depends on its access operation and retention time, the initial state is S when the cache block starts to enter the cache₀Entering the next state every time a transition time T elapses, and if a read or write access operation occurs, resetting the state of the cache block to S₀Otherwise, if at (2)ⁿ-1) x T, no access operation occurs on the cache block, and the cache block will reach

State and hold this state until the cache block is accessed or replaced; in the cache block, the corresponding state values sequentially increase from the initial state to the last state. For example, a 2-bit register is provided for each SRAM and soft block, with 4 possible states for each block, respectively state S₀、S₁、S₂ and S₃State S₀To S₃The state values of (1) are sequentially increased, as shown in fig. 4, when a new block enters the cache, the initial state is S₀After every conversion time T (T ═ retention time/4), the system will go to nextOne state. If a read or write operation occurs, the state will be reset to S₀. Otherwise, if at (2)ⁿ-1) x T, no access operation has occurred on the cache block, and the block will reach

State and hold this state until reset or replaced. In this embodiment, the data state may also be used for a potential cache replacement algorithm, since the state is

The block in (1) represents the least recently used block with the state of S₀。

Step S3, obtaining NVP energy residual quantity Q, comparing the energy residual quantity Q with a high energy threshold value theta 1 and a low energy threshold value theta 2, and judging the size relation between Q and the high energy threshold value theta 1 and the low energy threshold value theta 2, wherein:

(1) if the energy surplus Q is larger than a high energy threshold value theta 1, performing cache management, in the process of performing cache management, if the target block TB is hit, performing (1-1), and if the target block TB is not hit, performing (1-2);

(1-1), performing the exchange operation of the following blocks according to the hit position of the target block TB and the read-write operation of the target block TB:

(1-1-1), exchanging a target block TB with the reading operation times cold value exceeding a threshold value C in the SRAM block with a soft block with the largest writing operation times heat value;

(1-1-2) exchanging a target block TB with the write operation times heat value exceeding a threshold value H in soft with an SRAM block with the maximum read operation times cold value;

(1-1-3) transferring the target block TB located in the hard to an SRAM or soft block, and if the SRAM and the soft are full, exchanging the target block TB with the block with the largest data state in the SRAM and soft blocks;

(1-1-4) State of data in SRAM

Migrating the data block to a hard block;

(1-2) firstly judging whether a space exists in the SRAM block and the soft block; if yes, the target block TB enters a corresponding position; if not, searching the block with the maximum data state in the SRAM block and the soft block and then replacing; and determines whether the hard block is full,

(2) And if the energy remaining quantity Q is less than or equal to the high energy threshold value theta 1 and greater than the low energy threshold value theta 2, performing pre-backup, determining the number of hard blocks to be cleared according to the number of dirty SRAM blocks, judging whether the hard blocks to be cleared are dirty hard blocks, and backing up data in the dirty hard blocks in the main memory.

In this embodiment, the cleared space may contain all dirty SRAM blocks, considering the worst case, i.e., all SRAM blocks are dirty blocks. Based on the cache set model in the architecture, the number of SRAM blocks is equal to the number of hard blocks. Thus, we can ensure that hard blocks can be cleared to ensure success of the backup. The number of invalid and clean hard blocks and dirty SRAM blocks determines whether some hard blocks need to be cleared and written to main memory; thereafter, if the energy does not drop to the low threshold, the program may continue running using the remaining blocks.

(3) If the energy remaining quantity Q is less than or equal to the low energy threshold value theta 2, namely the system enters a sleep mode, the remaining energy is used for executing backup of the dirty SRAM blocks, the dirty SRAM blocks are backed up to the hard blocks with data cleared, the data in the dirty hard blocks are backed up to a main memory, and when the energy is recovered, namely when a call comes, the backup is immediately stopped, the execution is recovered, namely, the program which is stopped to be executed due to the backup is recovered;

in the present embodiment, when the remaining amount of energy Q is equal to or less than the low energy threshold θ 2 to perform backup, an interval time Re _ time from power-off to recovery (Re _ time < retention time) is defined according to the retention time, and the size of the time t at which the remaining amount of energy Q is less than the low energy threshold θ 2 is determined to occur, where:

(3-1) when the time t is less than the interval time Re _ time, sequentially backing up the dirty SRAM blocks with the state values from large to small in the time range from the occurrence of the energy residual quantity Q being less than or equal to the low energy threshold value theta 2 to the energy recovery, namely, the power acquisition, and stopping the backup when the energy recovery is supplied; for example, only the dirty SRAM block with the largest state value is backed up.

And (3-2) when the time t is greater than the interval time Re _ time, backing up all the dirty SRAM blocks.

In this embodiment, when performing cache management in step S3, a cold value and a threshold C are set for each SRAM block, and the number of times of data read operation in the SRAM block is recorded by the cold value; setting heat values and threshold values H for each soft block, and recording the times of data write operation in the soft blocks through the heat values; and acquiring the states of each SRAM block and each soft block; as shown in fig. 5, the specific process of cache management in step S3 is as follows:

step 1, initializing variable values, including initializing cold values of each SRAM block and heat values of each soft block. In this embodiment, the cold value of each SRAM block and the heat value of each soft block are initialized to 0.

when the target block TB is located in the hard block, step 6 is executed;

will be in the SRAM data state

Migrating the data block to a hard block;

and 4, adding 1 to the cold value of the SRAM block where the target block TB is located, judging whether the cold value reaches a threshold value C or not, if so, exchanging the target block TB in the SRAM block with the soft block with the largest heat value of the write operation times, initializing the cold value of the SRAM block and the heat value of the soft block to be 0 after exchanging, and setting the states of the SRAM block and the soft block to be S₀(ii) a Otherwise, the state value of the SRAM block is reset according to the read operation.

Step 5, adding 1 to the heat value of the soft block where the target block TB is located, judging whether the heat value reaches a threshold value H, and if so, exchanging the target block TB in the soft with the SRAM block with the largest cold value; after the swap, the cold value of the SRAM block and the heat value of the soft block are initialized to 0, and the states of the SRAM block and the soft block are set to S₀(ii) a Otherwise, the state value of the soft block is reset according to the write operation.

Step 6, transferring the target block TB in the hard to an SRAM or soft block, and if the SRAM and the soft are full, exchanging the target block TB with the block with the largest data state, namely the largest state value, in the SRAM and soft blocks; when the block with the maximum state value is the SRAM, the target block TB is exchanged into the SRAM block, the cold value of the SRAM block is initialized to 0, and the state of the SRAM block is set to S₀(ii) a When the block with the maximum state value is a soft block, the target block TB is switched into the soft block, the heat value of the soft block is initialized to 0, and the state of the soft block is set to S₀；

if yes, the target block TB enters a corresponding position;

if not, searching the block with the maximum data state, namely the maximum state value, in the SRAM block and the soft block, then replacing, initializing the cold value or the heat value corresponding to the SRAM block or the soft block with the maximum state value to 0, and setting the state to S₀(ii) a And determining whether a hard block is presentWhen the container is full of the liquid, the liquid is filled in the container,

if yes, acquiring the hard block with the most prior data stored in all the current hard blocks, and determining whether the hard block is a dirty block;

Based on the cache management process, for each cache access, the migration replacement policy of data is determined according to the variable value cold of the SRAM, the variable value heat of soft, the threshold C, the threshold H, and the state S. And (4) assuming that the target block accessed each time is TB, and judging whether the cache is hit according to the mapping rule. If a cache hits, there may be three cases depending on the hit location: 1. if the TB exists in the hard, the TB needs to be transferred to the SRAM or the soft, if the SRAM and the soft are full, the data block with the largest state value in the SRAM and the soft is selected for exchange, and the cold or heat value and the state value are reset according to the TB entry position. 2. And the TB is positioned in the SRAM, if the TB is read, 1 is added to the cold value of the TB, whether the cold value is equal to the threshold value C or not is judged, if the cold value is equal to the threshold value C, a data block with a larger heat value in soft is selected for exchange, and the variable value and the state value are reset. Otherwise only the state value of TB needs to be reset. 3. And the TB is positioned in soft, similarly to the case 2, if the TB is in the write operation, heat is added with 1, whether the TB is equal to the threshold H or not is judged, if the TB is equal to the threshold H, data with a large cold value in the SRAM is selected for block exchange, and the variable value and the state value of the TB are changed. Otherwise only the state value of TB needs to be reset. If the cache is not hit, firstly judging whether vacant spaces exist in the soft and the SRAM, if so, replacing is not needed, directly entering the target block TB into the vacant spaces of the soft or the SRAM, and otherwise, selecting the data block with the largest state value in the SRAM and the soft for replacing. And putting the replaced data blocks in the SRAM and the soft into the hard, directly storing the replaced data blocks in the hard if the hard is not full, acquiring the hard block in which the current most prior data is stored if the hard is full, removing the data in the hard block, storing the removed data in the SRAM and the soft into the replaced data blocks in the soft, updating the time for storing the data in the hard, and writing the removed data in the hard back into the main memory if the hard block is a dirty block.

Considering the situation of power failure and fast recovery, when the available energy is lower than or equal to the low energy threshold, all dirty blocks in the SRAM need to be backed up to hard blocks. However, if the voltage is restored during the backup process, the backup will be stopped to minimize backup redundancy. Therefore, the present embodiment method defines an interval time Re _ time from power-off to recovery (Re _ time < retention time) according to the retention time. If the power-off time is less than the time Re _ time, only the dirty blocks with larger state values need to be backed up, and the data blocks with small state values are reserved. Otherwise, all dirty blocks in the SRAM are backed up. In this embodiment, the high energy threshold θ 1 is: θ 1 — e1+ e2, and the low energy threshold θ 2 is: θ 2 ═ e 2; wherein e1 is the energy consumption required for successfully backing up all dirty SRAM blocks, and e2 is the energy consumption required for backing up all SRAM blocks into hard;

e1＝num_hard×write_energy_to_main_memory；

e2＝num_SRAM×write_energy_to_hard；

where num _ SRAM is the number of SRAM blocks and write _ energy _ to _ hard represents the power consumption for writing to hard by the SRAM blocks.

The method of the embodiment reduces the rollback and backup overhead generated by the power-off system under the condition of successful backup through the steps as follows: the energy-collectable nonvolatile processor is used for collecting energy to supply to equipment by depending on the external environment, so that the nonvolatile processor has the characteristic of energy instability, data needs to be backed up from the volatile memory to the nonvolatile memory when power is off, and the data needs to be restored when energy is restored; in order to ensure data consistency, the conventional method is to backup all volatile data into a nonvolatile memory, and an instant backup scheme is adopted, which can generate redundancy of backup and increase energy burden. And the method of the embodiment makes a data state marking mechanism and a data migration replacement strategy according to the retention time of the cache data, and determines whether the data is immediately backed up or not by sensing the data state information, the energy remaining state and the possibility of energy recovery, so that the redundancy of the backup is reduced, and the overhead of the backup is reduced. If only data blocks with larger state values need to be backed up in a short time, compared with the instant backup, the energy consumed by the backup can be reduced, and meanwhile, the replaced data blocks are stored by utilizing the hard buffer area, so that the expense of accessing the main memory is reduced.

In the method of the embodiment, when the capacity of the nonvolatile memory in the NVP is limited, the capacity of the nonvolatile memory is fully and reasonably utilized: in the method, the backup cache adopts a nonvolatile memory MLC STT-RAM, so that the STT-RAM always works in an MLC mode, the MLC STT-RAM is used for caching data and temporarily storing the replaced data when the energy is sufficient, and meanwhile, space is provided for the backup data when the power is off so as to ensure the success of the backup and fully utilize the space capacity of the backup. The method introduces MLC STT-RAM of logic partition, uses soft block as data buffer, uses hard block as buffer to temporarily store replaced block, raises buffer hit rate, reduces cost of accessing main memory, and provides space for backup. In addition, by sensing the data state during the backup phase and the possibility of energy recovery, redundancy and energy consumption of the backup are reduced.

Those skilled in the art will appreciate that all or part of the steps in the method according to the present embodiment may be implemented by a program to instruct the relevant hardware, and the corresponding program may be stored in a computer-readable storage medium. It should be noted that although the method operations of embodiment 1 are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Rather, the depicted steps may change the order of execution, and some steps may be executed concurrently. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.

Example 2

The embodiment 1 discloses a cache data management device based on an energy-harvesting nonvolatile processor, wherein a cache constructed by the nonvolatile processor is a hybrid cache based on a nonvolatile memory, and comprises a volatile memory SRAM and a nonvolatile memory MLC STT-RAM, and the device comprises:

State and hold this state until the cache block is accessed or replaced;

for placing data in SRAM in the state of

Migrating the data block to a hard block;

For specific implementation of each module in this embodiment, reference may be made to embodiment 1, and details are not described here. It should be noted that, the apparatus provided in this embodiment is only illustrated by dividing the functional modules, and in practical applications, the functions may be distributed by different functional modules according to needs, that is, the internal structure is divided into different functional modules to complete all or part of the functions described above.

Example 3

The present embodiment discloses a storage medium storing a program, which when executed by a processor, implements the cache data management method based on an energy harvesting non-volatile processor described in embodiment 1, as follows:

setting an n-bit register for each volatile memory SRAM block and nonvolatile soft blockEach cache block correspondingly comprises 2ⁿA state, when the cache block starts to enter the cache, the initial state is S₀Entering the next state every time a transition time T elapses, and if a read or write access operation occurs, resetting the state of the cache block to the initial state S₀Otherwise, if at (2)ⁿ-1) x T, no access operation occurs on the cache block, and the cache block will reach

State and hold this state until the cache block is accessed or replaced;

will be in the SRAM data state

Migrating the data block to a hard block;

The specific implementation process of the above steps is referred to as embodiment 1, and is not described herein again.

In this embodiment, the storage medium may be a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a Random Access Memory (RAM), a usb disk, a removable hard disk, or other media.

Example 4

The embodiment discloses a computing device, which includes a processor and a memory for storing a processor executable program, and when the processor executes the program stored in the memory, the method for managing cache data based on an energy collection nonvolatile processor as described in embodiment 1 is implemented as follows:

State and hold this state until the cache block is accessed or replaced;

will be in the SRAM data state

Migrating the data block to a hard block;

In this embodiment, the computing device may be a desktop computer, a notebook computer, a smart phone, a PDA handheld terminal, a tablet computer, or other terminal devices.

The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims

1. A cache data management method based on an energy collection nonvolatile processor is characterized in that an architectural cache of the nonvolatile processor is a mixed cache based on a nonvolatile memory, and comprises a volatile memory SRAM and a nonvolatile memory MLC STT-RAM; the method comprises the following steps:

setting an n-bit register for each volatile memory SRAM block and nonvolatile memory soft block, wherein each cache block correspondingly comprises 2ⁿA state, when the cache block starts to enter the cache, the initial state is S₀Entering the next state every time a transition time T elapses, and if a read or write access operation occurs, resetting the state of the cache block to the initial state S₀Otherwise, if at (2)ⁿ-1) x T, no access operation occurs on the cache block, the cache block will reach S₂ ⁿ _-1State and hold this state until the cache block is accessed or replaced;

the data state in SRAM is S₂ ⁿ _-1Migrating the data block to a hard block;

2. The method of claim 1, wherein, before logical partitioning, in each MLC STT-RAM block, 1/2 is a soft bit, 1/2 is a hard bit, and when logical partitioning is performed on the MLC STT-RAM, every two adjacent physical blocks are coupled to obtain that each MLC STT-RAM block is a soft block or a hard block, wherein the number of the soft blocks is the same as the number of the hard blocks.

3. The energy harvesting non-volatile processor-based cache data management method of claim 1, wherein when performing cache management, further comprising the process of: when the target block TB is not hit, firstly judging whether a space exists in an SRAM block and a soft block;

if yes, the target block TB enters a corresponding position;

4. The energy harvesting non-volatile processor-based cache data management method of claim 1, wherein for each SRAM block and soft block, the state values increase sequentially from an initial state to a last state.

5. The energy-harvesting nonvolatile-processor-based cache data management method according to claim 4, wherein when performing cache management, a cold value and a threshold C are set for each SRAM block, and the number of times of data read operations in the SRAM block is recorded by the cold value; setting heat values and threshold values H for each soft block, and recording the times of data write operation in the soft blocks through the heat values; and acquiring the states of each SRAM block and each soft block;

the specific process of cache management is as follows:

when the target block TB is located in the hard block, step 6 is executed;

the data state in SRAM is S₂ ⁿ _-1Migrating the data block to a hard block;

and 4, adding 1 to the cold value of the SRAM block where the target block TB is positioned, judging whether the cold value reaches a threshold value C, and if so, judging whether the cold value reaches the threshold value CExchanging the target block TB in the SRAM block with the soft block with the largest heat value of the write operation times, initializing the cold value of the SRAM block and the heat value of the soft block after exchanging, and setting the states of the SRAM block and the soft block as S₀；

if yes, the target block TB enters a corresponding position;

6. The energy-harvesting nonvolatile-processor-based cache data management method according to claim 4, wherein when the remaining amount of energy Q is equal to or less than the low energy threshold θ 2, a backup is performed, an interval time Re _ time from power-off to recovery is defined according to a retention time, and a size of a time t at which the remaining amount of energy Q is equal to or less than the low energy threshold θ 2 is determined, wherein:

7. The energy harvesting non-volatile processor-based cache data management method of claim 1, wherein the high energy threshold θ 1 is: θ 1 — e1+ e2, and the low energy threshold θ 2 is: θ 2 ═ e 2; wherein e1 is the energy consumption required for successfully backing up all dirty SRAM blocks, and e2 is the energy consumption required for backing up all SRAM blocks into hard;

e1＝num_hard×write_energy_to_main_memory；

e2＝num_SRAM×write_energy_to_hard；

8. The cache data management device based on the energy collection nonvolatile processor is characterized in that the cache architected by the nonvolatile processor is a mixed cache based on a nonvolatile memory, and comprises a volatile memory SRAM and a nonvolatile memory MLC STT-RAM; the device comprises:

a data state machine setting module used for setting n-bit registers for each volatile memory SRAM block and nonvolatile soft block, each cache block correspondingly comprises 2ⁿA state, when the cache block starts to enter the cache, the initial state is S₀Entering the next state every time a transition time T elapses, and if a read or write access operation occurs, resetting the state of the cache block to the initial state S₀Otherwise, if at (2)ⁿ-1) x T, no access operation occurs on the cache block, the cache block will reach S₂ ⁿ _-1State and hold this state until the cache block is accessed or replaced;

for setting data in SRAM to S state₂ ⁿ _-1Migrating the data block to a hard block;

9. A storage medium storing a program, wherein the program, when executed by a processor, implements the energy harvesting non-volatile processor-based cache data management method according to any one of claims 1 to 7.

10. A computing device comprising a processor and a memory for storing a program executable by the processor, wherein the processor, when executing the program stored in the memory, implements the method for managing cache data based on an energy harvesting non-volatile processor according to any one of claims 1 to 7.