CN113190301A

CN113190301A - User interface operation implementation method of FPGA platform

Info

Publication number: CN113190301A
Application number: CN202110338135.9A
Authority: CN
Inventors: 方磊; 倪常茂; 李勋龙
Original assignee: Wuhan Guide Infrared Co Ltd
Current assignee: Wuhan Guide Infrared Co Ltd
Priority date: 2021-03-30
Filing date: 2021-03-30
Publication date: 2021-07-30

Abstract

A user interface display method of an FPGA platform comprises the following steps: numbering all pictures needing to be displayed on a user interface; cutting all pictures into blocks with the same size according to a preset size, removing repeated blocks from all the blocks, and numbering the remaining blocks after the repeated blocks are removed; sequentially storing the block data into an RAM (random access memory) in the FPGA for caching according to the block numbers; counting the corresponding relation between the picture numbers and the block numbers, setting a corresponding counting table for each picture number, wherein the table entry numbers of the counting table correspond to the picture numbers, and each table entry comprises the block numbers and the combination modes of the pictures with the corresponding numbers; storing the corresponding relation statistical table of the picture numbers and the block numbers into an RAM (random access memory) cache inside the FPGA; updating the image queue to be displayed in real time according to the actual interaction and the display requirement of a user interface; and displaying an interface required by a user according to the picture queue required to be displayed. The invention does not need to use external storage such as DDR and the like, saves bandwidth and power consumption and is beneficial to the development of projects.

Description

User interface operation implementation method of FPGA platform

Technical Field

The invention relates to the field of user interface operation of an FPGA (field programmable gate array), in particular to a user interface operation implementation method of an FPGA platform.

Background

The conventional user interface operation based on the FPGA is generally realized based on DDR storage, all interface pictures required by an interface are cached in the DDR at first, and then the corresponding interface pictures in the DDR are read for operation and display according to the real-time interaction requirement.

The existing algorithm generally needs DDR as a cache, thereby occupying DDR bandwidth, increasing timing instability and increasing the power consumption of the whole machine to a certain extent; in addition, each interface picture needs DDR read burst, and the number of DDR read burst times which can be borne by the fixed row pixel points of the original image is very limited, so that the number of pictures which can be displayed on the same row is very limited.

Disclosure of Invention

In view of the above, the present invention has been developed to provide a method and system for big data statistics based on urban alien and resident people that overcomes or at least partially solves the above-mentioned problems.

In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:

the invention discloses a user interface display method of an FPGA platform, which comprises the following steps:

s100, numbering all pictures needing to be displayed on a user interface;

s200, cutting all pictures into blocks with the same size according to a preset size, obtaining repeated blocks after cutting, removing the repeated blocks from all the blocks, and numbering the remaining blocks after removing the repeated blocks;

s300, sequentially storing the block data into an RAM (random access memory) in the FPGA for caching according to the block numbers, wherein the caching addresses are from 0 to 0, and the block data are sequentially stored;

s400, counting the corresponding relation between the picture numbers and the block numbers, setting a corresponding counting table for each picture number, wherein each table entry number of the counting table corresponds to the picture number, and each table entry comprises the block number and the combination mode of the picture with the corresponding number;

s500, storing the corresponding relation statistical table of the picture numbers and the block numbers into an RAM (random access memory) in the FPGA for caching;

s600, updating a picture queue to be displayed in real time according to actual interaction and user interface display requirements;

and S700, displaying an interface required by a user according to the picture queue required to be displayed.

Further, all pictures were cut into equal-sized blocks in 16 rows in the horizontal and vertical directions.

Furthermore, when the user interface is cut and designed, the blocks with repeated numbers are preferentially used, so that the total number of the block numbers is smaller, and the cache used for subsequent storage is also smaller.

Further, the block combination method in the statistical table is as follows: the block numbers are arranged and combined from left to right and from top to bottom.

Further, the picture queue includes a corresponding relation statistical table entry of the picture number and the block number and a coordinate position of the picture display.

Further, according to the image queue to be displayed, the method for displaying the interface required by the user comprises the following steps: and reading corresponding table entry number information at a corresponding coordinate position according to the picture queue, then reading block data corresponding to respective block numbers, and displaying pictures according to respective display modes.

Further, the entry of the statistical table further includes a display mode including a picture or block number according to actual needs, specifically: font color in picture, background transparency.

The technical scheme provided by the embodiment of the invention has the beneficial effects that at least:

the user interface display method of the FPGA platform does not need to use external storage such as DDR and the like, saves bandwidth and power consumption, and uses few RAM resources in the FPGA. Particularly, aiming at the scheme with more reusable blocks in the picture, for example, setting an interactive interface with more character information such as a menu and the like, the reusability of the Chinese character information is very high. For image display, the method can basically cover all the row points of the displayable pictures of each row without the limitation of the number of the pictures of the user interface. Aiming at the dilemma that the current domestic FPGA platform is limited by the shortage of the type and the model of the current domestic DDR and other cache devices, the domestic FPGA platform is developed, the storage bandwidth is not used, is less used or is reduced, and the development of projects is greatly facilitated.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

fig. 1 is a flowchart of a method for displaying a user interface of an FPGA platform in embodiment 1 of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In order to solve the problems in the prior art, the embodiment of the invention provides a method for realizing user interface operation of an FPGA platform.

Example 1

The embodiment discloses a user interface display method of an FPGA platform, which comprises the following steps:

s100, numbering all pictures needing to be displayed on a user interface; specifically, the present embodiment may number all the pictures as ID0, ID1, ID 2.

S200, cutting all pictures into blocks with the same size according to a preset size, obtaining repeated blocks after cutting, removing the repeated blocks from all the blocks, and numbering the remaining blocks after removing the repeated blocks; specifically, all pictures are cut into blocks of the same size, for example, the pictures are cut in a manner of 16 × 16 in the horizontal and vertical directions, and of these blocks, there are usually a very large number of the same blocks, all the blocks are counted, and the number of the blocks is defined without counting repeated blocks (K0, K1, K2,... Km). When the user interface is cut and designed, the blocks with repeated numbers are preferentially used, so that the total number of the block numbers is smaller, and the cache used for subsequent storage is also smaller.

S300, sequentially storing the block data into an RAM (random access memory) in the FPGA for caching according to the block numbers, and sequentially storing the data of K0-Km blocks from 0 to the cache addresses.

S400, counting the corresponding relation between the picture numbers and the block numbers, setting a corresponding counting table for each picture number, wherein each table entry number of the counting table corresponds to the picture number, and each table entry comprises the block number and the combination mode of the picture with the corresponding number.

In this embodiment, the entries of the statistical table may be numbered as L0, L1, L2,.. and Ln; the table entries L0-Ln correspond to the picture IDs 0-IDn respectively, each table entry needs a combination mode of block numbers corresponding to the ID besides the block numbers, and the block numbers are arranged from left to right and from top to bottom; for example, suppose the picture number is IDx, the corresponding table entry Lx includes the block numbers K0, K1, K8, and K9, and the combination is defined as 0x22, i.e. two lines, 2 blocks each, and these information constitute the picture information of IDx.

S500, storing the corresponding relation statistical table of the picture numbers and the block numbers into an RAM (random access memory) in the FPGA for caching.

S600, updating the picture queue to be displayed in real time according to the actual interaction and the display requirement of the user interface. In this embodiment, the queue needs to include a coordinate position of the picture display in addition to the statistical entry Lx of the correspondence between the picture number and the block number.

And S700, displaying an interface required by a user according to the picture queue required to be displayed. Specifically, according to the picture queue, corresponding table entry number Lx information is read at a corresponding coordinate position, then block data corresponding to respective block numbers are read, and finally, pictures are displayed according to respective display modes. In some preferred embodiments, the entries L0-Ln may further include display modes (which may be represented by 2-3 bits) of picture or block numbers according to actual needs, such as white characters under black, black characters under white, transparent background, and semi-transparent.

According to the user interface display method of the FPGA platform, external storage such as DDR (double data rate) is not needed, the bandwidth and the power consumption are saved, and few RAM resources inside the FPGA are used. Particularly, aiming at the scheme with more reusable blocks in the picture, for example, setting an interactive interface with more character information such as a menu and the like, the reusability of the Chinese character information is very high. For image display, the method can basically cover all the row points of the displayable pictures of each row without the limitation of the number of the pictures of the user interface. Aiming at the dilemma that the current domestic FPGA platform is limited by the shortage of the type and the model of the current domestic DDR and other cache devices, the domestic FPGA platform is developed, the storage bandwidth is not used, is less used or is reduced, and the development of projects is greatly facilitated.

It should be understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not intended to be limited to the specific order or hierarchy presented.

In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, invention lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. Of course, the processor and the storage medium may reside as discrete components in a user terminal.

For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in memory units and executed by processors. The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.

What has been described above includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the embodiments described herein are intended to embrace all such alterations, modifications and variations that fall within the scope of the appended claims. Furthermore, to the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim. Furthermore, any use of the term "or" in the specification of the claims is intended to mean a "non-exclusive or".

Claims

1. A user interface display method of an FPGA platform is characterized by comprising the following steps:

s100, numbering all pictures needing to be displayed on a user interface;

2. The method of claim 1, wherein all pictures are cut into blocks of the same size in 16 rows.

3. The method as claimed in claim 1, wherein when the user interface is cut and designed, the blocks with repeated numbers are preferentially used, so that the total number of the block numbers is smaller, and the cache used for subsequent storage is smaller.

4. The method of claim 1, wherein the combination of the blocks in the statistical table is as follows: the block numbers are arranged and combined from left to right and from top to bottom.

5. The method according to claim 1, wherein the picture queue comprises a statistical entry of correspondence between picture numbers and block numbers and a coordinate position of picture display.

6. The method for displaying the user interface of the FPGA platform according to claim 5, wherein the method for displaying the interface required by the user according to the picture queue required to be displayed comprises the following steps: and reading corresponding table entry number information at a corresponding coordinate position according to the picture queue, then reading block data corresponding to respective block numbers, and displaying pictures according to respective display modes.

7. The method according to claim 1, wherein the entry of the statistical table further includes a display mode including a picture or block number according to actual needs, specifically: font color in picture, background transparency.