CN113178484B - Thin-capacitance coupling thyristor and preparation method thereof - Google Patents
Thin-capacitance coupling thyristor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7436—Lateral thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66393—Lateral or planar thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
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Abstract
The invention relates to a thin capacitive coupling thyristor and a preparation method thereof, wherein the thin capacitive coupling thyristor comprises: a substrate; the substrate comprises an anode region, an n base region, a p base region and a cathode region which are sequentially connected; the P base region is a nano sheet stack part, the nano sheet stack part forms a plurality of conducting channels, and the nano sheet stack part comprises; a stack of nanoplates and a support structure between adjacent nanoplates, the support structure being formed of a first semiconductor and the nanoplates being formed of a second semiconductor; the width of the nano-sheet is larger than that of the supporting structure; and the surrounding grid surrounds the nano stack part. The Thin Capacitive Coupling Transistor (TCCT) exhibits obvious switching characteristics, the Fishbone FET design based on bulk silicon can be combined with the TCCT design method to design it into a capacitively coupled thyristor, which will significantly improve the switching characteristics and subthreshold swing of the device, and simultaneously can also improve the operating current of the device by utilizing the excellent current drive characteristics of Fishbone FET, and the connection of bulk silicon and the substrate is also beneficial to solving the heat dissipation problem of the device.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a thin capacitively coupled thyristor, a method for manufacturing the same, and a semiconductor device.
Background
The development of large-scale integrated circuits and chips has prompted the trend toward ever shrinking dimensions and ever optimizing electrical characteristics of transistors. And for high power integrated circuits, the electrostatic protection and breakdown resistance characteristics of the device are important. The thyristor formed by the parasitic bipolar transistors triggered by the two impact ionization has steep switching characteristics and larger current drive, the switching characteristics are applied to the integrated circuit, the subthreshold swing of the device is improved, and the single-gate control circuit can also effectively control the switching state of the device. Currently, thin capacitively coupled thyristors based on SOI substrates exhibit high speed, low power consumption characteristics in the study of DRAM and SRAM, which is also beneficial for the design of large scale integrated circuits.
Referring to fig. 1, the Thin Capacitively Coupled Thyristor (TCCT) in the comparison document 1(Hyun-Jin Cho Nemati,F.Roy,R.Gupta,R.Yang,K.Ershov,M.Banna,S.Tarabbia,M.Sailing.A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor(TCCT)[C]//IEEE Internationalelectron Devices Meeting.IEEE,2005) is directly connected above the p-base region by a thyristor and a gate capacitor, and the TCCT device structure combined with the gate auxiliary switch technology solves the problem of slow switching speed of the conventional thyristor, so that the TCCT device can operate at a very high speed. The thyristor of the TCCT device is a p-n-p-n device with three pn junctions J1, J2 and J3 connected in series. The doping concentrations of different regions in the device design are different, wherein the p-type anode region and the n-type cathode are heavily doped, and the doping concentration of the n-type base region is reduced, so that the high breakdown voltage is realized, the grid electrode is coupled with the p-type base region, and the switching state of the device is controlled.
And GAA STACKED nanosheet FET has received extensive attention from academia and industry. The continuously updated preparation flow and key process, and the optimized device structure are the popular research direction of the novel CMOS device.
GAA STACKED nanosheet FET a novel device having a gate-all-around structure and a horizontal Nanosheet (NS) as a conductive channel. The novel Fishbone FET can greatly increase the driving current by adding the supporting structure on the stacked nano-sheet device under the condition of not affecting the subthreshold characteristic of the device basically; the source drain stress can be maintained, and the mobility of the device is improved; complex inner side wall technology can be omitted, and the preparation complexity and the electric characteristic fluctuation of the device are reduced; meanwhile, the heat dissipation of the conducting channel can be increased through the connection with the substrate, so that the self-heating effect is improved; the threshold value of the device can be adjusted by adjusting the width and the height of the supporting structure, so that the filling requirements of the high-K dielectric layer and the metal grid electrode are reduced in the process, and the multi-threshold value adjustment and control can be realized.
The Thin Capacitive Coupling Transistor (TCCT) exhibits obvious switching characteristics, the Fishbone FET design based on bulk silicon can be combined with the TCCT design method to design it into a capacitively coupled thyristor, which will significantly improve the switching characteristics and subthreshold swing of the device, and simultaneously can also improve the operating current of the device by utilizing the excellent current drive characteristics of Fishbone FET, and the connection of bulk silicon and the substrate is also beneficial to solving the heat dissipation problem of the device.
Disclosure of Invention
Aiming at the technical problems, the invention provides a thin capacitive coupling thyristor, a preparation method thereof and a thin capacitive coupling thyristor, and the invention adopts the following technical scheme:
A thin capacitively coupled thyristor, characterized by: comprising the following steps:
A substrate;
the substrate comprises an anode region, an n base region, a p base region and a cathode region which are sequentially connected;
The P base region is a nano sheet stack part, the nano sheet stack part forms a plurality of conducting channels, and the nano sheet stack part comprises; a stack of nanoplates and a support structure between adjacent nanoplates, the support structure being formed of a first semiconductor and the nanoplates being formed of a second semiconductor; the width of the nano-sheet is larger than that of the supporting structure;
and the surrounding grid surrounds the nano stack part.
The invention also discloses a preparation method of the thin capacitance coupling thyristor, which is characterized in that: the method comprises the following steps:
Providing a substrate;
Epitaxially growing a superlattice laminate of a first semiconductor and a second semiconductor on a substrate;
Etching the superlattice laminate to form a plurality of fins;
Forming a dummy gate on the fin;
sequentially forming a cathode region, an n base region, an anode region and a p base region on the fin through mask etching and epitaxial growth;
Selectively removing superlattice laminates of a first semiconductor and a second semiconductor remained on the fins and under the pseudo gate to form nano stack parts of a plurality of conducting channels so as to form a P base region, wherein the nano stack parts comprise nano sheets formed by the second semiconductor and supporting structures formed by the first semiconductor, and the width of each nano sheet is larger than that of each supporting structure, so that the channel release of each nano sheet is realized;
A surrounding grid is formed around the nano stack part.
Compared with the prior art, the invention has the following beneficial technical effects:
the design of the novel Fishbone FET as a capacitive coupling thyristor type can obviously improve the subthreshold characteristic of the device; the working current of the device can be obviously improved by utilizing the design of combining the multilayer nano-sheets and the supporting structure; the capacitive coupling thyristor adopts the Si nano-plate as a conducting channel and SiGe as a supporting structure, which is beneficial to remarkably improving the carrier concentration of the channel; the grid structure with the partial ring grid structure can effectively control the working state of the capacitive coupling thyristor; the gate capacitance and the conductive channel characteristics of the device can be regulated by adjusting the width and the height of the nano-sheet and the supporting structure.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures.
Fig. 1 is a schematic diagram of a prior art thin capacitively coupled thyristor.
Fig. 2 is a schematic longitudinal cross-section of a superlattice grown on a substrate in accordance with the invention along a direction perpendicular to a fin line.
Fig. 3 is a schematic longitudinal cross-section of a superlattice laminate in accordance with the invention, with the first side wall formed on the superlattice laminate along a direction perpendicular to the fin line.
Fig. 4 is a schematic longitudinal cross-section of an etched superlattice laminate to form fins along a vertical fin line in accordance with the invention.
Fig. 5 is a schematic longitudinal cross-section of the present invention along the direction perpendicular to the fin line, where the first sidewall is removed and a shallow trench isolation is formed.
Fig. 6 is a top view of a dummy gate formed on a fin according to the present invention, wherein X is a center line of the fin along a fin line direction, and Y is a center line of the fin perpendicular to the fin line direction.
Fig. 7A, B is a schematic view of a vertical section along Y-line and X-line of the formation of dummy gates on fins according to the present invention.
FIG. 8A, B is a schematic view of a longitudinal cross-section of the second sidewall deposited along the Y-line and X-line according to the present invention.
Fig. 9-11 are schematic longitudinal cross-sectional views of the invention along Y-line and X-line of etching the second sidewall, etching the corresponding superlattice stack, epitaxially growing the cathode region.
Fig. 12-14 are schematic longitudinal cross-sectional views of the invention, in which the third sidewall is deposited, the third sidewall is etched, the corresponding superlattice stack is etched, and the epitaxially grown n-base region is grown along the Y-line and the X-line.
Fig. 15A, B is a schematic view of a longitudinal section along Y-line and X-line of the invention with the third sidewall removed and the fourth sidewall deposited.
Fig. 16 is a schematic view of a longitudinal cross section along X-ray of the invention etching the fourth and second side walls, etching the corresponding superlattice laminate, and epitaxially growing the anode region.
Fig. 17A, B is a schematic view of a longitudinal section of the fourth and second sidewalls along the Y-line and X-line, with the top portion of the dummy gate removed, and fig. 17C is a schematic view of a longitudinal section of the deposited isolation layer along the X-line. The nanochannel releases a longitudinal cross-section along the direction perpendicular to the fin line.
Fig. 18A, B is a schematic view of a vertical section along Y-line and X-line with dummy gate removed according to the present invention.
FIG. 19 is a schematic diagram of a nano-stack according to the present invention.
Fig. 20 is a schematic view of a longitudinal cross-section of the high K dielectric layer along the Y-line and X-line formed in accordance with the present invention.
Fig. 21 is a schematic view of a longitudinal cross section of a metal gate formed according to the present invention along the Y-line and X-line.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
In this embodiment, a method for fabricating a thin capacitively coupled thyristor device is provided. Fig. 2-21 are schematic views of a process for fabricating a thin capacitively coupled thyristor device 100 according to the present invention, the process for fabricating Bao Dianrong a coupled thyristor device 100 comprising:
As illustrated in fig. 2, a substrate 101, which may be bulk silicon, is provided.
The substrate 101 is a portion of a semiconductor wafer suitable for forming one or more IC devices, and when a bulk silicon substrate is employed, a highly doped P-well region is formed in the bulk silicon substrate 101 by implantation of P-type impurity ions, such as boron (B) ions, diffusion, and annealing to a desired well depth.
Silicon dioxide (SiO 2) is removed from the bulk silicon substrate surface and a stack of superlattice structures of the first semiconductor 201 '/the second semiconductor 202' is epitaxially grown on the bulk silicon substrate for a plurality of cycles. The SiGe thickness and the Si thickness are respectively regulated and controlled in the superlattice laminated epitaxial process. In one embodiment, the first semiconductor 201 '/second semiconductor 202' superlattice laminate is a SiGe/Si laminate.
As shown in fig. 3, a self-aligned sidewall transfer (SIT) process is used to form a nano-scale first sidewall 301 array, wherein the first sidewall 301 is silicon nitride (SiN X), and the specific forming process is as follows: a sacrificial layer 302 is covered on the superlattice laminate, the sacrificial layer 302 may be specifically polysilicon (PolySi, p-si) or amorphous silicon (a-si), a part of the sacrificial layer 302 is etched, a silicon nitride (SiN x) layer is deposited, and then anisotropic etching is adopted to etch the remaining sacrificial layer 302, so that the remaining sacrificial layer 302 is only remained on a plurality of periodic silicon nitride (SiN x) first side walls (spacers) 301 on the superlattice laminate, and the silicon nitride (SiN x) first side walls 301 play a role of a Hard Mask (Hard Mask) in lithography.
And manufacturing the epitaxially grown superlattice laminate into a plurality of fins which are distributed periodically through an etching process. And etching by taking the first side wall 301 as a mask to form the fin with the superlattice laminated structure. The upper part of the fin is a conductive channel region formed by superlattice lamination, and the lower part of the fin is a substrate, so that the fin shown in fig. 4 is formed. The etching process is either a dry etch or a wet etch, and in one embodiment Reactive Ion Etching (RIE) may be employed. The fins will be used to form one or more n-type field effect transistors and/or horizontal nanoplates of p-type field effect transistors. Although one fin is shown in fig. 4, it should be understood that any suitable number and configuration of fins may be used. The fin has a height of 100nm to 400nm and a width of about 20 nm to 200nm. The direction is defined herein, the X direction is the fin line direction, and the Y direction is the method of perpendicular fin line.
As shown in fig. 5, a shallow trench isolation (shallow trench isolation, STI) region 103 is disposed between two adjacent fins, and a dielectric insulating material is deposited adjacent to the fins to form the shallow trench isolation region 103. The shallow trench isolation region 103 may be formed of a suitable dielectric material, such as silicon dioxide (SiO 2), silicon nitride (SiN x), or the like. The function of the shallow trench isolation regions 103 is to isolate transistors on adjacent fins. The shallow trench isolation 103 region exposes the first semiconductor layer 201' of the lowermost layer of the superlattice stack.
Two broken lines X, Y are provided in fig. 6, the X-line is along the fin line direction and the center line of the fin, the Y-line is perpendicular to the fin line direction and the center line of the fin, the subsequent figures are schematic cross-sectional views of X, Y, wherein the X-direction is the fin line direction and the Y-direction is the direction perpendicular to the fin line. As shown in fig. 7A, B, which is a cross-sectional view along the Y-direction and a cross-sectional view along the X-direction, a dummy gate 106 is formed on the exposed fin in a direction perpendicular to the fin line (i.e., the Y-direction), and the dummy gate 106 may be formed by thermal oxidation, chemical vapor deposition, sputtering (sputtering), or the like. The dummy gate 106 spans the superlattice stack above the fins and a plurality of dummy gates 106 may be periodically distributed along the fin-line direction (i.e., the X-direction). For a single device, the dummy gate 106 is located at a position offset from the center of the fin in the X-direction, which is set for subsequent placement of the gate of the TCCT device. The material used for the dummy gate 106 may be polysilicon (PolySi, p-si) or amorphous silicon (a-si).
As shown in fig. 7, a second sidewall 107 of silicon nitride (SiN x) is deposited over the entire device upper surface, the second sidewall 107 being disposed on top of the dummy gate 106 and on top of the superlattice stack not covered by the dummy gate 106.
A portion of the silicon nitride (SiN x) second sidewall 107 is etched away, and a portion of the second sidewall 107 on the smaller side of the dummy gate 106 at the top of the superlattice is etched away in the X direction, forming a second sidewall 107a as described in fig. 9B.
The superlattice laminate is etched using the second sidewall 107a as a mask, and a cathode etch is performed to the substrate 101, see fig. 10.
Referring to fig. 11, a cathode region 108a is epitaxially grown in the space cleaned by the cathode etching. In one embodiment, where N-type doping is used in the bulk silicon substrate 101, the cathode region 108a is heavily doped with phosphorus (P) using epitaxially grown silicon (Si).
Next, a layer of silicon nitride (SiN x) is deposited on the upper surface of the whole device to form a third sidewall 107b, and then a part of the second sidewall 107a and the third sidewall 107b on the other side of the dummy gate 106 in the X direction and in the larger part are etched away to form the sidewall as shown in fig. 12. The superlattice laminate is etched using the sidewall of fig. 12 as a mask, and n-base etching is performed to etch to the substrate 101, see fig. 13.
Referring to fig. 14, n-base region 108b is epitaxially grown in the cathode etched clean space. In one embodiment, where N-type doping is used in the bulk silicon substrate 101, the N-base region 108b is epitaxially grown silicon (Si), lightly doped with phosphorus (P).
The third sidewall 107b is removed and then a fourth sidewall 107c is deposited on top of the device, see fig. 15.
The superlattice laminate is etched using the second sidewall 107a and the fourth sidewall 107c as masks, and then anodized to the substrate 101, see fig. 16A, B.
Referring to fig. 16C, anode region 108C is epitaxially grown in the space cleared by the anodic etching. In one embodiment, where the bulk silicon substrate 101 is P-doped, the anode region 108c is heavily doped with boron (B) using epitaxially grown silicon (Si).
Referring to fig. 17B, portions of the second sidewall 107a and the fourth sidewall 107c on the dummy gate 106 are etched away, and an isolation layer 109 is deposited on both sides of the second sidewall 107a and the fourth sidewall 107c in the X direction, preventing the gate 105 from being shorted to the anode region 108c and the cathode region 108a in the subsequent step, and performing chemical mechanical polishing on the isolation layer 109 to planarize it.
As shown in fig. 18A, B, the dummy gate etch 106 formed of the aforementioned polysilicon (PolySi, p-si) or amorphous silicon (a-si) is etched away, i.e., the dummy gate 106 is removed, by an etching process.
As shown in fig. 19, the sacrificial layer in the superlattice laminate is selectively etched to perform nano-plate (nanosheet) channel release. The exposed portion of the conductive channel region of the fin is processed to remove most of each first semiconductor layer 201', wherein the first semiconductor layer 201' is a sacrificial layer, and the remaining first semiconductor layers 201' form a supporting structure 201 to connect adjacent nano-sheets 202 formed of a second semiconductor. The nanosheets 202 have a width W NS to 50nm, a thickness T NS of 3 to 20nm, a height H SC of the support structure 201 of 5 to 30nm, and a width W SC of 3 to 40nm. The bottom-most support structure 201 is connected to the substrate 101.
In one embodiment, the sacrificial layer is a SiGe layer, a selective majority of the SiGe layer is selectively removed, the Si layer remains, the remaining SiGe layer is a support structure for adjacent Si layers, and is located at an intermediate position between adjacent Si layers, forming a device in which the Si horizontal stack + SiGe support structure is a periodic stack, the support structure SiGe has a width W SC that is less than the width W NS of the nanoplatelets Si, and is a fishbone device when viewed in the X direction. An etchant that selectively etches SiGe at a faster rate relative to Si may be used in the selective removal process. In one embodiment, a conventional wet process isotropically etching the sacrificial layer effects nanochannel release, thereby forming a conducting channel in which the nanoplatelets and support structure are combined.
In one embodiment, the nanochannel release is achieved using an Atomic Layer Etching (ALE) process for precise control of the width of the support structure.
As shown in fig. 19, a portion of the support structure 201 formed by the first semiconductor layer and the nanolayer formed by the second semiconductor layer 202 are selectively removed to form a nanostack 102.
Next, as shown in fig. 20, a high-K dielectric layer 104 is deposited such that the high-K dielectric layer 104 surrounds the surface of the nano-stack 102 and covers the isolation layer and the silicon nitride (SiN x) sidewall surface 107. The high-K dielectric layer may have a dielectric constant above about 7.0, and HfO 2 or Al 2O3 may be used.
Next, as shown in fig. 21, a metal gate 105 is deposited outside the space cleaned by the dummy gate 106 and the high K dielectric layer 104, and chemical mechanical polishing is performed on the metal gate 105 to planarize the metal gate. The metal gate 105 may have a multi-layered structure, and the metal gate 105 may employ metal aluminum (Al) or tungsten (W). The metal-containing gate is formed by chemical vapor deposition, physical vapor deposition, and the like. As shown in fig. 21, the metal gate 105 fills the space after the dummy gate 106 is cleaned.
In one embodiment, the high-K dielectric layer 104 and the metal gate 105 are deposited layer by layer using an Atomic Layer Deposition (ALD) process, including an interfacial oxide layer (IL), a gate dielectric HfO 2, a barrier layer TiN/TaN, and a gate metal (NMOS TiaAlC; PMOS TiN), forming a vertical stack of horizontal multi-layered nano-sheets 202 and support structures 201.
The above process flow is to prepare a complete thin capacitively coupled thyristor device, and a thin capacitively coupled thyristor device as shown in fig. 21 is formed. It follows that the presence of the support structure simplifies the process of filling the high K dielectric and gate metal between the nanoplates and that the formation of bottom parasitic channels can be suppressed by the support structure portion.
In one embodiment, the thin capacitively coupled thyristor may use silicon-on-insulator (SOI) as a substrate, and the superlattice stack is directly epitaxially grown on the insulating layer SiO 2, and the rest of the process flows are the same as the process flows of the thin capacitively coupled thyristor using bulk silicon as a substrate, which is not described herein. Replacement of the substrate 101 with an SOI substrate can effectively suppress the substrate leakage current of the device.
To this end, there is provided a thin capacitively coupled thyristor device structure, as shown in connection with fig. 21 and 19, the thin capacitively coupled thyristor device 100 comprising: the semiconductor device comprises a substrate 101, wherein the substrate 101 comprises an anode region 108c, an n-base region 108b, a p-base region and a cathode region 108a which are sequentially connected. The substrate 101 is bulk silicon or silicon-on-insulator, the anode region 108c and the cathode region 108a are heavily doped, and the n-base region 108b is lightly doped.
The P base region is a nano-sheet stack portion 102, the nano-sheet stack portion 102 forms a plurality of conductive channels, and the nano-sheet stack portion includes; a stack of nanoplates 202 and a support structure 201 between adjacent nanoplates 202, the support structure 201 being formed of a first semiconductor and the nanoplates 202 being formed of a second semiconductor; the width of the nanoplatelets 202 is greater than the width of the support structure 201; in one embodiment, the first semiconductor is SiGe and the second semiconductor is Si, and the stacked device with the Si horizontal stack and the SiGe support structure being periodic is formed to have a fishbone shape as viewed along the fin line direction.
The nanosheets 202 have a width W NS to 50nm, a thickness T NS of 3 to 20nm, a height H SC of the support structure 201 of 5 to 30nm, and a width W SC of 3 to 40nm. The bottom-most support structure 201 is connected to the substrate 101.
A surrounding gate surrounding the nano-stack 102; the surrounding gate comprises, from inside to outside, a high-K dielectric layer 104 and a metal gate 105. A high K dielectric layer surrounding the surface of the nano-stack 102 may have a dielectric constant above about 7.0, and may be HfO 2 or Al 2O3.
The metal gate 105 is located outside the high-K dielectric layer 204, the metal gate 105 may have a multi-layer structure, and the metal gate 105 may be made of aluminum (Al) or tungsten (W).
The technical scheme provided by the embodiment of the application at least has the following technical effects or advantages:
the design of the novel Fishbone FET as a capacitive coupling thyristor type can obviously improve the subthreshold characteristic of the device; the working current of the device can be obviously improved by utilizing the design of combining the multilayer nano-sheets and the supporting structure; the capacitive coupling thyristor adopts the Si nano-plate as a conducting channel and SiGe as a supporting structure, which is beneficial to remarkably improving the carrier concentration of the channel; the grid structure with the partial ring grid structure can effectively control the working state of the capacitive coupling thyristor; the gate capacitance and the conductive channel characteristics of the device can be regulated by adjusting the width and the height of the nano-sheet and the supporting structure.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present invention are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.
Claims (21)
1. A thin capacitively coupled thyristor, characterized by: comprising the following steps:
A substrate;
the substrate comprises an anode region, an n base region, a p base region and a cathode region which are sequentially connected;
The P base region is a nano sheet stack part, the nano sheet stack part forms a plurality of conductive channels and is in a fishbone shape, and the nano sheet stack part comprises; a stack of nanoplates and a support structure between adjacent nanoplates, the support structure being formed of a first semiconductor and the nanoplates being formed of a second semiconductor; the width of the nano-sheet is larger than that of the supporting structure;
A surrounding grid surrounding the nano stack part;
the first semiconductor is SiGe and the second semiconductor is Si.
2. The thin capacitively coupled thyristor of claim 1, wherein: the grid electrode sequentially comprises a high-K dielectric layer and a metal grid from inside to outside.
3. The thin capacitively coupled thyristor of claim 1, wherein: the width range of the nano sheet is 5-50 nm, and the thickness range is 3-20 nm.
4. The thin capacitively coupled thyristor of claim 1, wherein: the height range of the supporting structure is 5-30 nm, and the width range is 3-40 nm.
5. The thin capacitively coupled thyristor of claim 1, wherein: the substrate is bulk silicon or silicon-on-insulator.
6. The thin capacitively coupled thyristor of claim 1, wherein: the length of the conductive channel ranges from 10 nm to 100nm.
7. The thin capacitively coupled thyristor of claim 2, wherein: the high-k dielectric layer is HfO 2 or Al 2O3.
8. The thin capacitively coupled thyristor of claim 2, wherein: the metal gate is tungsten (W) or cobalt (Co).
9. The thin capacitively coupled thyristor of claim 1, wherein: the anode region and the cathode region are heavily doped, and the n base region is lightly doped.
10. A preparation method of a thin capacitively coupled thyristor is characterized by comprising the following steps: the method comprises the following steps:
Providing a substrate;
Epitaxially growing a superlattice laminate of a first semiconductor and a second semiconductor on a substrate;
Etching the superlattice laminate to form a plurality of fins;
Forming a dummy gate on the fin;
sequentially forming a cathode region, an n base region, an anode region and a p base region on the fin through mask etching and epitaxial growth;
Selectively removing superlattice laminates of a first semiconductor and a second semiconductor remained on the fins and under the pseudo gate to form nano stack parts of a plurality of conducting channels so as to form a P base region, wherein the nano stack parts comprise nano sheets formed by the second semiconductor and supporting structures formed by the first semiconductor, and the width of each nano sheet is larger than that of each supporting structure, so that the channel release of each nano sheet is realized;
A surrounding grid is formed around the nano stack part.
11. The method according to claim 10, wherein: the step of forming the plurality of fins is specifically: a first side wall is arranged on the superlattice lamination; and etching the superlattice laminate by taking the first side wall as a mask to form a plurality of fins.
12. The method according to claim 11, wherein: the method also comprises the step of forming a shallow trench isolation region, and specifically comprises the following steps: shallow trench isolation regions are created between adjacent fins such that a plurality of conductive channels are located over the shallow trench isolation regions.
13. The method according to claim 12, wherein: the cathode region is specifically formed by: and depositing a second side wall on the upper surfaces of the pseudo gate and the superlattice laminate, etching the second side wall on one side of the pseudo gate, etching the corresponding superlattice laminate part, forming a cathode space, epitaxially growing silicon in the cathode space, and carrying out first type heavy doping to form a cathode region.
14. The method according to claim 13, wherein: the formation of the n base region is specifically: and depositing a third side wall on the upper surfaces of the pseudo gate and the superlattice laminate, etching the second side wall and the third side wall which are on the other side of the pseudo gate and are close to the pseudo gate, further etching the corresponding superlattice laminate part to form an n base region space, epitaxially growing silicon in the n base region space and carrying out first type light doping to form an n base region.
15. The method according to claim 14, wherein: the anode region is specifically formed by: removing the residual third side wall, depositing a fourth side wall on the upper surfaces of the dummy gate and the superlattice laminate, etching the second side wall and the fourth side wall which are at the other side of the dummy gate and are far away from the dummy gate, further etching the corresponding superlattice laminate part to form an anode region space, epitaxially growing silicon in the anode region space and carrying out heavy doping opposite to the first type to form an n base region.
16. The method according to claim 15, wherein: the step of forming the surrounding grid electrode specifically comprises the following steps: and etching to clean the pseudo gate, and after the release of the nano sheet channel is realized, depositing the gate at the original pseudo gate position.
17. The method according to claim 10, wherein: the first semiconductor is SiGe and the second semiconductor is Si.
18. The method according to claim 10, wherein: the surrounding grid electrode sequentially comprises a high-K dielectric layer and a metal grid from inside to outside.
19. The method according to claim 10, wherein: the width range of the nano sheet is 5-50 nm, and the thickness range is 3-20 nm.
20. The method according to claim 10, wherein: the height range of the supporting structure is 5-30 nm, and the width range is 3-40 nm.
21. A semiconductor device, characterized in that: the semiconductor device comprising the thin capacitively coupled thyristor of any of claims 1 to 9.
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| EP3203517A1 (en) * | 2016-02-08 | 2017-08-09 | Kilopass Technology, Inc. | Methods and systems for reducing electrical disturb effects between thyristor memory cells using heterostructured cathodes |
| CN111384156A (en) * | 2020-01-21 | 2020-07-07 | 中国科学院微电子研究所 | C-channel semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
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