CN113178476A - Fin field effect transistor and method for forming blunt fin by gas cluster ion beam - Google Patents

Fin field effect transistor and method for forming blunt fin by gas cluster ion beam Download PDF

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CN113178476A
CN113178476A CN202110366705.5A CN202110366705A CN113178476A CN 113178476 A CN113178476 A CN 113178476A CN 202110366705 A CN202110366705 A CN 202110366705A CN 113178476 A CN113178476 A CN 113178476A
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fins
subset
fin
semiconductor
dielectric
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曹路
宋凤麒
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Jiangsu Jichuang Atomic Cluster Technology Research Institute Co ltd
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Jiangsu Jichuang Atomic Cluster Technology Research Institute Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

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  • General Physics & Mathematics (AREA)
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Abstract

A fin field effect transistor, comprising: a semiconductor substrate; an insulator layer disposed on the semiconductor substrate; a plurality of fins disposed on the insulator layer; wherein a first subset of the plurality of fins is comprised of a semiconductor material, and wherein a second subset of the plurality of fins is comprised of a dielectric material; wherein the second subset of the plurality of fins is comprised of silicon nitride and is interleaved with the first subset of the plurality of fins; and wherein a set of fins from the first subset of the plurality of fins is merged with the epitaxially grown silicon, and wherein at least one set of fins from the first subset of the plurality of fins is merged with the n-doped epitaxially grown silicon, and wherein at least another set of fins from the first subset of the plurality of fins is merged with the p-type doped epitaxially grown silicon.

Description

Fin field effect transistor and method for forming blunt fin by gas cluster ion beam
Technical Field
The present invention relates generally to semiconductor fabrication, and more particularly to fin field effect transistor (finFET) structures and fabrication methods.
Background
With the continuing trend toward miniaturization of Integrated Circuits (ICs), transistors of increasingly smaller sizes are required. As device dimensions continue to shrink, FinFET technology becomes more prevalent. Accordingly, it is desirable to have improved finFET devices and fabrication methods.
One practical problem in finFET fabrication is that some finfets may contain multiple (subsets) of fins that require epitaxial merging of groups of fins, while other finfets may utilize un-merged fins. Some devices (e.g., SRAM) may require finfets with both merged and non-merged fins.
In prior art methods, some fins are removed to facilitate merged and un-merged fins (subsets). There are various problems with this approach. Removing dummy fins can result in variations in fin density, which can cause the dummy gate polysilicon to no longer plasticize, thereby presenting a significant challenge in subsequent replacement metal gate processes (RMGs).
Disclosure of Invention
The present invention is directed to an improved finFET device, a finFET, and a method of forming blunt fins using a gas cluster ion beam.
The technical scheme of the invention is that the semiconductor structure (fin field effect transistor) comprises: a semiconductor substrate; an insulator layer disposed on the semiconductor substrate; a plurality of fins disposed on the insulator layer;
wherein a first subset of the plurality of fins is comprised of a semiconductor material, and wherein a second subset of the plurality of fins is comprised of a dielectric material; wherein the second subset of the plurality of fins is comprised of silicon nitride and is interleaved with the first subset of the plurality of fins; and
wherein a set of fins from the first subset of the plurality of fins is merged with the epitaxially grown silicon, and wherein at least one set of fins from the first subset of the plurality of fins is merged with the n-doped epitaxially grown silicon, and wherein at least another set of fins from the first subset of the plurality of fins is merged with the p-type doped epitaxially grown silicon.
Another semiconductor structure, comprising: a semiconductor substrate; forming a plurality of fins on a semiconductor substrate; wherein a first subset of the plurality of fins is comprised of a semiconductor material, and wherein a second subset of the plurality of fins is comprised of a dielectric material; wherein the second subset of the plurality of fins is comprised of silicon nitride and is interleaved with the first subset of the plurality of fins; and wherein a set of fins from the first subset of the plurality of fins is merged with the epitaxially grown semiconductor material, and wherein at least one set of fins from the first subset of the plurality of fins is merged with the n-doped epitaxially grown semiconductor material, and wherein at least another set of fins from the first subset of the plurality of fins is merged with the p-type doped epitaxially grown semiconductor material.
In another embodiment, a semiconductor structure is provided. The structure includes a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, wherein a first subset of the plurality of fins is comprised of a semiconductor material, and wherein a second subset of the plurality of fins is comprised of a dielectric material.
In another embodiment, a method for converting a subset of a plurality of semiconductor fins on a semiconductor structure into dielectric fins is provided. The method comprises the following steps: masking a first subset of the plurality of fins; reserving a second subset of the plurality of fins as unmasked fins; and applying a gas cluster ion beam to the unmasked fins to convert the unmasked fins into dielectric fins.
In another embodiment, a method for converting a subset of a plurality of semiconductor fins on a semiconductor structure into dielectric fins is provided. The method comprises the following steps: masking a first subset of the plurality of fins; leaving a second subset of the plurality of fins as unmasked fins; and applying ion implantation to the unmasked fins to convert the unmasked fins into dielectric fins.
Has the advantages that: the present invention can remove some fins to promote merged and un-merged fins (subsets). Removing the dummy fins increases the space between the un-merged fins, preventing undesired fin merging. Thus, the circuit density of the present invention is increased, thereby reducing the size of an SRAM or other integrated circuit.
Drawings
The structure, operation and advantages of the present invention will become more apparent upon consideration of the following description taken in conjunction with the accompanying drawings. The drawings are intended to be illustrative, not restrictive.
For clarity of illustration, certain elements in some of the figures may be omitted or not shown to scale. The cross-sectional view may be in the form of a "slice" or "near-sighted" cross-section, with certain background lines omitted for clarity of illustration, which would otherwise be visible in a "true" cross-sectional view.
In general, like elements may be represented by like numbers in the various figures, in which case, in general, the last two significant digits may be the same, with the most significant digit being the figure number. Moreover, some reference numerals may be omitted in some drawings for clarity.
Fig. 1 illustrates an SOI semiconductor structure at the beginning for an embodiment of the present invention.
Fig. 2 shows the SOI semiconductor structure after a subsequent processing step of applying a mask over a subset of the fins.
Fig. 3 shows the SOI semiconductor structure after a subsequent processing step in which a gas cluster ion beam is applied to the structure.
Fig. 4 shows an alternative embodiment in which gas cluster ion beam angles are applied to the structure.
Fig. 5 shows details of an alternative embodiment of the present invention with partially converted fin structures.
Fig. 6 shows the SOI semiconductor structure after subsequent processing steps to remove the mask.
Fig. 7 shows the SOI semiconductor structure after subsequent processing steps of fin merging.
Figure 8 shows the bulk semiconductor structure at the beginning for an embodiment of the present invention.
Fig. 9 shows the bulk semiconductor structure after a subsequent processing step of applying a mask over a subset of the fins.
Fig. 10 illustrates the bulk semiconductor structure after a subsequent processing step of applying a gas cluster ion beam to the structure.
Figure 11 shows the bulk semiconductor structure after a subsequent processing step to remove the mask.
Fig. 12 shows the bulk semiconductor structure after subsequent processing steps of fin merging.
Detailed Description
One practical problem in finFET fabrication is that some finfets may contain multiple (subsets) of fins that require epitaxial merging of groups of fins, while other finfets may utilize un-merged fins. Some devices (e.g., SRAM) may require finfets with both merged and non-merged fins.
Furthermore, removing the dummy fins increases the space between the un-merged fins, but due to lateral growth and epitaxial morphology, removing a single dummy fin does not provide enough margin to completely prevent undesired fin merging. Therefore, it is often necessary to remove multiple dummy fins, thereby reducing circuit density, which increases the size of the SRAM or other integrated circuit.
Embodiments of the present invention overcome the above-described shortcomings by converting semiconductor (silicon) fins into insulating dielectric fins using a gas cluster ion beam process.
Fig. 1 illustrates a starting point for a semiconductor-on-insulator (SOI) semiconductor structure 100 for use in an embodiment of the present invention. The semiconductor structure 100 includes a semiconductor substrate 102. The semiconductor substrate 102 forms the basis of the semiconductor structure 100. The semiconductor substrate 102 may be made of any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloy, silicon-carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium phosphide, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials. An insulator layer 104 is disposed on the semiconductor substrate 102. The insulator layer 104 may include a Buried Oxide (BOX) layer. A thin semiconductor layer is disposed on top of the insulator layer 104. The thin semiconductor layer may be comprised of silicon. In alternative embodiments, a semiconductor layer may be formed on top of the insulator layer 104 using silicon germanium, a III-V compound semiconductor, a II-V semiconductor, or a combination of these materials. A plurality of semiconductor fins 106 are formed on the insulator layer 104.
Fig. 2 shows the SOI semiconductor structure 200 after subsequent processing steps of applying a mask 208 over a subset of the mask. As previously mentioned, like elements may be represented by like numbers in the various figures of the drawing, in which case generally the last two significant figures may be the same. For example, the semiconductor substrate 202 of fig. 1 may include: fig. 2 is similar to the semiconductor substrate 102 of fig. 1. An area of mask 208 is deposited over a select fin (generally designated 206B) that will remain as a semiconductor fin. The unmasked (exposed) fins (fins not covered by the area of the mask 208) are generally designated 206A. The exposed fins will be converted into dielectric fins in a subsequent process step. In some embodiments, the material used for the mask 208 comprises photoresist. In other embodiments, the material used for mask 208 is a hard mask, such as silicon oxide. The mask region may be formed using industry standard patterning techniques on the desired fin to be maintained as a semiconductor fin.
Fig. 3 shows the SOI semiconductor 300 structure after subsequent processing steps in which a gas cluster ion beam (indicated by the arrow labeled "G") is applied to the structure. In Gas Cluster Ion Beam (GCIB) processing, the surface is bombarded with a beam of high energy gas phase atom clusters. When the high pressure gas (e.g., 10 atmospheres) is ultrasonically expanded to a vacuum (e.g., 1x 10)-5Torr), cooling and then condensing into weakly ionized clusters. The ionized clusters are accelerated to very high velocities by electrostatic interaction and focused into a tight beam that impinges on the substrate surface. In contrast to more dispersive ion implantation processes, the atoms of the cluster ions collide and interact with the substrate atoms almost simultaneously. In one embodiment, the GCIB species is nitrogen with an energy ranging from about 1KeV to about 100KeV and a dose ranging from about 5E13 atoms per cubic centimeter to about 2E15 atoms per cubic centimeter. The gas cluster ion beam is applied by a GCIB tool. When the beam G strikes the exposed fin (shown generally as 306A), the silicon fin will convert to a silicon nitride fin. Thus, the semiconductor fin is converted into a dielectric fin. In other embodiments, oxygen may be used instead of nitrogen, in which case the exposed silicon fin is converted to a silicon oxide fin. In another embodiment, both oxygen and nitrogen may be used simultaneously, in which case the exposed silicon fin is converted to a silicon oxynitride fin. In another embodiment, the semiconductor fins comprise silicon germanium and a nitrogen species may be used, in which case the exposed silicon germanium fins are converted to silicon nitride germanium fins. The converted dielectric fins will be an obstacle to the upcoming fin merging process. Further embodiments of the present invention may utilize ion implantation in place of GCIB. That is to say that the first and second electrodes,some embodiments may include applying ion implantation to the unmasked fins to convert the unmasked fins into dielectric fins, such as silicon nitride fins.
Fig. 4 illustrates a semiconductor structure 400 in which a gas cluster ion beam angle is applied to the structure, in accordance with an alternative embodiment of the present invention. In this embodiment, the beam G is applied at an angle a to the vertical. The beam G can be applied at various intermediate angles from 0 (vertical) to a. In some embodiments, a ranges from about 10 degrees vertical to about 20 degrees vertical. Applying the gas cluster ion beam G at an angle can cause the entire fin to be converted to a dielectric at a lower energy setting than in the vertical (straight) case (see fig. 3). This embodiment may be used to keep the energy low in case it is desired to avoid structural damage due to too high energy of the gas cluster ion beam.
Fig. 5 shows details of an alternative embodiment of the present invention with partially converted fin structures. Fin 506A is comprised of an outer portion 514, the outer portion 514 being comprised of a converted dielectric such as an oxide or nitride, and the outer portion surrounding a central portion 516 comprised of silicon. This embodiment utilizes a lower energy GCIB setting so that the entire fin does not convert to a dielectric. The GCIB beam may be applied at various angles (see fig. 4) such that the outer portion 514 is converted to dielectric, but the energy is set such that the GCIB beam does not convert the central portion 516 to dielectric, and therefore, it remains as silicon. However, in the case where the exterior 514 is converted to a dielectric, the fin 506A may still serve the purpose of a dielectric fin.
Fig. 6 shows the SOI semiconductor 600 structure (compare 308 of fig. 3) after subsequent processing steps to remove the mask. The mask may be removed using a selective process that removes only the mask material without significantly affecting the silicon fin 606B, the dielectric fin 606A, or the insulator layer 604. The dielectric fins 606A may be interleaved with the silicon fins 606B such that a single dielectric fin is disposed between two silicon fins and one or more silicon fins are disposed between each dielectric fin.
Fig. 7 shows SOI semiconductor structure 700 after subsequent processing steps for fin merging. In embodiments, the fins are combined with epitaxially grown silicon, silicon germanium, carbon doped silicon or any suitable combination of those materials. Epitaxially grown silicon may be doped with various dopants in-situ, depending on whether a particular semiconductor fin is to be part of an NFET or a PFET. Note that with respect to fig. 2, in fig. 7, each fin is labeled with a reference numeral for the purpose of explaining the semiconductor structure. Fins 706A, 706B, 706D, 706F, 706H, and 706J are semiconductor fins, shown as white. Fins 706C, 706E, and 706G are dielectric fins, shown shaded.
Epitaxial region 718 merges fins 706A and 706B. The dielectric fin 706C serves as an isolation region that prevents the epitaxial region 718 from affecting the semiconductor fins 706D, 706F, 706H, and 706J on the right side of the dielectric fin 706C. In some embodiments, fins 706A and 706B comprise NFET transistors, and epitaxial region 718 may be in-situ doped with arsenic or phosphorous.
Epitaxial region 722 is defined by dielectric fin 706C and dielectric fin 706E. In some embodiments, the semiconductor fin 706D may comprise a PFET transistor and the epitaxial region 722 may be in-situ doped with boron and in direct physical contact with the semiconductor fin 706D. The semiconductor fin 706D may be part of a single-fin finFET. Such finfets have been used in various applications, such as pull-up gates used in SRAMs. It is therefore advantageous to be able to place a single semiconductor fin (706D) between two dielectric fins (706C and 706E) to support these applications.
Epitaxial region 724 is defined by dielectric fin 706E and dielectric fin 706G. The epitaxial region 724 is in direct physical contact with the semiconductor fin 706F. The semiconductor fin 706F may be part of an additional single-fin finFET. In some embodiments, the semiconductor fin 706F may be part of a single-fin PFET, and the epitaxial region 724 may be doped with boron in a similar manner as the epitaxial region 722.
Epitaxial region 720 merges fins 706H and 706J. The dielectric fin 706G serves as an isolation region that prevents the epitaxial region 720 from affecting the semiconductor fins 706A, 706B, 706D, and 706F located to the left of the dielectric fin 706G. In some embodiments, fins 706H and 706J comprise NFET transistors, and epi region 720 may be in-situ doped with arsenic or phosphorous in a manner similar to epi region 718. From this point, the finFET can be completed using industry standard process flows.
Fig. 8 illustrates a bulk semiconductor structure 800 at the beginning for an embodiment of the invention. The semiconductor structure 800 includes a bulk silicon substrate 802, which may be in the form of a wafer or die or a portion thereof. A plurality of fins, generally indicated at 806, are formed on the silicon substrate 802. The fins 806 may be formed using industry standard patterning techniques. Unlike the SOI structure 100 (see fig. 1), there is no blanket insulating layer between the fin 806 and the silicon substrate 802 (compare to 104 of fig. 1).
Fig. 9 shows the bulk semiconductor structure 900 after a subsequent processing step of applying a mask 908 on the subset of fins. Regions of mask 908 are deposited on select fins (generally designated 906B) that will remain as semiconductor fins. The exposed fins not covered by the area of mask 908 are generally designated 906A. In some embodiments, the material for mask 908 comprises photoresist. In other embodiments, the material for mask 908 is an oxide, such as silicon oxide. Industry standard patterning techniques may be used to form a mask region over the desired fin to be maintained as a semiconductor fin.
Fig. 10 shows a bulk semiconductor structure 1000 after subsequent processing steps in which a gas cluster ion beam (indicated by the arrow labeled "G") is applied to the structure. Similar to that described for the SOI case of fig. 1. As shown in fig. 3, a gas cluster ion beam process is used to convert the exposed fins from silicon into a dielectric material, such as silicon oxide or silicon nitride. Some embodiments using bulk semiconductor structures may also utilize angled GCIB applications, as shown in fig. 1. 4. Without the blanket insulator (e.g., 104 of fig. 1), a portion of the silicon substrate 1002 is also converted to a dielectric material, resulting in a dielectric (e.g., silicon nitride, silicon oxide, silicon oxynitride, or silicon germanium nitride).
FIG. 11 shows the bulk semiconductor structure 1100 (compared to the region of mask 1008 of FIG. 10) after a subsequent processing step to remove the mask. As shown in fig. 1. Referring to fig. 11, the dielectric fins (generally designated 1106) each include a fin portion 1109A and a horizontal portion 1109B located below fin portion 1109A and adjacent to fin portion 1109A. In some embodiments, horizontal portion 1109B has a thickness T in the range of about 3 nanometers to about 100 nanometers.
Fig. 12 shows a bulk semiconductor structure 1200 after subsequent processing steps of fin merging. The fins merge in a manner similar to that described for the SOI structure in fig. 1. Some finfets may include multiple merged fins, while other finfets may be single-fin finfets. Epitaxial region 1218 merges fins 1206A and 1206B. The dielectric fin 1206C serves as an isolation region that prevents the epitaxial region 1218 from affecting the semiconductor fins 1206D, 1206F, 1206H, and 1206J on the right side of the dielectric fin 1206C. In some embodiments, the fins 1206A and 1206B comprise NFET transistors, and the epitaxial region 1218 may be in-situ doped with arsenic or phosphorous.
Epitaxial region 1222 is bounded by dielectric fin 1206C and dielectric fin 1206E. In some embodiments, the semiconductor fin 1206D may be part of a PFET transistor, and the epitaxial region 1222 may be in-situ doped with boron and in direct physical contact with the semiconductor fin 1206D. The semiconductor fin 1206D may be part of a single-fin finFET. Such finfets have been used in various applications, such as pull-up gates used in SRAMs. It is therefore advantageous to be able to place a single semiconductor fin (1206D) between two dielectric fins (1206C and 1206E) to support these applications.
Epitaxial region 1224 is defined by dielectric fin 1206E and dielectric fin 1206G. The epitaxial region 1224 is in direct physical contact with the semiconductor fin 1206F. The semiconductor fin 1206F may be part of an additional single-fin finFET. In some embodiments, the semiconductor fin 1206F may be part of a single-fin PFET, and the epi region 1224 may be doped with boron in a similar manner as the epi region 1222.
Epitaxial region 1220 merges fins 1206H and 1206J. Dielectric fin 1206G serves as an isolation region that prevents epitaxial region 1220 from affecting semiconductor fins 1206A, 1206B, 1206D, and 1206F on the left side of dielectric fin 1206G. In some embodiments, fins 1206H and 1206J are part of an NFET transistor, and epitaxial region 1220 may be in-situ doped with arsenic or phosphorous in a manner similar to epitaxial region 1218. From this point on, industry standard process flows can be employed. For completing the finFET.
A flow of processing steps of a method according to an embodiment of the invention.
In the process of the present invention, the catalyst is,
in 1350, fins are formed on the substrate (see 106 of fig. 1).
In step 1352, a mask is deposited over the subset of fins (see 208 of fig. 2).
In step 1354, the gas cluster ion beam is directed to a structure (see gold of fig. 3 and 4).
In 1356 process steps, the mask region is removed (see fig. 6).
In 1358 process steps, the fins are merged by epitaxially grown silicon (see 718, 720, 722, and 724 of fig. 7).
Embodiments of the present invention provide finFET structures with dielectric fins and methods of fabricating the same.
In an embodiment, a Gas Cluster Ion Beam (GCIB) tool is used to apply an ion beam to the exposed fins, which convert the fins from a semiconductor material such as silicon to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art, where some fins are removed before they merge, in embodiments of the invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins, where it is desirable to achieve isolation between groups of fins including various finFET devices on an Integrated Circuit (IC).
Advantages of embodiments of the present invention include facilitating a single dummy dielectric fin to provide robust isolation, which increases circuit density. In applications such as SRAM, it is important to increase circuit density, and thus, embodiments of the present invention are well suited for use in SRAM devices.
Another advantage of embodiments of the present invention is that by leaving the dielectric fins in place, rather than removing the fins, the topography of the various layers deposited on the fins during the completion of the fabrication process is more uniform. The more uniform morphology reduces complexity in downstream processing steps and therefore can be used to improve product yield.
Although the invention has been shown and described with respect to one or more preferred embodiments, certain equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.), the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular implementation.

Claims (3)

1. A fin field effect transistor, comprising: a semiconductor substrate; forming a plurality of fins on a semiconductor substrate; wherein a first subset of the plurality of fins is comprised of a semiconductor material, and wherein a second subset of the plurality of fins is comprised of a dielectric material; wherein the second subset of the plurality of fins is comprised of silicon nitride and is interleaved with the first subset of the plurality of fins;
and wherein a set of fins from the first subset of the plurality of fins is merged with the epitaxially grown semiconductor material, and wherein at least one set of fins from the first subset of the plurality of fins is merged with the n-doped epitaxially grown semiconductor material, and wherein at least another set of fins from the first subset of the plurality of fins is merged with the p-type doped epitaxially grown semiconductor material.
2. A fin field effect transistor, comprising: a semiconductor substrate; an insulator layer disposed on the semiconductor substrate; a plurality of fins disposed on the insulator layer; wherein a first subset of the plurality of fins is comprised of a semiconductor material, and wherein a second subset of the plurality of fins is comprised of a dielectric material; wherein the second subset of the plurality of fins is comprised of silicon nitride and is interleaved with the first subset of the plurality of fins; and wherein a set of fins from the first subset of the plurality of fins is merged with the epitaxially grown silicon, and wherein at least one set of fins from the first subset of the plurality of fins is merged with the n-doped epitaxially grown silicon, and wherein at least another set of fins from the first subset of the plurality of fins is merged with the p-type doped epitaxially grown silicon.
3. The method of converting a subset of a plurality of semiconductor fins on a semiconductor structure into dielectric fins of claim 2, the method comprising: masking a first subset of the plurality of fins; reserving a second subset of the plurality of fins as unmasked fins; and applying a gas cluster ion beam to the unmasked fins to convert the unmasked fins into dielectric fins.
CN202110366705.5A 2021-04-06 2021-04-06 Fin field effect transistor and method for forming blunt fin by gas cluster ion beam Withdrawn CN113178476A (en)

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