CN113169204A - Image sensor, method of manufacturing the same, and imaging device having image sensor mounted thereon - Google Patents
Image sensor, method of manufacturing the same, and imaging device having image sensor mounted thereon Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14607—Geometry of the photosensitive area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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Abstract
An image sensor, comprising: a semiconductor substrate having a first surface and a second surface; a photosensitive region on the semiconductor substrate; a readout circuit connected to the photosensitive region; the photosensitive region comprises a first doping region and a second doping region, the first doping region is arranged close to the first surface, a groove extending towards the first surface is formed in the second doping region, and a semiconductor layer is arranged on the groove wall of the groove. The imaging effect can be improved. A method of fabricating the image sensor and an imaging apparatus are also provided.
Description
Technical Field
The present invention relates to the field of image sensor technology, and in particular, to an image sensor, a method of manufacturing the same, and an imaging device equipped with the same.
Background
The image sensor is widely applied to the fields of consumer electronics, security monitoring, industrial automation, artificial intelligence, Internet of things and the like, is used for collecting and sorting image data information, and provides an information source for subsequent processing and application.
The image sensor may be divided into a photosensitive circuit region and a peripheral reading circuit region by functional composition. The photosensitive circuit region is used for converting optical signals into electric signals through a photodiode, storing the electric signals and then delivering the electric signals to a subsequent peripheral reading circuit for converting the electric signals into digital image signals.
In practical applications, the lighting conditions in the environment are complex, some are very dark, some are very bright, that is, in some environments, the contrast between the light and the dark is very strong, so that in order to clearly present the details of the dark place of the image, the image sensor needs to increase the exposure time to increase the signal amount in the dark place. However, since the exposure time of the entire image sensor is uniform, the exposure time cannot be changed according to the brightness of different spatial regions, and when the exposure time is long, the bright regions in the image are overexposed to appear a dead white, so that the dynamic Range (Dynami c Range, DR) of the image sensor is insufficient.
Disclosure of Invention
The application provides an image sensor, a manufacturing method thereof and an imaging device with the image sensor.
In a first aspect, the present application provides an image sensor comprising:
a semiconductor substrate having opposing first and second surfaces;
a photosensitive region on the semiconductor substrate, the photosensitive region capable of generating photogenerated carriers under illumination;
a readout circuit connected to the photosensitive region for reading out a voltage signal generated by the photo-generated carriers;
the photosensitive region comprises a first doped region of a first conductivity type and a second doped region of a second conductivity type, the first doped region is arranged close to the first surface, and the second doped region is arranged on one side, away from the first surface, of the first doped region; the second doping area is provided with a groove extending towards the first surface, and the wall of the groove is provided with a semiconductor layer of the first conduction type.
In a second aspect, the present application provides an imaging apparatus carrying any of the above-described image sensors.
In a third aspect, the present application provides a method for fabricating an image sensor, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
forming a photosensitive area on the semiconductor substrate, wherein the photosensitive area comprises a first doping area of a first conductivity type and a second doping area of a second conductivity type, the first doping area is arranged close to the first surface, and the second doping area is arranged on one side of the first doping area far away from the first surface;
forming a readout circuit on the semiconductor substrate, wherein the readout circuit is connected with the photosensitive area;
forming a trench in the second doped region extending toward the first surface;
a semiconductor layer having a first conductivity type is formed on a wall of the trench.
The embodiment of the application provides an image sensor, a manufacturing method thereof and an imaging device carrying the image sensor, and the imaging effect can be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure as claimed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an image sensor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the functional components of an image sensor in one embodiment;
FIG. 3 is a schematic diagram of a pixel in an image sensor in one embodiment;
FIG. 4 is a timing diagram illustrating pixel imaging in an image sensor, according to one embodiment;
FIG. 5 is a schematic diagram of a trench structure on an image sensor in one embodiment;
FIG. 6 is a schematic diagram of a trench structure on an image sensor in another embodiment;
FIG. 7 is a schematic diagram of a trench structure on an image sensor in accordance with yet another embodiment;
FIG. 8 is a schematic diagram of a trench structure on an image sensor in accordance with yet another embodiment;
fig. 9 is a schematic flowchart illustrating a method for manufacturing an image sensor according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of an imaging device according to an embodiment of the present application.
Reference numerals: 100. an image sensor; 110. a semiconductor substrate; 111. a first surface; 112. a second surface; 120. a light sensing area; 121. a first doped region; 122. a second doped region; 130. a readout circuit; 131. a floating diffusion region; 132. a conveying pipe; 133. a voltage output circuit; 140. a trench; 141. a trench wall; 142. the bottom of the tank; 143. a notch; 101. a semiconductor layer; 102. a dielectric material;
200. an image sensor; 210. a photosensitive circuit region; 211. a light sensing unit; 201. a photodiode; 202. a conveying pipe; 203. a floating diffusion region; 204. a reset tube; 205. a source follower tube; 206. a row gate pipe; 220. a peripheral circuit;
600. an imaging device; 601. an image sensor; 602. a processor; 603. a display screen.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The flow diagrams depicted in the figures are merely illustrative and do not necessarily include all of the elements and operations/steps, nor do they necessarily have to be performed in the order depicted. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Fig. 1 is a schematic structural diagram of an image sensor 100. Image sensor 100 includes a semiconductor substrate 110, a photosensitive region 120, and readout circuitry 130.
In some embodiments, as shown in fig. 2, the image sensor 200 may be divided into a photosensitive circuit region 210 and a peripheral circuit 220 according to functional composition, wherein the photosensitive circuit region 210 may include tens of thousands to hundreds of millions of photosensitive units 211, for example, the photosensitive circuit region 210 may be formed by a large number of photosensitive units 211 arranged in a certain manner, i.e., a so-called pixel array. The peripheral circuit 220 is responsible for converting the signal induced by the light sensing unit 211 into a digital signal and reading out the digital signal.
The light sensing units 211 of the image sensor 200 may also be referred to as pixels (pixel). In some embodiments, as shown in fig. 3, the light sensing unit 211 includes a photodiode 201, a transfer Transistor (TX)202, a Floating Diffusion (FD)203, a reset transistor (RST)204, a source follower transistor (SF)205, and a row select transistor (SEL) 206.
In some embodiments, the typical operation timing of the light sensing unit 211 is shown in fig. 4.
Referring to fig. 3 and 4, the photosensitive unit 211 typically operates as follows:
a. a reset stage: the reset tube 204 is turned on (i.e., turned on), the row strobe tube 206 is turned off (i.e., turned off), the transfer tube 202 is first turned on (i.e., turned on), the photo-generated carriers in the photodiode 201 are cleared, and then the transfer tube 202 is turned off (i.e., turned off);
b. and (3) an exposure stage: the transfer tube 202 is maintained in an off state (i.e., an off state), and the photodiode 201 generates photo-generated carriers under illumination;
c. a signal reading stage: the row gate tube 206 is turned on, then the reset tube 204 is turned off, the floating diffusion region 203 is floated to a high potential, and after stabilization, the reference voltage Vref is read at the output terminal (PXD terminal) (SHR stage), for example, the reference voltage Vref (i.e., reference signal) can be read by setting a read reference voltage enable signal of a peripheral circuit to a high level; next, the transmission tube 202 is opened, the photo-generated carriers in the photodiode 201 are poured into the floating diffusion region 203, the potential of the floating diffusion region 203 becomes lower as the photo-generated carriers enter, after the transmission of the photo-generated carriers is completed, the transmission tube 202 is closed, and after stabilization, the sampling hold signal voltage Vs ig is read at the output end (SHS stage), for example, the sampling hold signal voltage Vs ig can be read by setting the read sampling hold signal voltage enable signal of the peripheral circuit to be at a high level.
Then, according to the difference Δ V between the reference voltage Vref and the sample hold signal voltage Vs i g being Vref-Vs ig, that is, the voltage difference caused by the incident light signal, the difference is converted into a digital signal representing image information through a subsequent analog-to-digital (AD) conversion circuit. Such as analog-to-digital conversion by peripheral circuit 220.
In some embodiments, the image sensor 200 may include the peripheral circuit 220, and certainly, the peripheral circuit 220 may not be included, for example, functions such as analog-to-digital conversion may be implemented by an additionally mounted peripheral circuit.
As shown in fig. 1, the image sensor 100 includes a semiconductor substrate 110, a photosensitive region 120, and readout circuitry 130.
The semiconductor substrate 110 has a first surface 111 and a second surface 112 opposite to each other, the photosensitive region 120 is located on the semiconductor substrate 110, the photosensitive region 120 generates photo-generated carriers under illumination, and the readout circuit 130 is connected to the photosensitive region 120 and is configured to read out voltage signals generated by the photo-generated carriers. In some embodiments, the photosensitive region 120 may also be referred to as a photodiode.
Illustratively, the semiconductor substrate 110 may include at least one of a silicon substrate, a germanium substrate, and a silicon carbide substrate.
Illustratively, several tens of thousands to several hundred million of photosensitive regions 120 are formed on the semiconductor substrate 110, it being understood that an array of photosensitive regions 120 is formed on the semiconductor substrate 110.
In some embodiments, as shown in fig. 1, readout circuitry 130 includes a floating diffusion region 131 and a transfer tube 132.
Wherein the floating diffusion region 131 is located on a side of the semiconductor substrate 110 close to the first surface 111, and the floating diffusion region 131 is used for receiving photogenerated carriers; the transfer tube 132 can be controlled to connect or disconnect the photosensitive region 120 and the floating diffusion region 131.
Referring to fig. 1, the transfer tubes 132 are controlled to communicate with the photosensitive region 120 and the floating diffusions 131 during the reset phase. A control signal line, such as a pass transistor 132, receives a high level to turn on the pass transistor 132 so that the photosensitive region 120 and the floating diffusion 131 communicate. The floating diffusion region 131 is connected to a reset power supply through a conducted reset tube, the photosensitive region 120 and the floating diffusion region 131 are reset under the action of the reset power supply, photo-generated carriers in the photosensitive region 120 are emptied, and then the transfer tube 132 is closed; during the exposure period, the transmission tube 132 is kept closed, and the photosensitive region 120 generates photo-generated carriers under illumination; in the signal readout phase, the transmission tube 132 may be controlled to communicate the photosensitive region 120 and the floating diffusion region 131, so that the photo-generated carriers in the photosensitive region 120 are filled into the floating diffusion region 131, the potential of the floating diffusion region 131 becomes lower as the photo-generated carriers enter, and after the transmission of the photo-generated carriers is completed, the transmission tube 132 is closed.
In some embodiments, as shown in fig. 1, the readout circuit 130 further includes a voltage output circuit 133, the voltage output circuit 133 being connected to the floating diffusion region 131 for transmitting a voltage signal of the floating diffusion region 131 to peripheral circuits. Illustratively, the voltage output circuit 133 may include a source follower transistor (SF) and a row strobe transistor (SEL). It should be noted that the voltage output signal includes a sample-and-hold signal and a reference signal. Wherein the sample-and-hold signal is generated from photo-generated carriers.
As shown in fig. 1 and 5, the photosensitive region 120 includes a first doped region 121 of the first conductivity type and a second doped region 122 of the second conductivity type, the first doped region 121 is disposed near the first surface 111, and the second doped region 122 is disposed on a side of the first doped region 121 away from the first surface 111.
For example, the first conductive type may be a P-type, and the second conductive type may be an N-type. Or the first conductivity type may be N-type, and the second conductivity type is P-type. The first conductivity type is P-type, and the second conductivity type is N-type.
For example, the first doped region 121 may be referred to as a PI N, and the second doped region 122 may be referred to as a PD. For example, the photosensitive region 120 includes a p-i-n photodiode (pi n-PD).
Illustratively, the photosensitive region 120 includes an ion implantation layer PD doped by an N type and an ion implantation layer PI N doped by a P type.
It can be understood that the size of the full well Capacity (Fu l-We l Capacity, FWC) of the photosensitive region 120 essentially depends on the size of the PN junction capacitance between the PI N and the PD, but the area of the photosensitive region 120 is usually limited, and the full well Capacity of the photosensitive region 120 is limited by the junction area, so when the illumination condition in the environment is complicated and the contrast between light and dark is very strong, the image sensor 100 needs to increase the exposure time to clearly present the details of the image dark to increase the signal amount in the dark.
However, since the exposure time of the entire image sensor 100 is uniform, the exposure time cannot be changed according to the brightness of different spatial regions, and when the exposure time is long, the bright regions in the image are overexposed, and a dead white appears, so that the Dynamic Range (DR) of the image sensor 100 is insufficient.
The larger the junction area of the PI N/PD, the larger the PN junction capacitance, and the larger the full well capacity of the photosensitive region 120. The area of the photosensitive region 120 is typically limited and the full well capacity of the photosensitive region 120 is limited by the junction area. In view of this finding, the inventors of the present application have improved the image sensor 100 by increasing the junction capacitance between the second doped region 122 and the surrounding first conductivity type semiconductor to increase the full well capacity of the photosensitive region 120.
According to the dynamic range calculation formula: DR is 20 × l og (FWC ÷ Noi se), where DR denotes the dynamic range of the image sensor 100, FWC denotes the full well capacity of the photosensitive region 120, Noi se denotes Read noise (Read Noi se), and l og () denotes a logarithmic operation, it being understood that: the dynamic range of the image sensor 100 may be increased by increasing the full well capacity of the photosensitive region 120.
In some embodiments, the second doped region 122 has a trench 140 formed therein and extending toward the first surface 111, and the semiconductor layer 101 of the first conductivity type is on a trench wall 141 of the trench 140. Compared to the PN junction capacitance of a general photodiode, a large area PN junction interface is formed near the trench 140, i.e., the capacitance between the second doped region 122 and the surrounding first conductivity type semiconductor is increased.
It can be understood that the second doped region 122 of the second conductivity type and the semiconductor layer 101 of the first conductivity type form a PN junction capacitance, so that the PN junction capacitance of the photosensitive region 120 includes a capacitance between the first doped region 121 and the second doped region 122 and a capacitance between the second doped region 122 and the semiconductor layer 101, which can improve the charge storage capability of the photosensitive region 120, that is, the charge storage capability of the photosensitive region 120, and increase the maximum charge storage capability, that is, the full well capacity of the photosensitive region 120 is improved, the full well capacity that photogenerated carriers are not easily exceeded can be prevented from overflowing, so that more photogenerated carriers can be retained in the photosensitive region 120, image details at a bright place are prevented from being lost, and the dynamic range of the image sensor 100 is improved.
In some embodiments, the trench walls 141 of the trench 140 extend from the second surface 112 toward the first surface 111, and the trench walls 141 extend at least partially into the interior of the second doped region 122.
Illustratively, one or more trenches 140 may be etched, such as dry or wet etched, on the back side, i.e., the second surface 112, of the second doped region 122, and the trenches 140 penetrate into the interior of the second doped region 122. For example, the groove bottom 142 of the trench 140 is located inside the second doped region 122. The capacitance between the second doped region 122 and the semiconductor layer 101 can be increased. It is understood that the groove bottom 142 of the trench 140 may not be located inside the second doped region 122, for example, the groove bottom 142 of the trench 140 reaches the side of the second doped region 122 close to the second surface 112, and the full well capacity of the photosensitive region 120 may be improved by configuring the capacitance between the second doped region 122 and the semiconductor layer 101.
Illustratively, the depth of the trench 140 is 0.5 to 5 microns. The depth of the trench 140 may be determined according to the structure of the image sensor 100, such as the thickness of the photosensitive region 120, the thickness of the semiconductor substrate 110, and the parameter requirements of the image sensor 100, such as the full well capacity, the dynamic range, and the like.
Illustratively, the width of the trench 140 ranges from 0.1 to 0.5 microns. The width of the trench 140 may be determined according to the structure of the image sensor 100 (e.g., the width of the photosensitive region 120), the processing process of the image sensor 100 (e.g., the processing accuracy of the etching process, etc.), and the parameter requirements of the image sensor 100, such as the full well capacity, the dynamic range, etc., to determine the depth of the trench 140, etc. Illustratively, the wider the width of the trench 140, the larger the area of the semiconductor layer 101 that is present on the trench walls 141, the more the full well capacity of the photosensitive region 120 is increased, given the length and number of the trenches 140.
In some embodiments, as shown in fig. 1, the width of the notch 143 of the groove 140 is greater than or equal to the width of the groove bottom 142 of the groove 140.
Illustratively, the groove wall 141 of the trench 140 may have a slope shape to facilitate formation of the first conductive type semiconductor layer 101 on the groove wall 141 and the groove bottom 142, and may facilitate etching processing of the trench 140.
Illustratively, the width of the slot 143 is 0.5 microns and the width of the slot bottom 142 is 0.2 microns; or the width of the notch 143 is 0.4 microns and the width of the groove bottom 142 is 0.1 microns; although not limited thereto.
In some embodiments, one or more trenches 140 are formed in the second doped region 122 of the photosensitive region 120. As shown in fig. 1, 5 and 6, a plurality of trenches 140 are formed in the second doping region 122, as shown in fig. 7, one trench 140 is formed in the second doping region 122, as shown in fig. 8, two trenches 140 are formed in the second doping region 122.
Illustratively, as shown in fig. 1, 5, 6, and 8, the plurality of channels 140 may be arranged in parallel. For example, the efficiency of the groove 140 processing can be improved, for example, a plurality of linear grooves 140 arranged in parallel can be etched simultaneously.
Illustratively, as shown in FIG. 6, at least two grooves 140 are disposed to intersect. A greater number of trenches 140 may be formed in the photosensitive region 120 to increase the full well capacity of the photosensitive region 120.
Illustratively, as shown in fig. 5 and 6, the grooves 140 include straight grooves, which may facilitate machining of the grooves 140.
Illustratively, as shown in fig. 7, the trench 140 includes a spiral-shaped trench, and a greater length of the trench 140 may be formed in the second doped region 122 to increase the full well capacity of the photosensitive region 120.
Illustratively, as shown in fig. 8, the trench 140 includes an annular trench, for example, one or more annular trenches, and a trench 140 having a longer total length may be formed in the second doping region 122 to increase the full well capacity of the photosensitive region 120.
In some embodiments, the semiconductor layer 101 is a doped layer of the first conductivity type. For example, semiconductor layer 101 comprises a P-type doped semiconductor. The P-type doped semiconductor may form a PN junction capacitance with the N-type second doped region 122. Alternatively, the semiconductor layer 101 includes an N-type doped semiconductor. The N-type doped semiconductor may form a PN junction capacitance with the P-type second doped region 122.
For example, the wall 141 of the trench 140 may be doped to form a doped layer having the first conductivity type. For example, the trench 140 is etched from the second surface 112 into the second doped region 122, and then the wall 141 of the trench 140 is doped, such as by ion implantation or thermal doping, to form the first conductive type doped layer.
In some embodiments, trench 140 is filled with a negatively charged dielectric material 102, wherein dielectric material 102 induces a P-type semiconductor layer 101 on trench walls 141 of trench 140.
Illustratively, the trench 140 is etched from the second surface 112 to the inside of the second doped region 122, and then the trench 140 is filled with a negatively charged dielectric material 102, such as at least one of silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide, and silicon nitride. It is understood that the dielectric material 102 is silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride or a multilayer mixture thereof.
The negatively charged dielectric material 102 can induce a high concentration of P-type hole accumulation layer, i.e., P-type semiconductor layer 101, on the surface of the trench 140 in the N-type second doped region 122, and the P-type semiconductor layer 101 and the N-type second doped region 122 can form a PN junction capacitance.
Illustratively, the dielectric material 102 is a dielectric material 102 having an absorption of visible light that is less than a first value. Specifically, the first value may be determined according to parameter requirements of the image sensor 100, such as sensitivity to light, and the like. In one embodiment, the first value is five percent. For example, if the image sensor 100 is expected to be applied in a dark environment, the dielectric material 102 needs to have less absorption of visible light, so that more visible light can be transmitted to ensure the photosensitive efficiency of the photosensitive region 120; if the image sensor 100 is expected to be applied in a brighter environment, the absorptivity of the dielectric material 102 to visible light may be slightly larger to appropriately reduce the photosensitive efficiency of the photosensitive region 120 and prevent overexposure.
According to the image sensor provided by the embodiment of the application, the groove is formed in the photosensitive area of the image sensor, the semiconductor layer is formed on the groove wall of the groove, so that the PN junction capacitance is formed between the semiconductor layer and the photosensitive area, the charge storage capacity of the photosensitive area can be improved, namely, the full-well capacity of the photosensitive area is improved, more photon-generated carriers can be reserved in the photosensitive area, and the dynamic range of the image sensor is improved.
Referring to fig. 9 in conjunction with the above embodiments, fig. 9 is a schematic flowchart of a method for manufacturing an image sensor according to an embodiment of the present disclosure.
As shown in fig. 9, the manufacturing method includes steps S110 to S150.
Step S110, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
step S120, forming a photosensitive region on the semiconductor substrate, wherein the photosensitive region comprises a first doped region of a first conductivity type and a second doped region of a second conductivity type, the first doped region is arranged close to the first surface, and the second doped region is arranged on one side of the first doped region, which is far away from the first surface;
step S130, forming a readout circuit on the semiconductor substrate, wherein the readout circuit is connected with the photosensitive area;
step S140, forming a trench extending toward the first surface in the second doped region;
step S150, a semiconductor layer having a first conductivity type is formed on the wall of the trench.
In some embodiments, the forming a trench in the second doped region extending toward the first surface includes:
the trench is formed from the second surface toward the first surface, and the trench wall extends at least partially into an interior of the second doped region.
Illustratively, the bottom of the trench is located inside the second doped region.
Illustratively, the width of the notch of the groove is greater than or equal to the width of the groove bottom of the groove.
In some embodiments, the width of the trench ranges from 0.1 to 0.5 microns.
In some embodiments, the trench has a depth of 0.5 to 5 microns.
In some embodiments, forming a trench in the second doped region extending toward the first surface includes:
forming one or more of the trenches in the second doped region extending toward the first surface.
Illustratively, a plurality of the grooves are arranged in parallel or at least two of the grooves are arranged in an intersecting manner.
Illustratively, the groove includes at least one of a linear groove, a spiral groove, and an annular groove.
In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.
Illustratively, the forming a semiconductor layer having a first conductivity type on the trench wall includes:
and filling a negatively charged dielectric material in the groove so that the dielectric material induces a P-type semiconductor layer on the groove wall of the groove.
Illustratively, the dielectric material has an absorptivity to visible light smaller than a specific value.
Illustratively, the trench is filled with at least one of silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide and silicon nitride.
In some embodiments, the forming a semiconductor layer having a first conductivity type on the trench wall includes:
and doping the groove wall of the groove to form a doping layer with a first conductivity type.
In some embodiments, the forming a readout circuit on the semiconductor substrate includes:
forming a floating diffusion region on one side of the semiconductor substrate close to the first surface;
and forming a transmission pipe between the photosensitive area and the floating diffusion area, wherein the transmission pipe can be controlled to connect or disconnect the photosensitive area and the floating diffusion area.
According to the manufacturing method of the image sensor, the groove is formed in the photosensitive area of the image sensor, the semiconductor layer is formed on the groove wall of the groove, and the PN junction capacitance is formed between the semiconductor layer and the photosensitive area, so that the charge storage capacity of the photosensitive area can be improved, namely the full-well capacity of the photosensitive area is improved, more photon-generated carriers can be reserved in the photosensitive area, and the dynamic range of the image sensor is improved.
Referring to fig. 10 in conjunction with the above embodiments, fig. 10 is a schematic block diagram of an imaging device 600 according to an embodiment of the present application. The imaging device 600 is equipped with the image sensor 601 described above.
In some embodiments, as shown in fig. 10, the imaging device 600 may further include a processor 602, and the processor 602 is configured to process the image data output by the image sensor 601 into a shot that can be presented on the display screen 603.
In some embodiments, as shown in fig. 10, the imaging device 600 may further include a display screen 603, and the processor 602 is configured to process the image data output by the image sensor 601 into a shot that can be presented on the display screen 603.
Illustratively, the imaging device may be a terminal. The terminal may be a terminal device integrating a camera and a display screen, including but not limited to a smart phone, a tablet, a palm computer, a camera, etc. The camera in the terminal can be used for realizing photographing and camera shooting functions, and the display screen can be used for realizing a preview function of a photographed picture, namely, a picture of the current income of the camera is displayed in real time for previewing, so that the effect of a viewfinder is achieved.
The specific principle and implementation of the imaging device provided in the embodiment of the present application are similar to those of the image sensor in the foregoing embodiments, and are not described herein again.
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It should also be understood that the term "and/or" as used in this application and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (32)
1. An image sensor, comprising:
a semiconductor substrate having opposing first and second surfaces;
a photosensitive region on the semiconductor substrate, the photosensitive region capable of generating photogenerated carriers under illumination;
a readout circuit connected to the photosensitive region for reading out a voltage signal generated by the photo-generated carriers;
the photosensitive region comprises a first doped region of a first conductivity type and a second doped region of a second conductivity type, the first doped region is arranged close to the first surface, and the second doped region is arranged on one side, away from the first surface, of the first doped region; the second doping area is provided with a groove extending towards the first surface, and the wall of the groove is provided with a semiconductor layer of the first conduction type.
2. The image sensor of claim 1, wherein a wall of the trench extends from the second surface toward the first surface, and the wall extends at least partially into the interior of the second doped region.
3. The image sensor of claim 1 or 2, wherein a groove bottom of the trench is located inside the second doped region.
4. The image sensor according to claim 1 or 2, wherein a width of a notch of the trench is equal to or greater than a width of a groove bottom of the trench.
5. The image sensor of any of claims 1-4, wherein the width of the trench is in a range of 0.1 to 0.5 microns.
6. The image sensor of any of claims 1-5, wherein the trench has a depth of 0.5 to 5 microns.
7. The image sensor as in any of claims 1-6, wherein one or more of the trenches are formed in the second doped region of the photosensitive region.
8. The image sensor of claim 7, wherein a plurality of the trenches are arranged in parallel or at least two of the trenches intersect.
9. The image sensor of claim 7, wherein the trench comprises at least one of a linear trench, a spiral trench, and an annular trench.
10. The image sensor as claimed in any one of claims 1 to 9, wherein a wall of the trench has a semiconductor layer of the first conductivity type thereon; the first conduction type is a P type, and the second conduction type is an N type.
11. The image sensor as claimed in claim 10, wherein the trench is filled with a negatively charged dielectric material, wherein the dielectric material is capable of inducing a P-type semiconductor layer on the walls of the trench.
12. The image sensor of claim 11, wherein the dielectric material is a dielectric material having an absorbance of visible light less than a first value.
13. The image sensor of claim 11, wherein the trench is filled with at least one of silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide, and silicon nitride.
14. The image sensor of any of claims 1-9, wherein the semiconductor layer is a doped layer of the first conductivity type.
15. The image sensor of any of claims 1-14, wherein the readout circuitry comprises:
the floating diffusion region is positioned on one side, close to the first surface, of the semiconductor substrate and is used for receiving the photon-generated carriers;
and the transmission pipe can be used for controllably connecting or disconnecting the photosensitive area and the floating diffusion area.
16. The image sensor of claim 15, wherein the readout circuit further comprises:
and the voltage output circuit is connected with the floating diffusion region and is used for transmitting the voltage signal of the floating diffusion region to a peripheral circuit.
17. An imaging apparatus carrying the image sensor according to any one of claims 1 to 16.
18. A method of fabricating an image sensor, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
forming a photosensitive area on the semiconductor substrate, wherein the photosensitive area comprises a first doping area of a first conductivity type and a second doping area of a second conductivity type, the first doping area is arranged close to the first surface, and the second doping area is arranged on one side of the first doping area far away from the first surface;
forming a readout circuit on the semiconductor substrate, wherein the readout circuit is connected with the photosensitive area;
forming a trench in the second doped region extending toward the first surface;
a semiconductor layer having a first conductivity type is formed on a wall of the trench.
19. The method of claim 18, wherein forming a trench in the second doped region extending toward the first surface comprises:
the trench is formed from the second surface toward the first surface, and the trench wall extends at least partially into an interior of the second doped region.
20. The method of claim 18 or 19 wherein a bottom of the trench is located within the second doped region.
21. The method of claim 18 or 19, wherein the width of the notch of the groove is equal to or greater than the width of the groove bottom of the groove.
22. The method of any of claims 18-21, wherein the width of the trench is in a range of 0.1 to 0.5 microns.
23. The method of any one of claims 18-22, wherein the depth of the trench is 0.5 to 5 microns.
24. The method of any of claims 18-23, wherein forming a trench in the second doped region extending toward the first surface comprises:
forming one or more of the trenches in the second doped region extending toward the first surface.
25. The method of claim 24, wherein a plurality of the grooves are arranged in parallel or at least two of the grooves intersect.
26. The method of claim 24, wherein the groove comprises at least one of a linear groove, a spiral groove, and an annular groove.
27. The method of any of claims 18-26, wherein the first conductivity type is P-type and the second conductivity type is N-type.
28. The method of claim 27 wherein forming a semiconductor layer of the first conductivity type on the walls of the trench comprises:
and filling a negatively charged dielectric material in the groove so that the dielectric material induces a P-type semiconductor layer on the groove wall of the groove.
29. The method of claim 28, wherein the dielectric material is a dielectric material having an absorbance of visible light less than a specific value.
30. The method of claim 28 wherein the trench is filled with at least one of silicon dioxide, aluminum oxide, hafnium dioxide, tantalum oxide, and silicon nitride.
31. The method of any of claims 18-26, wherein forming the semiconductor layer of the first conductivity type on the trench walls comprises:
and doping the groove wall of the groove to form a doping layer with a first conductivity type.
32. The method of any of claims 18-31, wherein forming a readout circuit on the semiconductor substrate comprises:
forming a floating diffusion region on one side of the semiconductor substrate close to the first surface;
and forming a transmission pipe between the photosensitive area and the floating diffusion area, wherein the transmission pipe can be controlled to connect or disconnect the photosensitive area and the floating diffusion area.
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| PCT/CN2020/099595 WO2022000349A1 (en) | 2020-06-30 | 2020-06-30 | Image sensor and manufacturing method therefor, and imaging device carrying same |
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| US20130234202A1 (en) * | 2012-03-08 | 2013-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Image Sensor Isolation Region and Method of Forming the Same |
| US20160163897A1 (en) * | 2014-12-03 | 2016-06-09 | Renesas Electronics Corporation | Imaging device |
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Application publication date: 20210723 |