CN113162131A

CN113162131A - Reverse charging system, reverse charging method and terminal equipment

Info

Publication number: CN113162131A
Application number: CN202010075823.6A
Authority: CN
Inventors: 马鹏飞; 付颖科
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-01-22
Filing date: 2020-01-22
Publication date: 2021-07-23

Abstract

The embodiment of the application provides a reverse charging system, a reverse charging method and terminal equipment, which relate to the field of communication, and the method comprises the following steps: the main terminal equipment can output an electric signal on a D-line of an OTG (over the glass) line connected with the auxiliary terminal equipment in the process of reversely charging the auxiliary terminal equipment, so that the auxiliary terminal equipment identifies the USB port as a CDP (continuous data packet) based on a high level on the D-line, the auxiliary terminal equipment can be charged under the CDP with larger current transmission capacity, and the charging efficiency is improved.

Description

Reverse charging system, reverse charging method and terminal equipment

Technical Field

The embodiment of the application relates to the technical field of terminals, in particular to a reverse charging system, a reverse charging method and terminal equipment.

Background

With the continuous development of communication technology, the functions of the mobile phone are also more and more powerful. One function of the mobile phone is to supply power to other mobile phones or devices, so as to provide a charging mode under special conditions, such as a scene that a charging power supply cannot be found in time, wherein the charging mode is a reverse charging mode.

In the prior art, when a device such as a mobile phone or a tablet is used for carrying out reverse charging on other devices, the mobile phone or the tablet can provide 1.5A or even 2A current as a main device for providing current, but the device to be charged usually identifies a USB Port as a Standard Downstream Port (SCP) based on the BC1.2 protocol requirement of the USB, and in this case, the device to be charged only carries out charging under the current of 500mA after identifying the SCP Port according to the current corresponding relation specified by BC 1.2.

Disclosure of Invention

The application provides a reverse charging method, a reverse charging system and a terminal device, which can charge a slave terminal device under the current magnitude corresponding to a CDP port.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a reverse charging method, where the method is applied to a slave terminal device, the slave terminal device is connected to a master terminal device through an OTG line, the OTG line includes a D + line, a D-line, and a VBUS line, and the method includes: the slave terminal device outputs a first electric signal on the D + line in response to the detected power supply signal output by the master terminal device on the VBUS line, the first electric signal making the level on the D + line high. Then, the slave terminal device acquires the level on the D-line in response to the detected second electric signal output by the master terminal device on the D-line. If the level on the D-line acquired from the terminal device is a high level, the terminal device stops outputting the first electrical signal on the D + line, outputs the third electrical signal on the D-line, and acquires the level on the D + line. And if the level on the D + line acquired from the terminal equipment is low level, the slave terminal equipment determines that the type of the USB port connected with the main terminal equipment through the OTG line is CDP, and charges according to the current magnitude corresponding to the CDP.

Based on the above manner, the slave device can determine that the USB port is not the SDP after detecting that the D-line is at a high level, and further determine that the USB port is the CDP based on the result, and the slave terminal device can charge under the power supply signal provided by the master terminal device based on the current magnitude corresponding to the CDP.

In one possible implementation, the D + line is connected to a first comparator in the main terminal device, and the voltage of the first electrical signal is greater than a first reference voltage of the first comparator

Based on the above manner, it is realized that the slave terminal device can cause the level on the D + line indicated as the output result of the first comparator to change to the high level by outputting the first electric signal having a voltage greater than the first reference voltage.

In one possible implementation, the D-line is connected to a second comparator in the slave terminal device, and the voltage of the second electrical signal is greater than a second reference voltage of the second comparator; acquiring a level on a D-line, comprising: and reading a first output value of the second comparator as a first preset value from the terminal equipment, determining that the level on the D-line is a high level, and confirming that the USB port type is CDP or DCP, wherein the first output value is the result of comparing the voltage of the second electric signal with a second reference voltage by the second comparator.

Based on the mode, the slave terminal equipment can determine that the level on the D-line is high level by reading the output value of the second comparator, so that the USB port is not SDP, namely the USB port is CDP or DCP.

In one possible implementation, the D + line is connected to a third comparator in the slave terminal device; acquiring a level on a D + line, comprising: and reading the second output value of the third comparator as a second preset value from the terminal equipment, and determining the level on the D + line as a low level.

Based on the mode, the slave terminal equipment can determine that the level on the D + line is low level by reading the output value of the third comparator.

In one possible implementation, the CDP corresponds to a current of 1.5A.

Based on the mode, the slave terminal equipment can be charged based on the current corresponding to the CDP, namely 1.5A, so that the slave terminal equipment can obtain larger transmission current compared with the SCP.

In a second aspect, an embodiment of the present application provides a reverse charging method, where the method is applied to a master terminal device, the master terminal device is connected to a slave terminal device through an OTG line, the OTG line includes a D + line, a D-line, and a VBUS, and the method includes: after the main terminal equipment outputs a power supply signal on the VBUS line, responding to a detected first electric signal output by the slave terminal equipment on the D + line, and acquiring the level on the D + line; and if the level on the D + line is high level, the main terminal equipment controls the first power supply module to output a second electric signal on the D-line, and the second electric signal enables the level on the D + line to be high level.

Based on the manner, the master terminal device can make the level on the D + line be high level by outputting the electric signal on the D-line, so that the slave device can determine the USB port non-SDP port after detecting that the level on the D-line is high level, and further make the slave device charge under the current corresponding to the CDP.

In one possible implementation, the D + line is connected to a first comparator in the main terminal device, and a voltage of the first electrical signal is greater than a first reference voltage of the first comparator; acquiring a level on a D + line, comprising: and the main terminal equipment reads a first output value of the first comparator as a first preset value, and determines that the level on the D + line is a high level, wherein the first output value is the result of comparing the voltage of the first electric signal with the first reference voltage by the first comparator.

Based on the above manner, the main terminal device can acquire that the level on the D + line is the high level based on the read output value of the first comparator.

In one possible implementation, the method further includes: and after the preset time length, the main terminal equipment stops outputting the second electric signal on the D-line.

Based on the above manner, the main terminal equipment recovers the original state in the main equipment after waiting for the preset time, namely, stops outputting the second electric signal to wait for the next reverse charging process, and repeats the steps in the application.

In a third aspect, an embodiment of the present application provides a reverse charging system, where the system includes a master terminal device and a slave terminal device connected by an OTG line, the master terminal device includes a first processor, a first power module, a second power module and a first comparator, and the slave terminal device includes a second processor, a third power module, a fourth power module, a fifth power module and a second comparator; the first power supply module is connected with the third power supply module through a VBUS wire of the OTG wire and used for outputting a power supply signal on the VBUS wire; the fourth power module is connected with the second processor, is connected with the first comparator through a D + line of the OTG line, and is used for responding to the power supply signal on the VBUS line detected by the second processor and outputting a first electric signal on the D + line, wherein the first electric signal enables the level on the D + line to be high level; the first processor is connected with the first comparator and used for responding to a read first output result of the first comparator and determining the level on the D + line, wherein the first output result is the result of the first comparator comparing the voltage on the D + line with a first reference voltage of the first comparator; the second power module is connected with the first processor, is connected with the second comparator through a D-line of the OTG line, and is used for outputting a second electric signal on the D-line if the level on the D + line determined by the first processor is a high level, and the second electric signal enables the level on the D + line to be the high level; the second processor is connected with the second comparator and used for responding to the read second output result of the second comparator and determining the level on the D-line, wherein the second output result is the result of the comparison between the voltage on the D-line and a second reference voltage of the second comparator by the second comparator; if the level on the D + line is high level, the fourth power supply module stops outputting the first electric signal on the D + line; the fifth power supply module is connected with the D-line and used for outputting a third electric signal on the D-line; the second processor is also used for acquiring the level on the D + line; if the level on the D + line is low level, determining that the type of the USB port connected with the main terminal equipment through the OTG line is CDP, and indicating a third power supply module to charge according to the current magnitude corresponding to CDP; and the third power supply module is used for responding to the instruction of the second processor and charging according to the current magnitude corresponding to the CDP.

In one possible implementation, the voltage of the first electrical signal is greater than a first reference voltage of the first comparator; the first processor determines a level on the D + line in response to the read first output result of the first comparator, including: the first processor reads a first output value of the first comparator as a first preset value, and determines that the level on the D + line is a high level.

In one possible implementation, the voltage of the second electrical signal is greater than a second reference voltage of the second comparator; the second processor determines a level on the D-line in response to the read second output result of the second comparator, including: the second processor reads a second output value of the second comparator as a first preset value, determines that the level on the D-line is a high level, and confirms that the USB port type is CDP or DCP.

In a possible implementation manner, the slave terminal device further includes a third comparator, and the third comparator is connected to the D + line; the second processor obtains a level on the D + line, including: and the second processor reads a third output value of the third comparator as a second preset value and determines that the level on the D + line is a low level.

In one possible implementation, the CDP corresponds to a current of 1.5A.

In a fourth aspect, an embodiment of the present application provides a reverse charging system, where the system includes a master terminal device and a slave terminal device connected by an OTG line, and the slave terminal device includes a first processor, a first power module, a second power module, a third power module, and a first comparator; the main terminal equipment is connected with the first power supply module through a VBUS wire of the OTG wire and used for outputting a power supply signal on the VBUS wire; the second power supply module is connected with the first processor, is connected with the main terminal equipment through a D + line of the OTG line, and is used for responding to a power supply signal on the VBUS line detected by the first processor and outputting a first electric signal on the D + line, wherein the first electric signal enables the level on the D + line to be high level; the main terminal equipment is also used for responding to the detected first electric signal on the D + line and acquiring the level on the D + line; the main terminal equipment is also used for outputting a second electric signal on the D-line if the level on the D + line is high level, and the second electric signal enables the level on the D + line to be high level; the first processor is connected with the first comparator and used for responding to the read first output result of the first comparator and determining the level on the D-line, wherein the first output result is the result of the first comparator comparing the voltage on the D-line with the first reference voltage of the first comparator; if the level on the D + line is high level, the first power supply module stops outputting the first electric signal on the D + line; the third power supply module is connected with the D-line and used for outputting a third electric signal on the D-line; the first processor is also used for acquiring the level on the D + line; if the level on the D + line is low level, determining that the USB port type of the universal serial bus physical layer connected with the main terminal equipment through the OTG line is a charging downstream port CDP, and indicating the first power supply module to charge based on the current size corresponding to the CDP; and the first power supply module is used for responding to the indication of the first processor and charging based on the current magnitude corresponding to the CDP.

In one possible implementation, the D + line is connected to a second comparator in the main terminal device, and the voltage of the first electrical signal is greater than a second reference voltage of the second comparator; the master terminal device obtains the level on the D + line, and the method comprises the following steps: and the main terminal equipment reads a first output value of the first comparator as a first preset value, and determines that the level on the D + line is a high level, wherein the first output value is the result of comparing the voltage of the first electric signal with the first reference voltage by the first comparator.

In one possible implementation, the voltage of the second electrical signal is greater than a second reference voltage of the second comparator; the first processor determines a level on the D-line in response to the read first output result of the first comparator, including: the first processor reads the second output value of the first comparator as a first preset value, determines the level on the D-line as high level, and confirms that the USB port type is CDP or DCP.

In one possible implementation, the D + line is connected to a third comparator in the slave terminal device; obtaining a level on a D + line from a terminal device, comprising: and the first processor reads the third output value of the third comparator as a second preset value and determines that the level on the D + line is a low level.

In one possible implementation, the CDP corresponds to a current of 1.5A.

In a fifth aspect, an embodiment of the present application provides a slave terminal device, where the slave terminal device is connected to a master terminal device through an OTG line, the OTG line includes a D + line, a D-line, and a VBUS line, and the slave terminal device includes a processor, a first power module, a second power module, a third power module, and a first comparator; the first power supply module is connected with the main terminal equipment through a VBUS line and used for receiving a power supply signal output by the main terminal equipment on the VBUS line; the second power supply module is connected with the processor, is connected with the main terminal equipment through a D + line, and is used for responding to a power supply signal received by the first power supply module detected by the processor and outputting a first electric signal on the D + line, wherein the first electric signal enables the level on the D + line to be a high level; the first comparator is connected with the processor, is connected with the main terminal equipment through a D-line and is used for comparing the voltage of a second electric signal output on the D-line based on the main terminal equipment with a first reference voltage of the first comparator to obtain a first output result; a processor for determining a level on the D-line in response to the read first output result of the first comparator; if the level on the D-line determined by the processor is a high level, the second power supply module stops outputting the first electric signal on the D + line; the third power supply module is connected with the D-line and used for outputting a third electric signal on the D-line; the processor is also used for acquiring the level on the D + line; if the level on the D + line is low level, determining that the type of the USB port connected with the main terminal equipment through the OTG line is CDP, and indicating the first power supply module to charge according to the current magnitude corresponding to CDP; and the first power supply module is used for responding to the instruction of the processor and charging according to the current magnitude corresponding to the CDP.

In one possible implementation manner, the second power supply module is connected to the second comparator of the main terminal device through a D + line, and the voltage of the first electrical signal is greater than the second reference voltage of the second comparator.

In one possible implementation, the voltage of the second electrical signal is greater than the first reference voltage of the first comparator; and the processor is specifically used for reading the first output value of the first comparator as a first preset value, determining the level on the D-line as a high level and confirming that the USB port type is CDP or DCP.

In a possible implementation manner, the slave terminal device further includes a third comparator, and the third comparator is connected to the D + line; and the processor is specifically used for reading a second output value of the third comparator as a second preset value and determining that the level on the D + line is a low level.

In one possible implementation, the CDP corresponds to a current of 1.5A.

In a sixth aspect, an embodiment of the present application provides a master terminal device, where the master terminal device is connected to a slave terminal device through an OTG line, the OTG line includes a D + line, a D-line, and a VBUS line, and the master terminal device includes a processor, a first power module, a second power module, and a first comparator; the first power supply module is connected with the slave terminal equipment through a VBUS wire and used for outputting a power supply signal on the VBUS wire; the first comparator is connected with the processor, connected with the slave terminal equipment through the D + line and used for comparing the voltage of a first electric signal output on the D + line by the slave terminal equipment with a first reference voltage of the first comparator to obtain an output result; a processor for determining a level on the D + line in response to the read output result of the first comparator; and the second power supply module is connected with the processor, is connected with the slave terminal equipment through the D-line, and is used for outputting a second electric signal on the D-line if the level on the D + line determined by the processor is high level, wherein the second electric signal enables the level on the D + line to be high level.

In one possible implementation, the voltage of the first electrical signal is greater than a first reference voltage of the first comparator; and the processor is specifically used for reading the output value of the first comparator as a first preset value and determining that the level on the D + line is a high level.

In one possible implementation, the second power supply module is connected to a second comparator of the slave terminal device through a D-line, and a voltage of the second electrical signal is greater than a second reference voltage of the second comparator.

In one possible implementation manner, the second power module stops outputting the second electrical signal on the D-line after a preset time period.

In a seventh aspect, an embodiment of the present application provides a slave terminal device, where the slave terminal device is connected to a master terminal device through an OTG line, the OTG line includes a D + line, a D-line, and a VBUS line, and the slave terminal device includes a processor and a memory, where the processor is coupled to the memory, and the memory is used to store program instructions, and when the program instructions are executed by the slave terminal device, the slave terminal device performs the following steps: outputting a first electrical signal on the D + line in response to the detected power supply signal output by the master terminal device on the VBUS line, the first electrical signal making a level on the D + line a high level; acquiring a level on the D-line in response to the detected second electric signal output by the master terminal device on the D-line; if the level on the D-line is high level, stopping outputting the first electric signal on the D + line, outputting the third electric signal on the D-line, and acquiring the level on the D + line; and if the level on the D + line is low level, determining that the type of the USB port connected with the main terminal equipment through the OTG line is CDP, and charging according to the current magnitude corresponding to the CDP.

In one possible implementation, the D-line is connected to a second comparator in the slave terminal device, and the voltage of the second electrical signal is greater than a second reference voltage of the second comparator; the program instructions, when executed by the slave terminal device, cause the slave terminal device to perform the steps of: and reading a first output value of the second comparator as a first preset value, determining that the level on the D-line is a high level, and confirming that the USB port type is CDP or DCP, wherein the first output value is the result of comparing the voltage of the second electric signal with a second reference voltage by the second comparator.

In one possible implementation, the D + line is connected to a third comparator in the slave terminal device; the program instructions, when executed by the slave terminal device, cause the slave terminal device to perform the steps of: and reading a second output value of the third comparator as a second preset value, and determining that the level on the D + line is a low level.

In one possible implementation, the CDP corresponds to a current of 1.5A.

In an eighth aspect, an embodiment of the present application provides a master terminal device, where the master terminal device is connected to a slave terminal device through an OTG line, the OTG line includes a D + line, a D-line, and a VBUS, the master terminal device includes a processor and a memory, the processor is coupled to the memory, the memory is used to store program instructions, and when the program instructions are executed by the master terminal device, the master terminal device executes the following steps: after the power supply signal is output on the VBUS line, the level on the D + line is obtained in response to the detected first electric signal output by the terminal equipment on the D + line; if the level on the D + line is high, a second electrical signal is output on the D-line, which makes the level on the D + line high.

In one possible implementation, the D + line is connected to a first comparator in the main terminal device, and a voltage of the first electrical signal is greater than a first reference voltage of the first comparator; the program instructions, when executed by the master terminal device, cause the master terminal device to perform the steps of: and reading a first output value of the first comparator as a first preset value, and determining that the level on the D + line is a high level, wherein the first output value is the result of comparing the voltage of the first electric signal with a first reference voltage by the first comparator.

In one possible implementation, the program instructions, when executed by the master terminal device, cause the master terminal device to perform the steps of: and stopping outputting the second electric signal on the D-line after the preset time length.

In a ninth aspect, embodiments of the present application provide a computer-readable medium for storing a computer program comprising instructions for executing the method of the first aspect or any possible implementation manner of the first aspect.

In a tenth aspect, embodiments of the present application provide a computer-readable medium for storing a computer program including instructions for executing the second aspect or the method in any possible implementation manner of the second aspect.

In an eleventh aspect, the present application provides a computer program including instructions for executing the method of the first aspect or any possible implementation manner of the first aspect.

In a twelfth aspect, the present application provides a computer program including instructions for executing the method of the second aspect or any possible implementation manner of the second aspect.

In a thirteenth aspect, an embodiment of the present application provides a chip, which includes a processing circuit and a transceiver pin. Wherein the transceiver pin and the processing circuit are in communication with each other via an internal connection path, and the processing circuit is configured to perform the method of the first aspect or any one of the possible implementations of the first aspect to control the receiving pin to receive signals and to control the sending pin to send signals.

In a fourteenth aspect, an embodiment of the present application provides a chip, where the chip includes a processing circuit and a transceiver pin. Wherein the transceiver pin and the processing circuit are in communication with each other via an internal connection path, and the processing circuit performs the method of the second aspect or any possible implementation manner of the second aspect to control the receiving pin to receive signals and to control the sending pin to send signals.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a schematic diagram of an exemplary application scenario;

fig. 2 is a block diagram of a reverse charging system according to an embodiment of the present disclosure;

FIG. 3 is a schematic illustration of an operation of the present application;

fig. 4 is a schematic internal circuit diagram of a master device and a slave device according to an embodiment of the present disclosure;

fig. 5 is a schematic flowchart of a reverse charging method according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an apparatus according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

Before describing the technical solution of the embodiment of the present application, an application scenario of the embodiment of the present application is first described with reference to the drawings. Referring to fig. 1, a schematic view of an application scenario provided in the embodiment of the present application is shown. The application scenario includes the terminal device 100 and the terminal device 200, and the terminal device (including the terminal 100 and the terminal 200) may include, but is not limited to, a mobile communication device such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer, and a portable device (e.g., a portable computer). The terminal device 100 and The terminal device 200 may be connected by a movable (On-The-Go, OTG) line between different devices.

Referring to fig. 2, fig. 2 is a block diagram of a reverse charging system in an embodiment of the present disclosure, which shows a connection relationship between a terminal device 100 and a terminal device 200 through an OTG line, and referring to fig. 2, an OTG line in the embodiment of the present disclosure includes a Voltage Bus (VBUS), a D + line (which may also be referred to as a data line positive electrode or a data positive signal line), a D-line (which may also be referred to as a data line negative electrode or a data negative signal line), a detection (identification) line (which may also be referred to as a configuration channel (cc) line), and a Ground (GND) line. The D + line and the D-line can be used for data transmission and can also be used for charging.

In this embodiment of the present application, the ID line is used to provide an OTG insertion interrupt signal, and specifically, when the OTG line is inserted into the terminal device 100 and/or the terminal device 200, the device may detect the OTG insertion interrupt signal on the ID line. And the terminal device 100 and the terminal device 200 are also connected through GND for providing a ground signal.

Still referring to fig. 2, the terminal device 100 in the embodiment of the present application includes an AP processor 110, a charging chip power supply module 120, a Universal Serial Bus Physical layer (USB PHY)130, and a battery 140. The AP processor 110, the charging chip power supply module 120 and the USB PHY130 are connected, and the charging chip power supply module 120 is connected to the battery 140, for example, through a bus. In the embodiment of the present application, the connection may include various interfaces, transmission lines, buses, and the like, which is not limited in this embodiment.

The AP processor 110 in the embodiment of the present application may be configured to implement various functions for the terminal, for example, to process a communication protocol and communication data, or to control the entire terminal device, execute a software program, and process data of the software program; or to assist in completing computational processing tasks, such as processing of graphical images or audio, etc.; or the processor 110 may be configured to perform one or more of the functions described above.

The charging chip power supply module 120 in the embodiment of the present application may be configured to output a power supply signal or input a power supply signal. Alternatively, the charging chip power supply module 120 may be configured to output a power supply signal with a specified current and voltage or input a power supply signal with a specified current and voltage based on an instruction of the AP processor 110, where the input is input to a battery, that is, the battery is charged. For example, the following steps are carried out: the AP processor 110 may send an output instruction to the charging chip power supply module 120 to instruct the charging management module to output a power supply signal (e.g., 5V 1.5A), and the charging chip power supply module 120 may output a power supply signal with a voltage value of 5V and a current value of 1.5A based on the output instruction. AP processor 100 may also send an input instruction to charging chip power supply module 120 to instruct the charging management module to input a power supply signal (e.g., 5V 1.5A), and it may also be understood that, no matter how much current is supplied to charging chip power supply module 120 by the external device, charging chip power supply module 120 charges at a current of a specified magnitude only according to the instruction of AP processor 110, that is, inputting a current of a specified magnitude to battery 140. Alternatively, the residual current may be supplied as a system power, for example, a display screen power.

Referring to fig. 2, the charging chip module 120 in the terminal device 100 is connected to the charging chip power supply module 220 in the terminal device 200 through a VBUS line, and a power supply current is transmitted in the VBUS line, that is, if the terminal device 100 is a device for supplying power to the terminal device 200, the charging chip power supply module 120 may provide a power supply signal and input the power supply signal to the charging chip power supply module through the VBUS line.

Referring to fig. 2, the terminal device 100 further includes a USB PHY130, which includes a D + Source Voltage (VDP _ SRC) module 131, a DATA positive signal (DATA PLUS, DP) comparator module 132, a D-Source Voltage (VDM _ SRC) module 133, and a DATA negative signal (DATA MINUS, DM) comparator module 134.

The VDP _ SRC module 131 in this embodiment of the application is connected to the DP comparator module 232 in the terminal device 200 through a D + line. The VDP _ SRC module 131 may be configured to output a VDP _ SRC electrical signal on the D + line.

In the DP comparator block 132 of the embodiment of the application, the DP comparator block 132 is configured to compare the voltage input to the DP comparator block 132 with the reference voltage in the DP comparator block 132 through the D + line and the VDP _ SRC block 231 in the terminal device 200, and output the comparison result. The input voltage of the DP comparator block 132 is equal to the voltage on the D + line.

The principle of the comparator is briefly described below: when the voltage input to the comparator is greater than the reference voltage in the comparator, the output result of the comparator is a first preset value, and the first preset value may be 1, which indicates that the input of the comparator is at a high level. When the voltage input to the comparator is less than the reference voltage in the comparator, the output result of the comparator is a second preset value, and the second preset value may be 0, which indicates that the input of the comparator is at a low level.

In the embodiment of the present application, the VDM _ SRC module 133 is connected to the DM comparator module 234 in the terminal device 200 through a D-line, and the VDM _ SRC module 133 may be configured to output a VDM _ SRC electrical signal on the D-line.

The DM comparator module 134 in this embodiment is connected to the VDM _ SRC module 233 of the terminal device 200 through a D-line, and the DM comparator module 134 is configured to compare the voltage input to the DM comparator module 134 with a reference voltage in the DM comparator module 134 and output a comparison result. Where the input voltage of the DM comparator module 134 is equal to the voltage on the D-line. The operation principle of the DM comparator module 134 is the same as that of the DP comparator module 132, and is not described herein.

The processor 110 in the embodiment of the present application can be used to read the output result of the DP comparator module 132 and/or the DM comparator module 134, and can also be used to control each power module to output a corresponding electrical signal.

Still referring to fig. 2, the terminal device 200 includes an AP processor 210, a charging chip power supply module 220, a USB PHY230, and a battery 240. The AP processor 210, the charging chip power supply module 220 and the USB PHY230 are connected, and the charging chip power supply module 220 is connected to the battery 240. The functions of the AP processor 210 and the charging chip power supply module 220 may refer to the description of the terminal device 100, which is not repeated herein.

The USB PHY230 in the terminal device 200 includes a VDP _ SRC module 231, a DP comparator module 232, a VDM _ SRC module 233, and a DM comparator module 234. The functions of the components in the terminal 200 can refer to the description of the terminal 100, and are not described herein. It should be noted that, for connection relationship between each module in the terminal device 200 and the terminal device 100, reference may be made to description in the terminal device 100, which is not described herein again.

The VDP _ SRC module 231 in this embodiment of the application may be configured to output a VDP _ SRC electrical signal on the D + line.

The DP comparator module 232 in this embodiment of the application can be configured to compare the voltage input to the DP comparator module 232 with a reference voltage in the DP comparator module 232 and output a comparison result. The input voltage of the DP comparator block 232 is equal to the voltage on the D + line. The working principle of the DP comparator block 232 is the same as that of the DP comparator block 132, and is not described herein.

The VDM _ SRC module 233 in this embodiment of the application may be configured to output a VDM _ SRC electrical signal on a D-line.

The DM comparator module 234 in the embodiment of the present application may be configured to compare the voltage input to the DM comparator module 234 with a reference voltage in the DM comparator module 234 and output the comparison result. Where the input voltage of the DM comparator module 234 is equal to the voltage on the D-line. The operation principle of the DM comparator module 234 is the same as that of the DP comparator module 132, and is not described herein.

The processor 210 in the embodiment of the present application may be configured to read the output result of the DP comparator module 232 and/or the DM comparator module 234, and may also be configured to control each power module to output a corresponding electrical signal.

Alternatively, in this application, the connection relationship in fig. 2 indicates that the terminal device 100 is a power supply (or charging) device and may also be referred to as a master device, and the terminal device 200 is a device to be charged and may also be referred to as a slave device.

In order to more clearly explain the technical solutions in the present application, in the following embodiments of the present application, the terminal device 100 is taken as a master device, and the terminal device 200 is taken as a slave device for example, which are described in detail.

Alternatively, the master device 100 and the slave device 200 in the present application may be manually specified by a user. For example, after the master device and the slave device are connected through the OTG line, a user selection interface may be provided on the master device and/or the slave device, so that a user can select the master device and the slave device, as shown in fig. 3.

Optionally, the master device 100 and the slave device 200 may also be determined by attributes of the OTG line, for example, one end of the OTG line is a power supply port for connecting the master device, and the other end of the OTG line is a charging port for connecting the slave device, so that the terminal device may determine that the terminal device is the master device or the slave device by detecting a port type of the OTG line inserted into the port of the terminal device, if the terminal device is determined as the master device, perform reverse charging through the OTG line, that is, supply power to the slave device, and if the terminal device is determined as the slave device, perform forward charging through the OTG line, that is, perform charging through the master device.

The reverse charging method in the embodiment of the present application is described below with reference to fig. 2 as a specific embodiment.

Specifically, the master device 100 and the slave device 200 are connected by an OTG line. In the embodiment of the present application, the AP processor 110 of the master device 100 has program instructions installed therein, and when the program instructions are executed by the AP processor 110, the master device 100 is enabled to execute the technical solution implemented by the master device 100 described in the present application.

Specifically, after the master device 100 and the slave device 200 are connected through the OTG line, the AP processor 110 in the master device 100 detects an OTG insertion interrupt signal, and determines that a connection event exists, specifically, the master device 100 and the external device are connected through the OTG line, for example, the external device may be the slave device 200 in this application. The AP processor 110 may control the charging chip power supply module 120 to output a power supply signal on the VBUS line. As described above, the power supply signal includes the output current and the output voltage, and for example, the current of the power supply signal may be 1.5A and the voltage may be 5V. Illustratively, it can be expressed as a power supply signal (5V 1.5A).

Specifically, the power supply signal output by the charging chip power supply module 120 is input to the charging chip power supply module 220 of the slave device 200 through the VBUS line.

Specifically, after the AP processor 210 of the slave device 200 detects the power supply signal on the VBUS line, the AP processor 210 controls the VDP _ SRC module 231 in the slave device 200 to output VDP _ SRC on the D + line. Specifically, in the embodiment of the present application, after the power supply signal on the VBUS line is input to the charging chip power supply module 220 of the slave device 200, the AP processor 210 of the slave device 200 detects the power supply signal on the VBUS line through the charging chip power supply module 220, determines that a charging event (or also referred to as a connection event) exists, and the slave device 200 enters a first Detection phase (Primary Detection). It should be noted that the output current or the output voltage of the master device 100 on the VBUS line may be referred to as an input current or an input voltage for the slave device 200. It should be further noted that the VDP _ SRC in the present application, for example, the VDP _ SRC output by the master device 100 and/or the VDP _ SRC output by the slave device 200, may be referred to as a VDP _ SRC electrical signal, and the VDP _ SRC electrical signal may include a combination of different currents or voltages. In other embodiments, VDP _ SRC may also be referred to as VDP _ SRC current or VDP _ SRC voltage, for example, VDP _ SRC may be 0.6V voltage, which is not limited in this application.

In the first detection phase, the AP processor 210 in the slave device 200 controls the internal circuit of the VDP _ SRC module 231 to be closed to output VDP _ SRC on the D + line. Specifically, after the internal circuit of the VDP _ SRC module 231 is closed, the VDP _ SRC is output from a D + pin (pin) connected to the D + line, for example, the voltage of the VDP _ SRC output by the VDP _ SRC module 231 may be 0.5V to 0.7V, and for example, in this embodiment, the voltage of the VDP _ SRC is 0.6V, and accordingly, the VDP _ SRC module 231 of the slave device 200 outputs the VDP _ SRC (0.6V voltage) to the D + line of the OTG line through the D + pin, inputs the VDP _ SRC (0.6V voltage) to the D + pin of the master device 100 through the D + pin, and inputs the VDP _ SRC into the DP comparator module 132 of the master device 100 through the D + pin of the master device 100, it can be understood that the voltage of 0.6V on the D + pin of the master device 100, and also can be understood as the voltage on the D + line, which is used as the input voltage of the DP comparator 132 for comparing with the reference voltage in the DP comparator module 132.

Specifically, the DP comparator block 132 of the master device 100 compares the input voltage, i.e., the voltage of VDP _ SRC, with the reference voltage of the DP comparator block 132 and outputs the comparison result. For example, the reference voltage of the DP comparator block 132 may be set to 0.375V.

Specifically, in the embodiment of the present application, the voltage of the VDP _ SRC output by the VDP _ SRC module 231 in the slave device 200 is configured to be greater than the reference voltage in the DP comparator module 132 in the master device 100, so that the voltage of the VDP _ SRC electrical signal is used as the input of the DP comparator module 132, and the voltage of the VDP _ SRC electrical signal is higher than the reference voltage of the DP comparator module 132, and in the embodiment of the present application, the output result of the DP comparator module 132 is 1.

Alternatively, in this embodiment, the master device 100 may wait for a predetermined time period after outputting the power supply signal, and read the output result of the DP comparator module 132 after the predetermined time period is over, so as to detect the electrical configuration on the D + line, for example, the electrical configuration may be a voltage or a level.

Specifically, in the embodiment of the present application, after the predetermined time period is over, the AP processor 110 reads the output result of the DP comparator module 132 as 1, and determines that the input of the DP comparator module 132, i.e. the D + line, is at a high level, which may also be understood as that the D + line is pulled high (or pulled up). It should be noted that the input of the DP comparator 132 is actually the voltage on the D + pin of the host device 100, and in the embodiment of the present application, the D + pin of the host device 100 is connected to the D + line of the OTG line, so that the voltage or level of the D + pin can also be considered to be equal to the voltage or level on the D + line.

The master device 100 then outputs VDM SRC on the D-line. Specifically, in this embodiment, after the AP processor 110 in the master device 100 determines that the D + line is at a high level, the AP processor may control the internal circuit of the VDM _ SRC module 133 in the master device 100 to close, so as to output the VDM _ SRC on the D-line. Specifically, after the internal circuit of the VDM _ SRC module 133 is closed, the VDM _ SRC is output at the D-pin connected to the D-line, and the voltage of the VDM _ SRC output by the VDM _ SRC module 133 may be, for example, 0.5V to 0.7V, and, for example, in the embodiment of the present application, the voltage of VDM _ SRC is 0.6V, and accordingly, the VDM _ SRC module 133 of the main device 100 outputs VDM _ SRC (0.6V voltage) to the D-line of the OTG line through the D-pin, through the D-line, to the D-pin of the slave device 200, and through the D-pin of the slave device 200 to the DM comparator module 234 of the slave device 200, it is understood that the 0.6V voltage on the D-pin of the slave device 200, and also the voltage on the D-line, is used as an input voltage to the DM comparator module 234 for comparison with the reference voltage in the DM comparator module 234.

It should be noted that, the VDM _ SRC according to the present application, for example, the VDM _ SRC output by the master device 100 and/or the VDM _ SRC output by the slave device 200 may be referred to as a VDM _ SRC electrical signal, and the VDM _ SRC electrical signal may include a combination of different currents or voltages. In other embodiments, VDM _ SRC may also be referred to as VDM _ SRC current or VDM _ SRC voltage, for example, VDM _ SRC may be 0.6V voltage, which is not limited in this application.

Specifically, the DM comparator module 234 of the slave device 200 compares with the reference voltage of the DM comparator module 234 based on the input voltage, i.e., the voltage of VDM _ SRC, for example, 0.6V, and outputs the comparison result. For example, the reference voltage of the DM comparator module 234 may be set to 0.375V.

Specifically, in this embodiment of the application, the voltage of the VDM _ SRC output by the VDM _ SRC module 133 of the master device 100 is configured to be greater than the reference voltage in the DM comparator module 234 of the slave device 200, so that the voltage of the VDM _ SRC electrical signal is used as the input of the DM comparator module 234, and the voltage of the VDM _ SRC electrical signal is higher than the reference voltage of the DM comparator module 234, in this embodiment of the application, the output result of the DM comparator module 234 is 1, and specific principles refer to the foregoing, which is not described herein again.

Specifically, reading the output of the DM comparator 234 as 1 from the AP processor 210 of the device 200 determines that the D-line is high, which can also be understood as the D-line being pulled high (or pulled up).

Complying with the BC1.2 protocol requirements, it provides that in the case of a high level on the D-line in the first detection phase, the USB Port type is a Charging Downstream Port (CDP) or a Dedicated Charging Port (DCP), and it can also be understood that the first detection phase is actually to detect whether the USB is an SDP Port or a Charging Port (Charging Port), and if the USB Port is determined to be a Charging Port, it is necessary to further detect the USB Port type, specifically the CDP Port or the DCP Port, through the second detection phase.

In the embodiment of the present application, after the AP processor 210 determines that the D-line is at a high level, the AP processor 210 may determine that the current USB port type is a CDP port or a DCP port, and the first detection phase is completed and enters the second detection phase.

It should be noted that, after the first detection stage is completed, the AP processor 210 controls each component to be restored, including: the internal circuitry of the VDM SRC module 133 is turned off and the DM comparator module 234 is disabled.

Specifically, in the second Detection phase, which may also be referred to as a Secondary Detection phase (Secondary Detection), the AP processor 210 in the slave device 200 controls the internal circuit in the VDM _ SRC block 233 to close to output VDM _ SRC on the D-line and controls the DP comparator block 232 to enable. It should be noted that the specific work flow of each comparator module, including enabling, comparing the output result and stopping enabling, for example, will be described in detail in the following embodiments, and will not be described herein again.

Specifically, since the internal circuit in the VDP _ SRC module 231 is turned off at the end of the first phase, that is, the VDP _ SRC module 231 stops outputting VDP _ SRC on the D + line. Accordingly, the voltage on the D + pin connected to the D + line in the slave device 200 is 0V, and the voltage on the D + pin, which is an input of the DP comparator block 232 in the slave device 200, has a voltage (0V) smaller than the reference voltage of the DP comparator block 232, for example, 0.375V, and thus, the output result of the DP comparator block 232 is 0. Specifically, the AP processor 210 in the slave device 200 may read the output result of the DP comparator block 232 as 0, and determine that the D + line is low, i.e., the D + line is pulled low (or pulled down).

In compliance with the BC1.2 protocol requirements of USB, in the second detection phase, after the AP processor 210 pulls up the D-line to a high level, the D + line is at a low level, which indicates that the D + line and the D-line are not shorted, and the USB port is the CDP port, i.e., the AP processor 210 of the slave device 200 may determine that the current USB port is the CDP port, and the second detection phase is completed.

Specifically, after the AP processor 210 of the slave device 200 determines that the USB port is the CDP port, the current of the input power supply signal corresponding to the CDP port may be determined according to the preset mapping relationship if the USB port is the CDP port. The AP processor 210 sends an input instruction to the charging chip power supply module 220, where the input instruction is used to instruct the charging chip power supply module 220 to control and input a power supply signal with a specified current, and it should be noted that the mapping relationship recorded by the AP processor 210 is a combination of a current and a voltage corresponding to a CDP port specified in the BC1.2 protocol. For example, the CDP port may correspond to a current of 1.5A and a voltage of 5V. In response to the input instruction transmitted from the AP processor 210, the charging chip power supply module 220 inputs a power supply signal having a specified current (1.5A) and voltage (5V) into the battery 240 in the slave device 200, that is, the slave device 200 is charged at a current of 1.5A. It should be noted that the current magnitude described in this application is merely an exemplary example, in other embodiments, when the master device 100 supplies power to the external device by 1.5A, after the slave device 200 recognizes the CDP port, the current magnitude corresponding to the CDP port may be 1A, the AP processor 210 may instruct the charging chip power supply module 220 to charge based on the power supply signal of the current of 1A, and the charging chip power supply module 220 may input the current of 1A to the battery 240 for charging based on the instruction of the AP processor 210, and supply the remaining 500mA current as a system power, for example, to supply power to the display screen.

In summary, in the present application, the program instruction is set in the AP processor of the master device 100, and the AP processor in the master device 100 is controlled by the program instruction to configure the voltage on the D-line to be the high level after detecting that the D + line is the high level, so that when the slave device 200 reads the USB port, the USB port is used as the CDP port to be charged, so as to obtain the current and the voltage corresponding to the CDP port, and further improve the charging efficiency of the slave device 200.

It is understood that the voltage status on the D + and/or D-lines is described herein, and in other embodiments, the AP processor, including the AP processor 110 and the AP processor 210, may determine the status of the USB port by confirming the current status on the D + and/or D-lines, which is not limited herein.

In order to make the technical solutions of the present application better understood, the following describes the technical solutions of the above-mentioned method embodiments in detail with reference to the internal circuit diagrams of the master device 100 and the slave device 200 shown in fig. 4. It should be noted that fig. 4 shows an internal circuit diagram of each module in combination with fig. 2, which is only a schematic example, and actually, the circuit in the terminal device includes, but is not limited to, each component and circuit shown in fig. 4, which is not limited in this application.

With reference to fig. 4, as shown in fig. 5, a flow chart of the reverse charging method in the embodiment of the present application is shown, wherein a left half of fig. 5 is a flow chart of the master device 100 side, and a right half of fig. 5 is a flow chart of the slave device 200 side, specifically:

in step S21, the master device 100 supplies power to the outside.

Specifically, after the master device 100 and the slave device 200 are connected by an OTG line, and after the AP processor 110 of the master device 100 detects an OTG insertion interrupt signal on an ID line, the AP processor 110 sets the power supply mode of the master device 100 to a boost (boost) mode, for example, the boost mode may be that the charging chip power supply module 120 in the master device 100 supplies power to the outside, the output current is 1.5A, and the output voltage is 5V.

In step S22, the master device 100 starts the DP comparator module 132.

Specifically, the AP processor 110 controls the DP comparator module 132 of the master device 100 to start. Specifically, the AP processor 110 may turn on a D-Sink Current (IDM _ SINK) in the DP comparator block 132, and the output Current of the IDM _ SINK may be 25 μ A to 175 μ A, for example. Wherein, the IDM _ SINK is used for preventing the electric signal from drifting.

And, the AP processor 110 controls the DP comparator enable in the DP comparator module 132. Specifically, the AP processor 110 sets the reference voltage of the DP comparator in the DP comparator module 132, illustratively 0.375V, the DP comparator in the DP processor module 132 is enabled, and switch 1 in the DP processor module 132 is closed.

After the AP processor 110 starts the DP comparator module 132, it waits for a predetermined time period, which may be set based on actual requirements, for example: 5 ms. It should be noted that the AP processor 110 sets the predetermined time period to wait for the operation of the slave device 200.

Referring to the right half of fig. 5, i.e. the flow chart of the slave device 200, specifically:

in step S31, the slave device 200 detects the connection of the master device 100.

Specifically, the AP processor 210 of the slave device 200 reads the voltage input of the charging chip power supply module 220, determines the voltage (5V) on the VBUS line, and confirms that there is a charging event (or connection event), i.e., that the slave device 200 is connected to the master device 100.

Optionally, the slave device 200 may perform Data Connection Detection (DCD) detection after detecting the charging event, that is, after connecting to the master device 100, and the specific detection process may refer to the prior art and is not described herein again.

It should be noted that the sequence of step S31 and step S22 is not sequential.

In step S32, the slave device 200 controls the VDP _ SRC module 231 to output VDP _ SRC on the D + line.

Specifically, after the AP processor 210 of the slave device 200 detects the voltage on the VBUS line through the charging chip power supply module 220, it determines that a charging event exists, and the slave device 200 enters the first detection phase. Specifically, the AP processor 210 in the slave device 200 controls the switch 2 in the VDP _ SRC module 231 to be closed, and the VDP _ SRC voltage is input into the DP comparator module 132 of the master device 100 through the D + pin of the slave device 200, the D + line, and the D + pin of the master device 100. For example, in this embodiment, the VDP _ SRC voltage output by the VDP _ SRC module 231 is taken as 0.6V for example.

Specifically, in the present application, after the slave device 200 closes the switch 2, that is, outputs the VDP _ SRC voltage, the IDM _ SINK in the slave device 200 may be opened, and for example, the current provided by the IDM _ SINK is in a range from 25 μ a to 175 μ a, which is not limited in the present application. Next, the AP processor 210 may set a reference voltage of the DM comparator in the DM comparator module 234, which is 0.375V for example. The AP processor 210 enables the DM comparator and switch 3 in the DM comparator module 234 is closed.

Still referring to the left half of fig. 5, i.e. the flowchart of the master device 100, specifically:

in step S23, the master device 100 reads whether the output result of the DP comparator module 132 is 1.

Specifically, after the master device 100 waits for a predetermined time, the AP processor 110 reads the output result of the DP comparator in the DP comparator module 132.

In one possible implementation, as shown in step 32, the VDP _ SRC voltage output from the device 200 is input to the DP comparator block 132 through the D + line, and the DP comparator in the DP comparator block 132 compares the reference voltage (0.375V) with the input voltage, i.e., the voltage (0.6V) on the D + line, and the output result of the DP comparator is 1 because the voltage on the D + line is higher than the reference voltage of the DP comparator. The AP processor 110 reads that the output result of the DP comparator in the DP comparator module 132 is 1, determines that the D + line is high, and performs step S25.

In another possible implementation, if the slave device 200 is a non-to-be-charged device, the slave device 200 does not pull up (or pull up) the D + line in this scenario. The AP processor 110 reads that the output result of the DP comparator in the DP comparator module 132 is 0, determines that the D + line is low, and performs step S24.

Optionally, after reading the output value of the DP comparator, the AP processor 110 of the master device 100 turns off the DP comparator module 132, including: disable DP comparator enable, turn IDP _ INK off, and turn off switch 1 in DP comparator block 132. It is also understood that the AP processor 110 does not read the output result of the DP comparator module 132 after reading the output value of the DP comparator.

In step S24, the master device 100 reads whether the output result of the DM comparator module 134 is 1.

Specifically, the AP processor 110 starts the DM comparator module 134, which includes: IDM _ SINK in DM comparator module 134 is opened, the reference voltage of the DM comparator is set and the DM comparator is enabled, and switch 4 is closed. Optionally, the reference voltage is 0.375V. Subsequently, the AP processor 110 reads the output result of the DM comparator in the DM comparator module 132 after waiting for a predetermined time period, where the predetermined time period may be set according to actual requirements, for example, 10ms, and the application is not limited thereto.

Optionally, if the slave device 200 is a low-speed device such as a keyboard and a mouse, the slave device 200 will pull up the D-line to make the output result of the DM comparator in the DM comparator module 132 be 1, and specific details may refer to the prior art, which is not described in detail herein.

Alternatively, in the case that the host device 100 is plugged into the OTG line and the slave device 200 is not plugged, the AP processor 110 reads that the output result of the DM comparator in the DM comparator module 132 is 0, that is, the D-line is at a low level, and the D + line is configured as a low level, then the AP processor restores the components, and performs step S22 again.

In step S25, the master device 100 controls the VDM _ SRC module 134 to output VDM _ SRC on the D-line.

Specifically, after the AP processor 110 in the master device 100 detects that the output result of the DP comparator module 132 is 1, it determines that the D + line is at a high level. Subsequently, the AP processor 110 controls the switch 5 in the VMD _ SRC module 133 to close, and the VDM _ SRC voltage output by the VDM _ SRC module 134 is input into the DM comparator 234 of the slave device 200 through the D-pin of the master device 100, the D-line, and the D-pin of the slave device 200. For example, in this embodiment, the VDM _ SRC voltage output by the VDM _ SRC module 134 is taken as 0.6V for example.

Optionally, in this application, the AP processor 110 closes 5, and after waiting for the preset time period, opens the switch 5, that is, the AP processor 110 outputs the VDM _ SRC on the D-line within the preset time period, and stops outputting the VDM _ SRC on the D-line after the preset time period is over, so as to restore the circuit in the master device 100. For example, the preset time period may be 100ms, and the application is not limited thereto.

It should be noted that, during the process of executing each step by the master device 100, the master device 100 is always in the boost mode, that is, the charging chip power supply module 120 of the master device 100 executes reverse charging, that is, a power supply signal with a voltage of 5V and a current of 1.5A is output outwards.

Still referring to the right half of fig. 5, i.e. the flow chart of the slave device 200, specifically:

in step S33, the slave device 200 reads whether the output result of the DM comparator module 234 is 1.

Specifically, the output result of the DM comparator module 234 is read from the AP processor 210 in the device 200.

In one possible implementation, if the output result of the DM comparator is 1, that is, the output result of the DM comparator module 234 is 1 by the VDM _ SRC on the D-line, the AP processor 210 determines that the D-line is at a high level, and the AP processor 210 may determine that the USB port is a CDP port or a DCP port. Optionally, after the first detection stage is finished, the AP processor 210 in the slave device 200 controls each component to be restored, including: the DM comparator module 234 is turned off, and switch 2 is opened to stop the output VDP SRC. Wherein the shutdown DM comparator module 234 comprises: stop DM comparator enable, open switch 3, close IDM _ SINK. The slave device 200 enters the second detection phase and performs step S34.

In another possible implementation manner, if the output result is 0, the AP processor 210 determines that the D-line is at a low level, and complies with the BC1.2 protocol requirement of the USB, and if the D-line is at a low level, the AP processor 210 may determine that the type of the USB port is an SDP port, and the AP processor 210 interacts with the master device 100 according to the specification of the standard downlink port, for example, charging is performed at a current of 500mA, that is, a current of 500mA is input to the battery 240, and the remaining current of 1A is used as a system power supply, and the specific interaction process may refer to the prior art, which is not described herein again.

In step S34, the slave device 200 controls the VDM _ SRC module 233 to output VDM _ SRC on the D-line.

Specifically, the slave device 200 executes the second detection phase to further determine whether the USB port is a CDP port or a DCP port, according to the requirements of the BC1.2 protocol.

In the second detection phase, the AP processor 210 enables the VDM _ SRC, i.e. closes the switch 6 in the VDM _ SRC module 233, and the VDM _ SRC voltage output by the VDM _ SRC module 233 is input into the DM comparator 134 of the master device 100 through the D-pin, the D-line, and the D-pin of the master device 100 of the slave device 200. Illustratively, the VDM _ SRC voltage output by the VDM _ SRC module 233 is 0.6V.

In step S35, the slave device 200 reads that the output result of the DP comparator block 232 is 0.

Specifically, the AP processor 210 starts the DP comparator module 232, which includes: opening the IDP _ SINK power supply in the DP comparator block 232, setting the reference voltage of the DP comparator, which may be 0.375V, for example, and enabling the DP comparator, and closing the switch 7.

Specifically, as described above, after the first phase is ended and the switch 2 in the VDP _ SRC module 231 is turned off, the VDP _ SRC module 231 stops outputting the VDP _ SRC voltage. Since the voltage of the VDP _ SRC on the D + line is 0V, the output result of the DP comparator module 232 is 0, and the specific principle is referred to above and is not described herein. The AP processor 210 in the slave device 200 reads that the output of the DP comparator block 232 in the slave device 200 results in 0, confirming a low on the D + line.

It should be noted that, as described above, after reading the output result of the DP processor module 132, the AP processor 110 in the master device 100 stops enabling the DP processor module 132, so that, in this step, after the VDP _ SRC voltage on the D + line becomes 0, since the AP processor 110 does not read the output result of the DP processor module 132 any more, the AP processor does not take other operations.

In step S36, the slave device 200 determines that the USB port is a CDP port, and inputs a current of 1.5A for charging.

Specifically, during the second detection phase, the AP processor 210 closes the switch 6, and the VDM _ SRC module 233 outputs VDM _ SRC on the D-line, that is, the AP processor 210 pulls the D-line high. And if the AP processor 210 detects a low level on the D + line, it may determine that the D-line and the D + line are not shorted, and the AP processor 210 determines that the USB port is a CDP port according to the BC1.2 protocol requirement of the USB.

Optionally, after the second detection phase is finished, and after the AP processor 210 determines that the type of the USB port is the CDP port, the AP processor 210 may send an input instruction to the charging chip power supply module 220 based on a mapping relationship between the CDP port and the input power supply signal, for example, the voltage is 5V and the current is 1.5A, to instruct the charging chip power supply module 220 to input the power supply signal (5V 1.5A), that is, when the AP processor 210 confirms that the USB port is the CDP port, the charging chip power supply module 220 may input the power supply signal, for example, the 1.5A current, transmitted to the slave device 200 through the VBUS line to the battery 240 by the master device 100, specifically, the charging chip power supply module 120 in the master device 100, so that the slave device 200 charges at the charging current of 1.5A.

An apparatus 300 provided by an embodiment of the present application is described below. As shown in fig. 6:

the apparatus 300 includes a processing module 310 and a communication module 320. Optionally, the apparatus 300 further comprises a storage module 330. The processing module 310, the communication module 320 and the memory module 330 are connected by a communication bus.

The communication module 320 may be a device having a transceiving function for communicating with other network devices or a communication network.

The storage module 330 may include one or more memories, which may be one or more devices, circuits, or other devices for storing programs or data.

The memory module 330 may be separate and coupled to the processing module 310 via a communication bus. The memory module may also be integrated with the processing module 310.

The apparatus 300 may be a terminal device in the embodiment of the present application, such as the terminal device 100 or the terminal device 200. Optionally, the communication module 320 of the apparatus 300 may include an antenna and a transceiver of the terminal. Optionally, the communication module 320 may also include an output device and an input device.

The apparatus 300 may be a chip in a terminal device in the embodiment of the present application. The communication module 320 may be an input or output interface, a pin or circuit, or the like. Alternatively, the storage module may store computer-executable instructions of the terminal-side method, so as to enable the terminal device to execute the steps performed by the master device 100 and/or the slave device 200 in the embodiment of the present application.

The storage module 330 may be a register, a cache, or a RAM, etc., and the storage module 330 may be integrated with the processing module 310; the memory module 330 may be a ROM or other type of static storage device that may store static information and instructions, and the memory module 330 may be separate from the processing module 310.

In this embodiment of the present application, the apparatus 300 may be a terminal device or a chip in the terminal device in this embodiment of the present application, and the apparatus 300 may implement the method executed by the master device or the slave device in the foregoing embodiment. Specifically, reference may be made to the related contents in fig. 5, which are not described herein again.

The embodiment of the application provides a reverse charging system, which comprises a main terminal device and a slave terminal device, wherein the main terminal device and the slave terminal device are connected through an OTG (over the go) line; the first power supply module is connected with the third power supply module through a VBUS wire of the OTG wire and used for outputting a power supply signal on the VBUS wire; the fourth power module is connected with the second processor, is connected with the first comparator through a D + line of the OTG line, and is used for responding to the power supply signal on the VBUS line detected by the second processor and outputting a first electric signal on the D + line, wherein the first electric signal enables the level on the D + line to be high level; the first processor is connected with the first comparator and used for responding to a read first output result of the first comparator and determining the level on the D + line, wherein the first output result is the result of the first comparator comparing the voltage on the D + line with a first reference voltage of the first comparator; the second power module is connected with the first processor, is connected with the second comparator through a D-line of the OTG line, and is used for outputting a second electric signal on the D-line if the level on the D + line determined by the first processor is a high level, and the second electric signal enables the level on the D + line to be the high level; the second processor is connected with the second comparator and used for responding to the read second output result of the second comparator and determining the level on the D-line, wherein the second output result is the result of the comparison between the voltage on the D-line and a second reference voltage of the second comparator by the second comparator; if the level on the D + line is high level, the fourth power supply module stops outputting the first electric signal on the D + line; the fifth power supply module is connected with the D-line and used for outputting a third electric signal on the D-line; the second processor is also used for acquiring the level on the D + line; if the level on the D + line is low level, determining that the type of the USB port connected with the main terminal equipment through the OTG line is CDP, and indicating a third power supply module to charge according to the current magnitude corresponding to CDP; and the third power supply module is used for responding to the instruction of the second processor and charging according to the current magnitude corresponding to the CDP.

The embodiment of the application further provides a reverse charging system, which comprises a main terminal device and a slave terminal device connected through an OTG (over the go) line, wherein the slave terminal device comprises a first processor, a first power module, a second power module, a third power module and a first comparator; the main terminal equipment is connected with the first power supply module through a VBUS wire of the OTG wire and used for outputting a power supply signal on the VBUS wire; the second power supply module is connected with the first processor, is connected with the main terminal equipment through a D + line of the OTG line, and is used for responding to a power supply signal on the VBUS line detected by the first processor and outputting a first electric signal on the D + line, wherein the first electric signal enables the level on the D + line to be high level; the main terminal equipment is also used for responding to the detected first electric signal on the D + line and acquiring the level on the D + line; the main terminal equipment is also used for outputting a second electric signal on the D-line if the level on the D + line is high level, and the second electric signal enables the level on the D + line to be high level; the first processor is connected with the first comparator and used for responding to the read first output result of the first comparator and determining the level on the D-line, wherein the first output result is the result of the first comparator comparing the voltage on the D-line with the first reference voltage of the first comparator; if the level on the D + line is high level, the first power supply module stops outputting the first electric signal on the D + line; the third power supply module is connected with the D-line and used for outputting a third electric signal on the D-line; the first processor is also used for acquiring the level on the D + line; if the level on the D + line is low level, determining that the USB port type of the universal serial bus physical layer connected with the main terminal equipment through the OTG line is a charging downstream port CDP, and indicating the first power supply module to charge based on the current size corresponding to the CDP; and the first power supply module is used for responding to the indication of the first processor and charging based on the current magnitude corresponding to the CDP.

The present invention also provides a computer-readable storage medium, which stores a computer program, where the computer program includes at least one code, and the at least one code is executed by a computer to perform the reverse charging method described in the foregoing embodiments.

The embodiment of the present application further provides a computer program, which is used to execute the reverse charging method in the above embodiment when the computer program is executed by a computer.

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A reverse charging system is characterized in that the system comprises a main terminal device and a slave terminal device which are connected through a movable OTG line, wherein the main terminal device comprises a first processor, a first power supply module, a second power supply module and a first comparator, and the slave terminal device comprises a second processor, a third power supply module, a fourth power supply module, a fifth power supply module and a second comparator;

the first power supply module is connected with the third power supply module through a voltage bus VBUS line of the OTG line and used for outputting a power supply signal on the VBUS line;

the fourth power module is connected with the second processor, connected with the first comparator through a data positive signal D + line of the OTG line, and configured to output a first electrical signal on the D + line in response to the power supply signal on the VBUS line detected by the second processor, where the first electrical signal makes a level on the D + line a high level;

the first processor is connected with the first comparator and used for responding to a read first output result of the first comparator and determining the level on the D + line, wherein the first output result is the result of the first comparator comparing the voltage on the D + line with a first reference voltage of the first comparator;

the second power module is connected with the first processor, connected with the second comparator through a data negative signal D-line of the OTG line, and configured to output a second electrical signal on the D-line if the level on the D + line determined by the first processor is a high level, where the second electrical signal makes the level on the D + line a high level;

the second processor is connected with the second comparator and used for responding to a read second output result of the second comparator and determining the level on the D-line, wherein the second output result is the result of the second comparator comparing the voltage on the D-line with a second reference voltage of the second comparator;

if the level on the D + line is a high level, the fourth power supply module stops outputting the first electric signal on the D + line;

the fifth power supply module is connected with the D-line and used for outputting a third electric signal on the D-line;

the second processor is further configured to obtain a level on the D + line; if the level on the D + line is low level, determining that the type of a Universal Serial Bus (USB) port on a physical layer, connected with the main terminal equipment through the OTG line, is a charging downstream port CDP, and indicating the third power supply module to charge according to the current magnitude corresponding to the CDP;

and the third power supply module is used for responding to the instruction of the second processor and charging according to the current magnitude corresponding to the CDP.

2. The system of claim 1, wherein the voltage of the first electrical signal is greater than a first reference voltage of the first comparator;

the first processor determining a level on the D + line in response to the read first output result of the first comparator, including:

and the first processor reads a first output value of the first comparator as a first preset value and determines that the level on the D + line is a high level.

3. The system of claim 1, wherein the voltage of the second electrical signal is greater than a second reference voltage of the second comparator;

the second processor determining a level on the D-line in response to the read second output result of the second comparator, including:

the second processor reads a second output value of the second comparator as a first preset value, determines that the level on the D-line is a high level, and confirms that the USB port type is CDP or DCP.

4. The system of claim 1, wherein the slave terminal device further comprises a third comparator, the third comparator being connected to the D + line;

the second processor obtaining a level on the D + line, comprising:

and the second processor reads a third output value of the third comparator as a second preset value, and determines that the level on the D + line is a low level.

5. The system of claim 1, wherein the CDP corresponds to a current of 1.5A.

6. The slave terminal equipment is characterized in that the slave terminal equipment is connected with a master terminal equipment through an OTG (over the top) line, the OTG line comprises a D + line, a D-line and a VBUS (visual basic unit) line, and the slave terminal equipment comprises a processor, a first power supply module, a second power supply module, a third power supply module and a first comparator;

the first power supply module is connected with the main terminal equipment through the VBUS line and used for receiving a power supply signal output by the main terminal equipment on the VBUS line;

the second power module is connected with the processor, connected with the main terminal device through the D + line, and configured to output a first electrical signal on the D + line in response to the power supply signal received by the first power module detected by the processor, where the first electrical signal makes a level on the D + line a high level;

the first comparator is connected with the processor, the main terminal equipment through the D-line, and the first comparator is used for comparing the voltage of a second electric signal output on the D-line based on the main terminal equipment with a first reference voltage of the first comparator to obtain a first output result;

the processor is used for responding to the read first output result of the first comparator and determining the level on the D-line;

if the level on the D-line determined by the processor is a high level, the second power module stops outputting the first electric signal on the D + line;

the third power supply module is connected with the D-line and used for outputting a third electric signal on the D-line;

the processor is further configured to obtain a level on the D + line; if the level on the D + line is low level, determining that the type of a USB port connected with the main terminal equipment through the OTG line is CDP, and indicating the first power supply module to charge according to the current magnitude corresponding to CDP;

the first power module is used for responding to the indication of the processor and charging according to the current magnitude corresponding to the CDP.

7. The terminal device of claim 6, wherein the second power module is connected to a second comparator of the master terminal device via the D + line, and wherein the voltage of the first electrical signal is greater than a second reference voltage of the second comparator.

8. The terminal device of claim 6, wherein the voltage of the second electrical signal is greater than the first reference voltage of the first comparator;

the processor is specifically configured to read that a first output value of the first comparator is a first preset value, determine that a level on the D-line is a high level, and confirm that the USB port type is CDP or DCP.

9. The terminal device of claim 6, wherein the slave terminal device further comprises a third comparator, the third comparator being connected to the D + line;

the processor is specifically configured to read a second output value of the third comparator as a second preset value, and determine that the level on the D + line is a low level.

10. The terminal device of claim 1, wherein the CDP corresponds to a current of 1.5A.

11. The main terminal equipment is characterized in that the main terminal equipment is connected with the auxiliary terminal equipment through an OTG (over the top) line, the OTG line comprises a D + line, a D-line and a VBUS (visual basic unit) line, and the main terminal equipment comprises a processor, a first power supply module, a second power supply module and a first comparator;

the first power supply module is connected with the slave terminal equipment through the VBUS wire and used for outputting a power supply signal on the VBUS wire;

the first comparator is connected with the processor, connected with the slave terminal equipment through the D + line, and used for comparing the voltage of a first electric signal output on the D + line by the slave terminal equipment with a first reference voltage of the first comparator to obtain an output result;

the processor is used for responding to the read output result of the first comparator and determining the level on the D + line;

the second power module is connected with the processor, connected with the slave terminal device through the D-line, and configured to output a second electrical signal on the D-line if the level on the D + line determined by the processor is a high level, where the second electrical signal makes the level on the D + line a high level.

12. The terminal device of claim 11, wherein the voltage of the first electrical signal is greater than a first reference voltage of the first comparator;

the processor is specifically configured to read that an output value of the first comparator is a first preset value, and determine that a level on the D + line is a high level.

13. The terminal device of claim 11, wherein the second power module is connected to a second comparator of the slave terminal device via the D-line, and wherein the voltage of the second electrical signal is greater than a second reference voltage of the second comparator.

14. The terminal device of claim 11, wherein the second power module stops outputting the second electrical signal on the D-line after a preset duration.

15. A reverse charging method is applied to a slave terminal device, the slave terminal device is connected with a master terminal device through an OTG line, the OTG line comprises a D + line, a D-line and a VBUS line, and the method comprises the following steps:

the slave terminal device outputs a first electric signal on the D + line in response to the detected power supply signal output by the master terminal device on the VBUS line, wherein the first electric signal enables the level on the D + line to be high level;

the slave terminal equipment responds to the detected second electric signal output by the master terminal equipment on the D-line to acquire the level on the D-line;

if the level on the D-line is high level, the slave terminal equipment stops outputting the first electric signal on the D + line, outputs a third electric signal on the D-line and acquires the level on the D + line;

and if the level on the D + line is low level, the slave terminal equipment determines that the type of the USB port connected with the master terminal equipment through the OTG line is CDP, and charges according to the current magnitude corresponding to the CDP.

16. The method of claim 15, wherein the D + line is connected to a first comparator in the master terminal device, and wherein the voltage of the first electrical signal is greater than a first reference voltage of the first comparator.

17. The method of claim 15, wherein the D-line is connected to a second comparator in the slave terminal device, and wherein the voltage of the second electrical signal is greater than a second reference voltage of the second comparator;

the obtaining the level on the D-line includes:

and the slave terminal device reads that a first output value of the second comparator is a first preset value, determines that the level on the D-line is a high level, and confirms that the USB port type is CDP or DCP, wherein the first output value is the result of comparing the voltage of the second electric signal with the second reference voltage by the second comparator.

18. The method of claim 15, wherein the D + line is connected to a third comparator in the slave terminal device;

the acquiring the level on the D + line includes:

and the slave terminal equipment reads a second output value of the third comparator as a second preset value, and determines that the level on the D + line is a low level.

19. The method of claim 15, wherein the CDP corresponds to a current of 1.5A.

20. A reverse charging method is applied to a master terminal device, the master terminal device is connected with a slave terminal device through an OTG (over the air) line, the OTG line comprises a D + line, a D-line and a VBUS (visual basic unit), and the method comprises the following steps:

after the master terminal equipment outputs a power supply signal on the VBUS line, responding to a detected first electric signal output by the slave terminal equipment on the D + line, and acquiring the level on the D + line;

and if the level on the D + line is high level, the main terminal equipment outputs a second electric signal on the D-line, and the second electric signal enables the level on the D + line to be high level.

21. The method of claim 20, wherein the D + line is connected to a first comparator in the master terminal device, and wherein the voltage of the first electrical signal is greater than a first reference voltage of the first comparator;

the acquiring the level on the D + line includes:

and the master terminal equipment reads a first output value of the first comparator as a first preset value, and determines that the level on the D + line is a high level, wherein the first output value is a result of comparing the voltage of the first electric signal with the first reference voltage by the first comparator.

22. The method of claim 20, further comprising:

and the main terminal equipment stops outputting the second electric signal on the D-line after the preset time length.

23. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, which is executed by a terminal device to control the terminal device to perform the method of any one of claims 15 to 19.

24. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, which is executed by a terminal device to control the terminal device to perform the method of any one of claims 20 to 22.