CN113158604A - Time sequence analysis method and device based on physical routing division, equipment and medium - Google Patents

Time sequence analysis method and device based on physical routing division, equipment and medium Download PDF

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CN113158604A
CN113158604A CN202110482164.2A CN202110482164A CN113158604A CN 113158604 A CN113158604 A CN 113158604A CN 202110482164 A CN202110482164 A CN 202110482164A CN 113158604 A CN113158604 A CN 113158604A
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clock
physical
path
clock delay
delay data
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CN113158604B (en
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赵凯
杜华斌
王鑫鑫
周彪
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Haiguang Information Technology Co Ltd
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Haiguang Information Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure provides a timing analysis method and apparatus, device and medium based on physical trace division, the method includes: acquiring a clock path structure based on the gate-level netlist, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock terminal units; carrying out physical routing division on the clock interconnection line to obtain a plurality of physical sub-nodes and physical sub-line segments so as to obtain physical connection relation data; generating clock delay data respectively corresponding to a plurality of physical branch segments and physical branch nodes through simulation based on the physical connection relation data and the logic connection data included in the gate-level netlist; based on the clock delay data of the common physical segment and the common physical segment node, an overly pessimistic amount generated by the common physical path is removed to obtain clock delay data of the clock path structure. The method can remove the excessive pessimistic quantity generated by the common physical path, reduce the clock deviation and improve the accuracy of the time sequence convergence.

Description

Time sequence analysis method and device based on physical routing division, equipment and medium
Technical Field
The embodiment of the disclosure relates to a time sequence analysis method and device based on physical routing division, equipment and a medium.
Background
The digital integrated circuit is divided into a front-end design stage and a rear-end design stage according to a design flow, the front-end design stage completes the top-layer framework selection and the main function module division of a circuit system according to user requirements and product function index definitions, the circuit design is completed through a high-level circuit modeling language, and the circuit logic synthesis is completed through an integrated circuit front-end design tool and in combination with the design constraint on the circuit, so that a gate-level netlist is obtained. Besides code design, the front-end design also needs to complete behavior-level verification and gate-level verification of codes, and complete testability design, power consumption control optimization and the like of a circuit according to requirements.
The back-end design of the integrated circuit is also called as physical design, and the layout and wiring of the circuit are completed based on a gate-level netlist obtained by front-end design, the circuit layout is realized, and the verification of the layout is completed. For example, back-end (physical) design is a process of creating a representation of a physical circuit corresponding to a netlist, and the design result needs to satisfy: first, various limitations of chip processing; second, acceptable design cycles; thirdly, the result verification and simulation after layout design need to meet the requirements (such as time sequence) on design performance indexes.
Back-end (physical) design can be considered as a physical representation (topology) of a circuit netlist, i.e., a complex set of structures composed of transistors, interconnections, and other circuit basic units built and connected on a chip. Major variables for backend design include, but are not limited to: how to solve the time delay problem of the interconnection line of the chip and a method for controlling the time delay of the interconnection line. The time delay of the interconnection lines has become an important factor affecting the performance of the chip.
Disclosure of Invention
At least one embodiment of the present disclosure provides a time sequence analysis method based on physical trace division, including: acquiring a clock path structure to be analyzed based on a gate-level netlist for integrated circuit design, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock terminal units, and the target clock driving unit and the at least two target clock terminal units are connected through the clock interconnection line; performing physical routing division on the clock interconnection line to obtain a plurality of physical branch nodes and a plurality of physical branch lines spaced by the plurality of physical branch nodes, so as to obtain physical connection relation data between the target clock driving unit and the at least two target clock end point units, wherein the plurality of physical branch lines and the plurality of physical branch nodes respectively include a common physical branch line and a common physical branch node corresponding to a common physical path of the at least two target clock end point units; generating clock delay data respectively corresponding to the plurality of physical line segments and the plurality of physical branch nodes through simulation based on the physical connection relation data and the logic connection data included in the gate-level netlist; removing an amount of excess pessimism generated by the common physical path based on the clock delay data for the common physical segment and the common physical segment node to obtain the clock delay data for the clock path structure.
For example, in a timing analysis method provided in at least one embodiment of the present disclosure, the target clock driving unit includes: one or more clock driver units of a plurality of clock driver units connected in series and/or in parallel.
For example, in a timing analysis method provided in at least one embodiment of the present disclosure, generating, through simulation, clock delay data respectively corresponding to the plurality of physical segment lines and the plurality of physical segment nodes includes: respectively extracting parasitic resistance data and parasitic capacitance data of the physical branch segments, and parasitic resistance data and parasitic capacitance data of the physical branch nodes to obtain parasitic parameter data; and generating clock delay data respectively corresponding to the plurality of physical branch segments and the plurality of physical branch nodes by simulation under different excitations based on the logic connection line data, the physical connection relation data and the parasitic parameter data.
For example, in a timing analysis method provided in at least one embodiment of the present disclosure, the different stimuli include: the input signal from low level to high level when based on different signal transition times, or the input signal from high level to low level when based on different signal transition times.
For example, in a timing analysis method provided by at least one embodiment of the present disclosure, based on the clock delay data of the common physical segment and the common physical segment node, removing an excessive pessimistic amount P generated by the common physical path to obtain the clock delay data of the clock path structure, the method includes: acquiring the logic connection data, the physical connection relation data and clock delay data which are generated by simulation and respectively correspond to the plurality of physical line segments and the plurality of physical nodes; according to the different stimuli, based on the logic connection data and the physical connection relation data, clock delay data corresponding to the common physical path is obtained through calculation by utilizing the clock delay data of the common physical line segment and the common physical node; obtaining the amount of excess pessimism P based on clock delay data corresponding to the common physical path; obtaining the clock delay data of the clock path structure by removing the over pessimistic amount P.
For example, in a timing analysis method provided in at least one embodiment of the present disclosure, the calculating clock delay data corresponding to the common physical path using the clock delay data of the common physical segment and the common physical segment node includes: multiplying the clock delay data corresponding to each of the common physical line segments of the common physical path by the corresponding scaling factor to obtain a first clock delay result D1; multiplying the clock delay data of each common physical branch node corresponding to the common physical path by the corresponding increase and decrease factor to obtain a second clock delay result D2; summing each of the first clock delay results D1 and each of the second clock delay results D2 to obtain clock delay data corresponding to the common physical path.
For example, in a timing analysis method provided in at least one embodiment of the present disclosure, the calculating clock delay data corresponding to the common physical path using the clock delay data of the common physical segment and the common physical segment node includes: obtaining first clock delay data D01 by summing each third clock delay result D3 obtained by multiplying clock delay data corresponding to each of the common physical segment of the common physical path by an increasing or decreasing factor corresponding to when a path is accepted, and each fourth clock delay result D4 obtained by multiplying clock delay data corresponding to each of the common physical segment nodes of the common physical path by an increasing or decreasing factor corresponding to when a path is accepted, wherein the first clock delay data D01 represents clock delay data corresponding to the common physical path when the path is accepted, and the accepted path is at least a portion of a clock interconnection between the target clock driving unit and a first one of the at least two target clock end units; and summing each fifth clock delay result D5 obtained by multiplying the clock delay data corresponding to each of the common physical segment of the common physical path by the corresponding increase and decrease factor for the transmit path, and each sixth clock delay result D6 obtained by multiplying the clock delay data corresponding to each of the common physical segment nodes of the common physical path by the corresponding increase and decrease factor for the transmit path, to obtain second clock delay data D02, wherein the second clock delay data D02 represents the clock delay data corresponding to the common physical path for the transmit path, and the transmit path is at least a portion of a clock interconnection between the target clock driving unit and a second one of the at least two target clock end units.
For example, in a timing analysis method provided in at least one embodiment of the present disclosure, for each common physical segment and each common physical node corresponding to the common physical path, the increase and decrease factors corresponding to the accepting of the path are the same; and/or, for each common physical line segment corresponding to the common physical path and each common physical node, the increase and decrease factors corresponding to the transmission path are the same.
For example, in a timing analysis method provided in at least one embodiment of the present disclosure, obtaining the excessive pessimistic amount P based on clock delay data corresponding to the common physical path includes: a difference obtained by subtracting the first clock delay data D01 and the second clock delay data D02 is taken as an excessive pessimistic amount P corresponding to the common physical path.
For example, in a timing analysis method provided by at least one embodiment of the present disclosure, the obtaining the clock delay data of the clock path structure by removing the over-pessimistic amount P includes: obtaining third clock delay data D03 for the accept path and fourth clock delay data D04 for the transmit path; configuring clock delay data of the clock path structure equal to: the third clock delay data D03- (the fourth clock delay data D04-the over-pessimistic amount P); wherein the third clock delay data D03 of the acceptance path is obtained by summing each seventh clock delay result D7 obtained by multiplying the clock delay data corresponding to each of the physical segment lines of the acceptance path by the corresponding increase and decrease factor for the acceptance path, and each eighth clock delay result D8 obtained by multiplying the clock delay data corresponding to each of the physical segment nodes of the acceptance path by the corresponding increase and decrease factor for the acceptance path; and summing every ninth clock delay result D9 obtained by multiplying the clock delay data corresponding to every physical branch segment of the transmission path by the corresponding increase and decrease factor used for the transmission path, and every tenth clock delay result D10 obtained by multiplying the clock delay data corresponding to every physical branch node of the transmission path by the corresponding increase and decrease factor used for the transmission path, so as to obtain fourth clock delay data D04 of the transmission path.
For example, in a timing analysis method provided in at least one embodiment of the present disclosure, for each physical segment and each physical node corresponding to the receiving path, the increase and decrease factors corresponding to the receiving path are the same; and/or for each physical branch segment corresponding to the transmission path and each physical branch node, the corresponding increase and decrease factors are the same when the increase and decrease factors are used for the transmission path.
At least one embodiment of the present disclosure provides a timing analysis device based on physical routing partitioning, including: the receiving module is configured to acquire a clock path structure to be analyzed based on a gate-level netlist for integrated circuit design, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock terminal units, and the target clock driving unit and the at least two target clock terminal units are connected through the clock interconnection line; a physical trace splitting module configured to: performing physical routing division on the clock interconnection line to obtain a plurality of physical branch nodes and a plurality of physical branch lines spaced by the plurality of physical branch nodes, so as to obtain physical connection relation data between the target clock driving unit and the at least two target clock end point units, wherein the plurality of physical branch lines and the plurality of physical branch nodes respectively include a common physical branch line and a common physical branch node corresponding to a common physical path of the at least two target clock end point units; a simulation module configured to: generating clock delay data respectively corresponding to the plurality of physical line segments and the plurality of physical branch nodes through simulation based on the physical connection relation data and the logic connection data included in the gate-level netlist; a timing calculation module configured to: removing an amount of excess pessimism generated by the common physical path based on the clock delay data for the common physical segment and the common physical segment node to obtain the clock delay data for the clock path structure.
At least one embodiment of the present disclosure also provides an electronic device, including: a processor and a memory, wherein the memory has stored thereon a computer executable program which, when executed by the processor, implements a timing analysis method as described in any one of the above.
At least one embodiment of the present disclosure further provides a computer-readable storage medium, in which a computer-executable program is stored, and when the computer-executable program is executed by a processor, the method for timing analysis as described in any one of the above is implemented.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a clock path architecture;
fig. 2 is a flowchart of a timing analysis method based on physical trace partitioning according to some embodiments of the present disclosure;
FIG. 3 is a schematic diagram of a clock path structure A100 according to some embodiments of the present disclosure;
FIG. 4 is a schematic diagram of a clock path structure according to further embodiments of the present disclosure;
FIG. 5 is a flow diagram of a method for simulating generation of clock delay data for a plurality of physical segment nodes and a plurality of physical segment nodes according to some embodiments of the present disclosure;
FIG. 6 is a flow diagram for obtaining clock delay data for a clock path structure by removing an overly pessimistic amount generated by a common physical path according to some embodiments of the present disclosure;
FIG. 7 is a flow chart for computing clock delay data corresponding to a common physical path using clock delay data of a common physical segment and a common physical segment node according to some embodiments of the present disclosure;
FIG. 8 is a flow chart for computing clock delay data corresponding to a common physical path using clock delay data of a common physical segment and a common physical segment node according to yet further embodiments of the present disclosure;
FIG. 9 is a flow chart for obtaining clock delay data for a clock path structure by removing an overly pessimistic amount provided by further embodiments of the present disclosure;
fig. 10 is a schematic block diagram of a timing analysis apparatus based on physical trace division according to some embodiments of the present disclosure; and
fig. 11 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The use of the terms "a" and "an" or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flow charts are used in the disclosed embodiments to illustrate the steps of a method according to an embodiment of the disclosure. It should be understood that the preceding and following steps are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or steps may be removed from the processes.
The inventor researches and discovers that for completely same logic units On the same integrated circuit Chip, the process deviation is caused by different positions, so that the timing delay is different, namely, On-Chip Variation (OCV). In order to calculate such a deviation, the timing calculation tool uses different increase and decrease factors (derates) when calculating the delays of the Clock transmission path and the Clock reception path, and when the transmission path and the reception path have a common path, it is necessary to remove an excessive pessimistic amount caused by different calculation methods of the transmission path and the reception path, which is called Clock convergence Pessimism Removal (CRPR), that is, the excessive pessimistic amount of the Clock is a deviation caused by using different increase and decrease factors when the transmission path and the reception path respectively use different increase and decrease factors to calculate the path delay and when the two paths have corresponding common physical paths.
FIG. 1 is a diagram of a clock path architecture. For example, as shown in fig. 1, the clock path structure includes a first clock driving unit 401, a second clock driving unit 402, and a third clock driving unit 403, and a first clock end point unit 501, a second clock end point unit 502, and a third clock end point unit 503. The clock path structure also includes clock interconnect lines, such as lines 300, 301, 302, and 303, for connecting the clock driver units and the clock destination units. 100, 101, 102, 103, 104, 105 shown in fig. 1 are physical line segments of a connection 303, respectively, the connections 300, 301, 302 are a concept of a path in a logical sense, and the connection 303 is also a connection in a logical sense, i.e. an arrow of the connection 303 in fig. 1 is only an indication of an abstract sense.
For example, in the example of fig. 1, there is a timing check between any two of the first clock end point unit 501, the second clock end point unit 502, and the third clock end point unit 503, which may be determined according to actual situations and is not limited thereto. For example, there is a timing check between the first clock end point unit 501 and the third clock end point unit 503, and if the first clock end point unit 501 is the clock end point unit corresponding to the transmission path, the third clock end point unit 503 is the clock end point unit corresponding to the reception path. The path taken by the clock 601(clock) to the first clock endpoint unit 501 is in turn: 300. 401, 301, 402, 302, 403, and 303. The paths traversed by clocks 601 to 503 are, in order: 300. 401, 301, 402, 302, 403, and 303, respectively, are associated with the physical line segments 100, 102, 104, and 105.
For example, the delay (delay1) from the clock 601 to the first clock endpoint unit 501 is calculated as: the respective delays from 300, 401, 301, 402, 302, 403, and 303 to the first clock end point unit 501 are multiplied by the respective increase and decrease factors to obtain respective sum values, and finally the sum values are added to obtain a first delay (delay 1). The delay (delay2) from the clock 601 to the third clock end point unit 503 is calculated as follows: the respective delays 300, 401, 301, 402, 302, 403, 303 to the third clock end point unit 503 are multiplied by the respective corresponding increase and decrease factors to obtain respective sum values, and finally the sum values are added to obtain a second delay (delay 2). As one of the clock delay data of the clock path structure, for example, a difference (Skew) of clock delays of the first clock end unit 501 and the third clock end unit 503 is equal to a first delay (delay1) minus a second delay (delay 2).
Since the clock 601 to the first clock end point unit 501 and the clock 601 to the third clock end point unit 503 respectively use different increasing and decreasing factors in consideration of the on-chip error, the clock convergence pessimistic elimination (CRPR) can remove the deviations of the common paths 300, 401, 301, 402, 302 and 403 in the logic sense due to the on-chip error using the different increasing and decreasing factors. However, the logic path 303 from the clock 601 to the first clock end point unit 501 and the third clock end point unit 503 respectively has a common physical path (e.g. including a common physical line segment 100), the physical line segment 100 adopts different increasing and decreasing factors due to on-chip errors to cause the delay offset, and the above pessimistic clock convergence removal (CRPR) does not remove the offset. If the first clock end point unit 501, the second clock end point unit 502, and the third clock end point unit 503 have timing checks with each other, and if the common physical path corresponding to the clock interconnection line (also called clock routing) is not considered, the following problems exist in practical application:
for example, the common physical path (e.g., including the common physical line segment 100) of the first clock end point unit 501 and the third clock end point unit 503 shown in fig. 1 results in an excessively pessimistic amount due to the on-chip error using different scaling factors; for another example, the common physical path (e.g., including the common physical line segments 100 and 102) of the second clock end point unit 502 and the third clock end point unit 503 shown in fig. 1 may cause an excessively pessimistic amount due to the on-chip error using different increasing and decreasing factors; for another example, the common physical path (e.g., including the common physical line segment 100) of the first clock end point unit 501 and the second clock end point unit 502 shown in fig. 1 may result in an excessively pessimistic amount due to the on-chip error using different scaling factors.
At least one embodiment of the present disclosure provides a time sequence analysis method based on physical trace division, including:
acquiring a clock path structure to be analyzed based on a gate-level netlist for integrated circuit design, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock terminal units, and the target clock driving unit and the at least two target clock terminal units are connected through the clock interconnection line;
the method comprises the steps of performing physical routing division on a clock interconnection line to obtain a plurality of physical sub-nodes and a plurality of physical sub-lines separated by the physical sub-nodes so as to obtain physical connection relation data between a target clock driving unit and at least two target clock terminal units, wherein the physical sub-nodes of the physical sub-lines respectively comprise a common physical sub-line and a common physical sub-node corresponding to a common physical path of the at least two target clock terminal units;
generating clock delay data respectively corresponding to a plurality of physical branch segments and a plurality of physical branch nodes through simulation based on the physical connection relation data and the logic connection data included in the gate-level netlist;
based on the clock delay data of the common physical segment and the common physical segment node, an overly pessimistic amount generated by the common physical path is removed to obtain clock delay data of the clock path structure.
At least one embodiment of the present disclosure further provides a device corresponding to the timing analysis method.
The timing analysis method or the timing analysis device according to the embodiment of the disclosure can remove excessive pessimism generated by a common physical path based on physical routing division of the clock interconnection line to obtain clock delay data of a clock path structure, reduce clock skew, and improve accuracy of timing convergence.
Fig. 2 is a flowchart of a timing analysis method based on physical trace division according to some embodiments of the present disclosure. For example, as shown in fig. 2, the timing analysis method provided in at least one embodiment of the present disclosure includes steps S1 to S4.
And step S1, acquiring a clock path structure to be analyzed based on the gate-level netlist for the integrated circuit design, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock terminal units, and the target clock driving unit and the at least two target clock terminal units are connected through the clock interconnection line.
Step S2, perform physical routing division on the clock interconnection line to obtain a plurality of physical branch nodes and a plurality of physical branch lines spaced by the plurality of physical branch nodes, so as to obtain data of a physical connection relationship between the target clock driving unit and the at least two target clock end point units, where the plurality of physical branch lines and the plurality of physical branch nodes respectively include a common physical branch line and a common physical branch node corresponding to a common physical path of the at least two target clock end point units.
And step S3, generating clock delay data respectively corresponding to the plurality of physical branch segments and the plurality of physical branch nodes through simulation based on the physical connection relation data and the logic connection data included in the gate-level netlist.
Step S4, removing an excessive pessimistic amount generated by the common physical path based on the clock delay data of the common physical segment and the common physical segment node to obtain the clock delay data of the clock path structure.
Fig. 3 is a schematic diagram of a clock path structure a100 according to some embodiments of the present disclosure. Fig. 4 is a schematic diagram of a clock path structure according to still other embodiments of the disclosure.
As shown in fig. 3, the clock path structure a100 to be analyzed includes a clock interconnection line (e.g., the connection line 303) and a target clock driving unit (e.g., the clock driving unit 403) and at least two target clock end units (e.g., any two of the target clock end units 501, 502, and 503) connected through the clock interconnection line (e.g., the connection line 303). It should be noted that the clock path structure a10 is a logical concept and not a physical concept, and the connection 303 is a logical connection, that is, the arrow of the connection 303 in fig. 3 is only an indication of an abstract meaning, and is not limited to fig. 3. This means that the connection 303 includes, in physical implementation, nodes in a physical sense (e.g., 200, 201, 202, 203, 204, 205, and 206) and segments in a physical sense (e.g., 100, 101, 102, 103, 104, and 105), as described with particular reference to the following.
For example, in some examples, the target clock driver unit includes at least one of a plurality of clock driver units connected in series with each other. For example, the target clock driving unit is one of the clock driving unit 403 and the clock driving unit 402 in fig. 4, for example, the target clock driving unit is the clock driving unit 403 in fig. 4. Of course, the target clock driving unit may also be the clock driving unit 402 in fig. 4, for example, when the inventor researches that paths from the clock driving unit 402 to the target clock end point unit 501 and another target clock end point unit (not shown, for example, denoted as a fourth target clock end point unit) are taken as a transmitting path and a receiving path (that is, a common physical path exists between the target clock end point unit 501 and the fourth target clock end point unit), the clock driving unit 402 is taken as the target clock driving unit, and details are not described herein. It should be noted that the meaning of the physical path in the embodiment of the present disclosure may be understood as a physical trace in the chip.
For another example, in some examples, the target clock drive unit may also include at least one of a plurality of clock drive units (not shown) connected in parallel. Therefore, the embodiments of the present disclosure do not limit the positions, the numbers, and the like of the target clock driving units, and the specific requirements are determined according to different processes and items, which are not described herein again.
For example, in some examples, the at least two target clock end point units refer to at least two clock end point units in which timing check exists, and specifically, which clock end point units, and embodiments of the present disclosure are not limited thereto, and may specifically need to be adjusted according to different processes and projects.
For example, in some examples, the at least two clock destination units include one clock destination unit for the transmit path and one clock destination unit for the receive path, e.g., the two target clock destination units are any two of the clock destination units 501, 502, and 503 of fig. 3 and 4. For example, in some examples, each clock end point unit includes a register and a latch, that is, a timing check existing between two target clock end point units may also be understood as a timing check between two different registers, and therefore, in view of this fact, the timing check is not a key point in the description of the embodiments of the present disclosure, and in order to ensure clarity and conciseness, the detailed description is not repeated here.
It should be noted that each of the clock driving units included in the clock path structure may correspond to one clock end point unit, or each of the clock driving units included in the clock path structure may correspond to a plurality of clock end point units.
Next, on the basis of the clock path structure illustrated in fig. 3, a timing analysis method based on physical trace division is further described, but embodiments of the present disclosure do not limit a specific form of the clock path structure, and a timing analysis method based on other forms of clock path structures is not described herein again.
For example, in some examples, for step S1, in the related process of the integrated circuit, the gate-level netlist is used to describe the circuit element interconnection relationship, such as the gate-level netlist is a text file, and the front-end design of the integrated circuit aims to obtain the gate-level netlist to provide some necessary files for the back-end design. Since the gate-level netlist is not the focus of the description of the embodiments of the present disclosure, in order to ensure the clarity and conciseness of the description of the embodiments of the present disclosure, the embodiments of the present disclosure are not described herein again.
For example, in some examples, for step S2, according to actual needs, a clock interconnection line (e.g., the connection line 303) in the clock path structure a100 for connecting the target clock driving unit (e.g., the clock driving unit 403) and the target clock destination unit (e.g., any two of the clock destination units 501, 502, and 503) is physically routed and divided to obtain a plurality of physical division nodes and a plurality of physical division lines spaced by the plurality of physical division nodes, so as to obtain physical connection relationship data between the target clock driving unit and the target clock destination unit, that is, obtain corresponding physical division lines and physical connection relationship data corresponding to the physical division nodes, as shown in fig. 3, for example, the divided physical division nodes include at least a part of the physical division nodes 200, 201, 202, 203, 204, 205, and 206, and the divided physical division lines include the physical division line 100, 101. 102, 103, 104, 105.
For example, the specific physical trace dividing manner includes: the physical jumper is used as a standard, physical routing before and after the jumper is physical branch segments (for example, segments made of different metals), and a through hole (Via) used by the jumper is marked as a physical branch node, for example, the through hole is used for electrically connecting lines in different conductive layers in an integrated circuit, so that the physical jumper can be used for realizing higher-integration-level wiring. Of course, this is merely exemplary and not a limitation of the present disclosure.
For example, for physical connection relationship data, the following is exemplified: the physical connection relationship between the clock driving unit 403 and the clock end point unit 501 in fig. 3 is the clock driving unit 403, the physical branch point 200, the physical branch segment 100, the physical branch point 201, the physical branch segment 101, the physical branch point 202, and the clock end point unit 501 in sequence. Of course, this is merely exemplary and not a limitation of the present disclosure, and the physical connection relationship in other cases is not described herein again.
For example, in some examples, for step S2, when the target clock drive unit is clock drive unit 403 and the target clock end units are clock end units 501 and 502, the common physical path is path 100a, as shown in fig. 3, and thus the physical segment and physical node that result after the physical trace division includes common physical segment 100 and common physical nodes 200 and 201 corresponding to common physical path 100 a. Of course, this is merely exemplary and not a limitation of the present disclosure, and the common physical path in other cases is not described herein again.
For example, in some examples, for step S3, the gate-level netlist includes the logical link data, and the logical link data includes the clock path structure described above. For example, the logic connection data is a netlist generated by an EDA tool (e.g., a Verilog netlist or a Spice netlist), and the clock driving unit 403 and the clock end point units 501, 502, and 503 are all connected through a logic-sense interconnection 303. In view of the fact that the front-end design is not the focus of the description of the embodiments of the present disclosure, the embodiments of the present disclosure omit the relevant contents of the front-end design and its gate-level netlist in order to ensure the clarity and conciseness of the description of the present disclosure.
For example, in some examples, after the layout and the routing, the timing analysis method based on the physical trace division in any of the above embodiments is performed, which is not described herein in detail.
FIG. 5 is a flow chart of a simulation of generating clock delay data for a plurality of physical segment lines and a plurality of physical segment nodes according to some embodiments of the present disclosure.
For example, as shown in fig. 5, for step S3, clock delay data respectively corresponding to a plurality of physical segment lines and a plurality of physical segment nodes is generated by simulation, specifically including step S31 and step S32.
Step S31, extracting the parasitic resistance data and the parasitic capacitance data of the plurality of physical segment segments, and the parasitic resistance data and the parasitic capacitance data of the plurality of physical segment nodes, respectively, to obtain parasitic parameter data.
Step S32, based on the logical connection data, the physical connection relation data, and the parasitic parameter data, under different stimuli, clock delay data corresponding to the plurality of physical segment lines and the plurality of physical segment nodes are generated through simulation.
For example, in some examples, for step S31, simulation of the clock delay data corresponding to the plurality of physical segment segments and the plurality of physical segment nodes is implemented by a simulation tool (e.g., an EDA tool). For example, the simulation tool includes an EDA tool. For example, in some examples, EDA tools employ ICC as a new generation back-end design tool for Synopsys. Of course, this is merely exemplary and not a limitation of the present disclosure.
For example, in some examples, for step S31, the EDA tool mates with a Starrc tool or the like to achieve accurate signature core drive design optimization, wherein parasitic resistance data and parasitic capacitance data are extracted by the Starrc tool, each physical tap segment has its own parasitic resistance and parasitic capacitance, respectively, and each physical tap node has its own parasitic resistance and parasitic capacitance, respectively.
For example, in some examples, parasitic resistances R and parasitic capacitances C of the physical segment and physical segment nodes, respectively, are extracted from the physical topology shown in fig. 3 (i.e., the physical topology formed via physical trace splitting) by the Starrc tool. Of course, the embodiments of the present disclosure do not limit the extraction manner of the parasitic resistance data and the parasitic capacitance data, and are not described herein again.
For example, in some examples, for step S32, the different stimuli include: the input signal is switched from a low level to a high level in the case of a different signal switching time (TransitionTime), or from a high level to a low level in the case of a different signal switching time.
For example, in some examples, for step S32, the logical connection data, the physical connection relationship data, and the parasitic parameter data are read in by the simulation tool for subsequent simulation to generate corresponding clock delay data.
For example, with regard to the meaning of clock delay data, the following is exemplified: for the physical segment 100 shown in fig. 3, when the output of the target clock driving unit 403 goes from low level to high level and the signal transition time is 20ps, the delay generated on the physical segment 100 after EDA simulation is 1ps, which means that the clock delay data of the corresponding physical segment 100 generated by simulation is 1 ps. Of course, this is merely exemplary to facilitate understanding of embodiments of the present disclosure and is not a limitation of the present disclosure.
FIG. 6 is a flow chart for obtaining clock delay data for a clock path structure by removing an overly pessimistic amount generated by a common physical path according to some embodiments of the present disclosure.
For example, as shown in fig. 6, for step S4, the method specifically includes steps S41 to S44, in which the excessive pessimistic amount generated by the common physical path is removed based on the clock delay data of the common physical segment and the common physical segment node to obtain the clock delay data of the clock path structure.
Step S41, obtaining the logical connection data, the physical connection relation data, and the clock delay data generated by simulation and respectively corresponding to the plurality of physical segment and the plurality of physical segment nodes.
And step S42, according to different stimuli, based on the logic connection data and the physical connection relation data, calculating clock delay data corresponding to the common physical path by using the clock delay data of the common physical line segment and the common physical node.
Step S43, based on the clock delay data corresponding to the common physical path, obtains the over-pessimism amount P.
Step S44, obtaining the clock delay data of the clock path structure by removing the excessive pessimistic amount P.
For example, in some examples, for step S41, the logical link data, the physical link relation data, and the simulation generated clock delay data are read in by the timing calculation tool for subsequent removal of the over-pessimistic amount P generated by the common physical path. For example, the timing calculation tool is a Primetime tool, wherein the ICC also mates with the Primetime tool to achieve precise signature core drive design optimization.
For example, in some examples, for step S44, the overly pessimistic amount P refers to a deviation caused by different increasing and decreasing factors when the transmit path and the receive path respectively use different increasing and decreasing factors to calculate the path delay and when the two paths have corresponding common physical paths, where the receive path is at least a portion of a clock interconnect between the target clock driver unit and a first one of the at least two target clock destination units, and the transmit path is at least a portion of a clock interconnect between the target clock driver unit and a second one of the at least two target clock destination units.
For example, when calculating the clock delay data of the clock path structure, the paths from the target clock driving unit 403 to the target clock end point units 501 and 502 are the transmission path and the reception path, and the physical segment 100 and the physical nodes 200 and 201 of the common physical path of the transmission path and the reception path are deviated due to different increasing and decreasing factors, respectively, thereby generating the over-pessimistic amount P. Of course, this is merely exemplary to facilitate understanding of the embodiments of the present disclosure, and is not a limitation of the present disclosure, and other possible situations will not be described herein.
Fig. 7 is a flow chart for calculating clock delay data corresponding to a common physical path using clock delay data of a common physical segment and a common physical segment node according to some embodiments of the present disclosure.
For example, as shown in fig. 7, for step S42, the clock delay data corresponding to the common physical path is calculated using the clock delay data of the common physical segment and the common physical segment, including steps S421 to S423.
Step S421, multiplying the clock delay data corresponding to each common physical segment of the common physical path by the corresponding increase/decrease factor to obtain a first clock delay result D1.
Step S422, the clock delay data corresponding to each common physical branch point of the common physical path is multiplied by the corresponding increase and decrease factor to obtain a second clock delay result D2.
Step S423, summing each first clock delay result D1 and each second clock delay result D2 to obtain clock delay data Dx corresponding to the common physical path.
For example, in some examples, when the common physical path is the common physical path 100a shown in fig. 3, the common physical segment corresponding to the common physical path 100a is 100, and the common physical nodes are 200 and 201, if the increase and decrease factors adopted by the common physical segment 100 and the common physical nodes are 200 and 201 are d1, d2, and d3 respectively, for example, the clock delay data generated by simulation corresponding to 100, 200, 201 are 3ps, 2ps, and 1ps respectively, then the clock delay data corresponding to the common physical path 100a is equal to: 3ps × d1+2ps × d2+1ps × d3, wherein the first clock delay result is 3ps × d1 and the second clock delay result is 2ps × d2 and 1ps × d3, respectively.
For example, in some examples, the increase and decrease factors d1, d2, d3 may be the same for each other, such as individually for the common physical path 100a owned by the receiving path, the increase and decrease factors for all common physical line segments and common physical node segments may be the same, i.e., d1 — d2 — d3 — d, then the above-mentioned clock delay data corresponding to the common physical path 100a is equal to (3ps +2ps +1ps) d. Certainly, in a specific case, the increase and decrease factors d1, d2, and d3 may also be different from each other, which is not limited in this embodiment of the present disclosure, and the increase and decrease factors are specifically determined according to an actual situation, and are not described herein again.
Fig. 8 is a flow chart for calculating clock delay data corresponding to a common physical path using clock delay data of a common physical segment and a common physical segment node according to still other embodiments of the present disclosure.
For example, as shown in fig. 8, for step S42, the clock delay data corresponding to the common physical path is calculated by using the clock delay data of the common physical segment and the common physical segment node, and specifically includes step S4201 and step S4202.
Step S4201, summing each third clock delay result D3 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increasing and decreasing factor corresponding to when the path is accepted, and each fourth clock delay result D4 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increasing and decreasing factor corresponding to when the path is accepted, to obtain first clock delay data D01, wherein the first clock delay data D01 represents the clock delay data corresponding to the common physical path when the path is accepted.
Step S4202, summing each fifth clock delay result D5 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increasing and decreasing factor corresponding to the transmission path, and each sixth clock delay result D6 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increasing and decreasing factor corresponding to the transmission path, to obtain second clock delay data D02, wherein the second clock delay data D02 represents the clock delay data corresponding to the common physical path when used for the transmission path.
It should be noted that, step S4201 and step S4202 herein have no preceding or subsequent order, for example, the order of the steps may be step S4201 to step S4202, or step S4202 to step S4201, or both steps may be processed simultaneously, which is not limited in this embodiment of the present disclosure.
For example, in the examples of fig. 7 and 8, the corresponding increase and decrease factors for accepting the path are the same for each common physical segment and each common physical node corresponding to the common physical path, and/or the corresponding increase and decrease factors for transmitting the path are the same for each common physical segment and each common physical node corresponding to the common physical path.
For another example, in the examples of fig. 7 and 8, the respective increase and decrease factors for accepting the path may be different for at least two of each common physical segment and each common physical node corresponding to the common physical path, and/or the respective increase and decrease factors for transmitting the path may be different for at least two of each common physical segment and each common physical node corresponding to the common physical path. The embodiment of the present disclosure is not limited to this, and may be specifically adjusted according to actual needs, which is not described herein again.
For example, in some examples, when the common physical path is the common physical path 100a shown in fig. 3, the common physical segment corresponding to the common physical path 100a is 100, and the common physical nodes are 200 and 201, if the common physical segment 100 and the common physical nodes 200 and 201 are both used in the transmit path with equal scaling factors, e.g., denoted as D, and the clock delay data corresponding to 100, 200 and 201 generated by simulation is 3ps, 2ps and 1ps, respectively, then the second clock delay data D02 is equal to (2ps +3ps +1ps) × D. Similarly, if the common physical segment 100 and the common physical nodes 200, 201 both use equal scaling factors when receiving paths, e.g., denoted as D ', and the simulation generated clock delay data corresponding to 100, 200, 201 are 3ps, 2ps, and 1ps, respectively, then the first clock delay data D01 is equal to (2ps +3ps +1ps) D'. Of course, this is merely exemplary to facilitate understanding of the embodiments of the present disclosure, and is not a limitation of the present disclosure, and other possible situations will not be described herein.
For example, in some examples, for step S43, obtaining the excessive pessimism amount P based on the clock delay data corresponding to the common physical path specifically includes: the difference obtained by subtracting the first clock delay data D01 and the second clock delay data D02 is taken as the excessive pessimistic amount P corresponding to the common physical path.
FIG. 9 is a flow chart for obtaining clock delay data for a clock path structure by removing an overly pessimistic amount according to still other embodiments of the disclosure.
For example, as shown in fig. 9, for step S44, the clock delay data Dy of the clock path structure a100 is obtained by removing the excessive pessimistic amount P, which specifically includes step S441 and step S442.
Step S441, third clock delay data D03 of the accept path and fourth clock delay data D04 of the transmit path are acquired.
Step S442, configure the clock delay data Dy of the clock path structure to be equal to: the third clock delay data D03- (the fourth clock delay data D04-amount of over pessimism P).
For example, in some examples, each seventh clock delay result D7 obtained by multiplying the clock delay data corresponding to each physical segment of the accepted path by the corresponding increase or decrease factor for the accepted path is summed with each eighth clock delay result D8 obtained by multiplying the clock delay data corresponding to each physical segment of the accepted path by the corresponding increase or decrease factor for the accepted path to obtain third clock delay data D03 for the accepted path; similarly, each ninth clock delay result D9 obtained by multiplying the clock delay data of each physical segment of the corresponding transmission path by the corresponding increase and decrease factor for the transmission path is summed with each tenth clock delay result D10 obtained by multiplying the clock delay data of each physical segment of the corresponding transmission path by the corresponding increase and decrease factor for the transmission path to obtain fourth clock delay data D04 of the transmission path.
For example, in some examples, the fourth clock delay data D04 for the transmit path between the target clock driver unit 403 to the target clock destination unit 501 in fig. 3 is equal to the total delay of the physical traces through the physical branch node 200, the physical branch segment 100, the physical branch node 201, the physical branch segment 101, and the physical branch node 202, wherein, if the increasing and decreasing factors adopted by 200, 100, 201, 101, 202 are d1, d2, d3, d4, d5 respectively, and for example, the clock delay data generated by simulation corresponding to 200, 100, 201, 101, 202 are 2ps, 3ps, 1ps, 4ps, 3.5ps respectively, then D04 equals 2ps x D1+3ps x D2+1ps x D3+4ps x D4+3.5ps x D5, the ninth clock delay result D9 is 3ps × D2 and 4ps × D4, and the tenth clock delay result D10 is 2ps × D1, 1ps × D3, and 3.5ps × D5.
For example, in some examples, the third clock delay data D03 for the accept path from the target clock driving unit 403 to the target clock destination unit 502 in fig. 3 is equal to the total delay of the physical traces passing through the physical branch node 200, the physical branch segment 100, the physical branch node 201, the physical branch segment 102, the physical branch node 203, the physical branch segment 103, and the physical branch node 204, wherein if the increase and decrease factors adopted by 200, 100, 201, 102, 203, 103, 204 are D1 ', D2', D3 ', D4', D5 ', D6', D7 ', and if the simulation-generated clock delay data corresponding to 200, 100, 201, 102, 203, 103, 204 are 2ps, 3ps, 1ps, 4.2ps, 3.2ps, 4.5ps, 3.5ps, D03 is equal to 2ps + 3+ 42 +1ps, 84 + 3+ 5 + 3+ 36' + 3+ 5 '+ 8925' + 36 '+ 3' + 42 '+ 3' + 36 '+ 3' + 36, wherein the seventh clock delay results D7 are 3ps × D2 ', 4.2ps × D4 ' and 4.5ps × D6 ', respectively, and the eighth clock delay results D8 are 2ps × D1 ', 1ps × D3 ', 3.2ps × D5 ' and 3.5ps × D7 ', respectively.
It should be noted that the increase and decrease factors d1, d2, d3, d4, and d5 for the transmit path may be the same as or different from each other, and similarly, d1 ', d2 ', d3 ', d4 ', d5 ', d6 ', and d7 ' for receiving the increase and decrease factors of the path may be the same as or different from each other, which is specifically referred to the above description and is not described herein again.
For example, in some examples, if the increase and decrease factors D1, D2, D3, D4 and D5 for the transmit path are the same, i.e., D1 ═ D2 ═ D4 ═ D5 ═ D, if D ═ 1.1, the fourth clock delay data D04 for the transmit path is equal to (2ps +3ps +1ps +4ps +3.5ps) × 1.1 ═ 14.85ps, and similarly, if the increase and decrease factors D1 ', D2', D3 ', D4', D5 ', D6', D7 'for the receive path are the same, i.e., D2 ═ D3 ═ D4' ═ D4 ═ 3ps +3.5ps + 3.3 ps + 3.1 ÷ P3.3.3.3.5 ps + 3.3.3.3.3 ps + 3.1 is equal to the common excess amount (P3.3.3.3 ps), the final clock delay data Dy is 19.26ps- (14.85ps-1.2ps) 5.61 ps. Of course, this is merely exemplary to facilitate understanding of the embodiments of the present disclosure, and is not a limitation of the present disclosure, and other possible situations will not be described herein.
Therefore, the embodiments of the present disclosure can avoid the excessive pessimistic amount P caused by the common physical path of the first clock end point unit 501 and the third clock end point unit 503 adopting different increasing and decreasing factors, can also avoid the excessive pessimistic amount P caused by the common physical path of the second clock end point unit 502 and the third clock end point unit 503 adopting different increasing and decreasing factors, and can also avoid the excessive pessimistic amount P caused by the common physical path of the first clock end point unit 501 and the second clock end point unit 502 adopting different increasing and decreasing factors.
According to the time sequence analysis method disclosed by the embodiment of the disclosure, the corresponding physical branch line segments and physical branch nodes are obtained through physical routing division of the clock interconnection line, and when the time sequence is calculated, delay deviations caused by different increases and decreases of the physical branch line segments and the physical branch nodes corresponding to the common physical path are removed, so that the clock deviation is reduced, the accuracy of time sequence convergence is improved, the power consumption is reduced, and the performance of a chip is improved.
Fig. 10 is a schematic block diagram of a timing analysis device based on physical trace division according to some embodiments of the present disclosure.
For example, as shown in fig. 10, the timing analysis apparatus 600 includes a receiving module 610, a physical trace dividing module 620, a simulation module 630, and a timing calculation module 640. The receiving module 610 is configured to: and acquiring a clock path structure to be analyzed based on the gate-level netlist for the integrated circuit design, wherein the clock path structure comprises a clock interconnection line, a target clock driving unit and at least two target clock terminal units, and the target clock driving unit and the at least two target clock terminal units are connected through the clock interconnection line. The physical trace splitting module 620 is configured to: the method comprises the steps of carrying out physical routing division on a clock interconnection line to obtain a plurality of physical branch nodes and a plurality of physical branch lines spaced by the physical branch nodes so as to obtain physical connection relation data between a target clock driving unit and at least two target clock terminal units, wherein the physical branch lines and the physical branch nodes respectively comprise common physical branch lines and common physical branch nodes corresponding to common physical paths of the at least two target clock terminal units. The simulation module 630 is configured to: and generating clock delay data respectively corresponding to the plurality of physical branch segments and the plurality of physical branch nodes through simulation based on the physical connection relation data and the logic connection data included in the gate-level netlist. The timing calculation module 640 is configured to: based on the clock delay data of the common physical segment and the common physical segment node, an overly pessimistic amount generated by the common physical path is removed to obtain clock delay data of the clock path structure.
For example, in some examples, a target clock drive unit includes: for one or more clock driving units of the plurality of clock driving units connected in series and/or in parallel, reference may be made to the description of the timing analysis method above, and details are not repeated here.
For example, in some examples, simulation module 630 is further configured to: respectively extracting parasitic resistance data and parasitic capacitance data of a plurality of physical branch segments and parasitic resistance data and parasitic capacitance data of a plurality of physical branch nodes to obtain parasitic parameter data; and generating clock delay data respectively corresponding to the plurality of physical line segments and the plurality of physical branch nodes by simulation under different excitations based on the logic connection data, the physical connection relation data and the parasitic parameter data.
For example, in some examples, the different stimuli include: the input signal from low level to high level when based on different signal transition times, or the input signal from high level to low level when based on different signal transition times.
For example, in some examples, simulation module 630 includes an EDA tool. Of course, this is merely exemplary and not a limitation of the present disclosure.
For example, in some examples, the timing calculation module 640 is further configured to: acquiring logic connection data, physical connection relation data and clock delay data which are generated by simulation and respectively correspond to a plurality of physical branch segments and a plurality of physical branch nodes; according to different stimuli, based on the logic connection data and the physical connection relation data, clock delay data corresponding to a common physical path are obtained through calculation by utilizing the clock delay data of the common physical line segment and the common physical node; acquiring an excessive pessimistic amount P based on clock delay data corresponding to a common physical path; the clock delay data of the clock path structure is obtained by removing the over pessimistic amount P.
For example, the timing calculation module 640 includes a Primetime tool, wherein the ICC also mates with the Primetime tool to achieve accurate signature core driver design optimization.
For example, in some examples, the timing calculation module 640 is further configured to: multiplying the clock delay data corresponding to each common physical line segment of the common physical path by the corresponding increase and decrease factor to obtain a first clock delay result D1; multiplying the clock delay data of each common physical branch node corresponding to the common physical path by the corresponding increase and decrease factor to obtain a second clock delay result D2; each of the first clock delay results D1 and each of the second clock delay results D2 are summed to obtain clock delay data corresponding to the common physical path.
For example, in some examples, the timing calculation module 640 is further configured to: obtaining first clock delay data D01 by summing each third clock delay result D3 obtained by multiplying clock delay data corresponding to each common physical segment of the common physical path by an incremental or decremental factor corresponding to when the path is accepted, and each fourth clock delay result D4 obtained by multiplying clock delay data corresponding to each common physical segment of the common physical path by an incremental or decremental factor corresponding to when the path is accepted, wherein the first clock delay data D01 represents clock delay data corresponding to the common physical path when the path is accepted, and the acceptance path is at least a portion of a clock interconnection between the target clock driving unit and a first one of the at least two target clock end units; and summing each fifth clock delay result D5 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increasing and decreasing factor corresponding to the transmitting path, and each sixth clock delay result D6 obtained by multiplying the clock delay data corresponding to each common physical segment of the common physical path by the increasing and decreasing factor corresponding to the transmitting path, to obtain second clock delay data D02, wherein the second clock delay data D02 represents the clock delay data corresponding to the common physical path for the transmitting path, and the transmitting path is at least a part of the clock interconnection line between the target clock driving unit and the second one of the at least two target clock end units.
For example, in some examples, for each common physical segment and each common physical node that correspond to a common physical path, the corresponding increase and decrease factors are the same when accepting the path; and/or, for each common physical segment corresponding to the common physical path and each common physical node, the increase and decrease factors corresponding to the transmission path are the same, which is not limited in this embodiment of the present disclosure.
For example, in some examples, the timing calculation module 640 is further configured to: the difference obtained by subtracting the first clock delay data D01 and the second clock delay data D02 is taken as the excessive pessimistic amount P corresponding to the common physical path.
For example, in some examples, the timing calculation module 640 is further configured to: acquiring third clock delay data D03 of the reception path and fourth clock delay data D04 of the transmission path; configuring the clock delay data of the clock path structure to be equal to: the third clock delay data D03- (the fourth clock delay data D04-amount of over pessimism P). For example, each seventh clock delay result D7 obtained by multiplying the clock delay data corresponding to each physical segment of the accepted path by the increasing or decreasing factor corresponding to the accepted path is summed with each eighth clock delay result D8 obtained by multiplying the clock delay data corresponding to each physical segment of the accepted path by the increasing or decreasing factor corresponding to the accepted path to obtain third clock delay data D03 of the accepted path; the fourth clock delay data D04 of the transmission path is obtained by summing each ninth clock delay result D9 obtained by multiplying the clock delay data of each physical division line segment of the corresponding transmission path by the corresponding increase and decrease factor for the transmission path, and each tenth clock delay result D10 obtained by multiplying the clock delay data of each physical division node of the corresponding transmission path by the corresponding increase and decrease factor for the transmission path.
For example, in some examples, for each physical segment and each physical node of the corresponding accepted path, the increase and decrease factors corresponding to accepting the path are the same; and/or for each physical segment and each physical node of the corresponding transmission path, the increase and decrease factors corresponding to the transmission path are the same, which is not limited in the embodiment of the present disclosure.
It should be noted that, in the embodiment of the present disclosure, the timing analysis apparatus 600 may include more or less modules, and the connection relationship between the modules is not limited and may be determined according to actual requirements. The specific configuration of each module is not limited. For technical effects of the timing analysis apparatus 600, reference may be made to technical effects of the timing analysis method in the foregoing embodiments of the disclosure, and details are not repeated here.
The various modules in the above embodiments may each be configured as software, hardware, firmware, or any combination thereof that performs a particular function. For example, the modules may correspond to an application specific integrated circuit, to pure software code, or to a combination of software and hardware.
It should be noted that, although the timing analysis apparatus is described above as being divided into modules for respectively performing corresponding processes, it is clear to those skilled in the art that the processes performed by the respective modules may also be performed without any specific division of the timing analysis apparatus into modules or without explicit delimitation between the modules.
For example, in some examples, the timing analysis method of embodiments of the present disclosure may be recorded in a computer-readable recording medium. In particular, embodiments of the present disclosure may provide a computer-readable recording medium storing computer-executable instructions that, when executed by a processor of the computer, may cause the computer processor to perform the timing analysis method as described above. Examples of the computer readable recording medium may include magnetic media (e.g., hard disks, floppy disks, and magnetic tapes); optical media (e.g., CD-ROM and DVD); magneto-optical media (e.g., optical disks); and hardware devices that are specially configured to store and execute program instructions (e.g., Read Only Memory (ROM), Random Access Memory (RAM), flash memory, etc.).
Fig. 11 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure.
For example, as shown in fig. 11, at least one embodiment of the present disclosure may also provide an electronic device 700, the electronic device 700 including a processor 710 and a memory 720. The memory 720 is used to store non-transitory computer readable instructions (e.g., one or more computer program modules) that the processor 710 is used to execute, and the non-transitory computer readable instructions, when executed by the processor 710, may perform one or more of the steps of the timing analysis method above. It should be noted that, in the embodiment of the present disclosure, reference may be made to the description of the timing analysis method in the foregoing for specific functions and technical effects of the electronic device 700, and details are not described herein again.
The following points need to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims (14)

1. A timing sequence analysis method based on physical routing division comprises the following steps:
obtaining a clock path structure to be analyzed based on a gate-level netlist for an integrated circuit design, wherein the clock path structure comprises a clock interconnection line and a target clock driving unit and at least two target clock end-point units connected through the clock interconnection line,
performing physical routing division on the clock interconnection line to obtain a plurality of physical branch nodes and a plurality of physical branch lines spaced by the plurality of physical branch nodes to obtain physical connection relation data between the target clock driving unit and the at least two target clock end point units, wherein the plurality of physical branch lines and the plurality of physical branch nodes respectively include a common physical branch line and a common physical branch node corresponding to a common physical path of the at least two target clock end point units,
generating clock delay data corresponding to the plurality of physical segment segments and the plurality of physical segment nodes, respectively, by simulation based on the physical connection relation data and logical connection data included in the gate-level netlist,
removing an amount of excess pessimism generated by the common physical path based on the clock delay data for the common physical segment and the common physical segment node to obtain the clock delay data for the clock path structure.
2. The timing analysis method of claim 1, wherein the target clock driving unit comprises: one or more clock driver units of a plurality of clock driver units connected in series and/or in parallel.
3. The timing analysis method of claim 1, wherein generating clock delay data corresponding to the plurality of physical segment lines and the plurality of physical segment nodes, respectively, by simulation comprises:
respectively extracting the parasitic resistance data and the parasitic capacitance data of the plurality of physical segment sections and the parasitic resistance data and the parasitic capacitance data of the plurality of physical segment nodes to obtain parasitic parameter data,
and generating clock delay data respectively corresponding to the plurality of physical branch segments and the plurality of physical branch nodes by simulation under different excitations based on the logic connection line data, the physical connection relation data and the parasitic parameter data.
4. The timing analysis method of claim 3, wherein the different stimuli comprise: the input signal from low level to high level when based on different signal transition times, or the input signal from high level to low level when based on different signal transition times.
5. The timing analysis method of claim 3, wherein removing an overly pessimistic amount P generated by the common physical path based on the clock delay data of the common physical segment and the common physical segment node to obtain the clock delay data of the clock path structure comprises:
acquiring the logic connection data, the physical connection relation data and clock delay data generated by simulation and respectively corresponding to the plurality of physical line segments and the plurality of physical division nodes,
calculating clock delay data corresponding to the common physical path based on the logical connection data and the physical connection relationship data using the clock delay data of the common physical segment and the common physical segment node according to the different stimuli,
obtaining the over-pessimistic amount P based on clock delay data corresponding to the common physical path,
obtaining the clock delay data of the clock path structure by removing the over pessimistic amount P.
6. The timing analysis method of claim 5, wherein calculating clock delay data corresponding to the common physical path using the clock delay data of the common physical segment and the common physical segment node comprises:
multiplying the clock delay data corresponding to each of the common physical line segments of the common physical path by the corresponding scaling factor to obtain a first clock delay result D1,
multiplying the clock delay data corresponding to each of the common physical nodes of the common physical path by the corresponding scaling factor to obtain a second clock delay result D2,
summing each of the first clock delay results D1 and each of the second clock delay results D2 to obtain clock delay data corresponding to the common physical path.
7. The timing analysis method of claim 5, wherein calculating clock delay data corresponding to the common physical path using the clock delay data of the common physical segment and the common physical segment node comprises:
obtaining first clock delay data D01 by summing each third clock delay result D3 obtained by multiplying clock delay data corresponding to each of the common physical segment of the common physical path by an increasing or decreasing factor corresponding to when a path is accepted, and each fourth clock delay result D4 obtained by multiplying clock delay data corresponding to each of the common physical segment nodes of the common physical path by an increasing or decreasing factor corresponding to when a path is accepted, the first clock delay data D01 representing clock delay data corresponding to the common physical path when the path is accepted, the accepted path being at least a portion of a clock interconnection between the target clock driving unit and a first one of the at least two target clock end units,
and summing each fifth clock delay result D5 obtained by multiplying the clock delay data corresponding to each of the common physical segment of the common physical path by the corresponding increase and decrease factor for the transmit path, and each sixth clock delay result D6 obtained by multiplying the clock delay data corresponding to each of the common physical segment nodes of the common physical path by the corresponding increase and decrease factor for the transmit path, to obtain second clock delay data D02, wherein the second clock delay data D02 represents the clock delay data corresponding to the common physical path for the transmit path, and the transmit path is at least a portion of a clock interconnection between the target clock driving unit and a second one of the at least two target clock end units.
8. The timing analysis method according to claim 6 or 7,
for each common physical segment and each common physical node corresponding to the common physical path, the increase and decrease factors corresponding to the path receiving are the same;
and/or, for each common physical line segment corresponding to the common physical path and each common physical node, the increase and decrease factors corresponding to the transmission path are the same.
9. The timing analysis method of claim 7, wherein obtaining the amount of excess pessimism P based on the clock delay data corresponding to the common physical path comprises:
a difference obtained by subtracting the first clock delay data D01 and the second clock delay data D02 is taken as an excessive pessimistic amount P corresponding to the common physical path.
10. The timing analysis method of claim 9, wherein obtaining the clock delay data of the clock path structure by removing the over-pessimistic amount P comprises:
third clock delay data D03 for the accept path and fourth clock delay data D04 for the transmit path are obtained,
configuring clock delay data of the clock path structure equal to: the third clock delay data D03- (the fourth clock delay data D04-the over-pessimistic amount P),
wherein the third clock delay data D03 of the acceptance path is obtained by summing each seventh clock delay result D7 obtained by multiplying the clock delay data corresponding to each of the physical segment of the acceptance path by the increase and decrease factor corresponding to the time of the acceptance path and each eighth clock delay result D8 obtained by multiplying the clock delay data corresponding to each of the physical segment of the acceptance path by the increase and decrease factor corresponding to the time of the acceptance path,
and summing every ninth clock delay result D9 obtained by multiplying the clock delay data corresponding to every physical branch segment of the transmission path by the corresponding increase and decrease factor used for the transmission path, and every tenth clock delay result D10 obtained by multiplying the clock delay data corresponding to every physical branch node of the transmission path by the corresponding increase and decrease factor used for the transmission path, so as to obtain fourth clock delay data D04 of the transmission path.
11. The timing analysis method of claim 10,
for each physical branch segment corresponding to the received path and each physical branch node, the corresponding increase and decrease factors for the received path are the same;
and/or for each physical branch segment corresponding to the transmission path and each physical branch node, the corresponding increase and decrease factors are the same when the increase and decrease factors are used for the transmission path.
12. A timing analysis device based on physical routing division comprises:
a receiving module configured to obtain a clock path structure to be analyzed based on a gate-level netlist for an integrated circuit design, wherein the clock path structure includes a clock interconnect and a target clock driving unit and at least two target clock end units connected by the clock interconnect,
a physical trace splitting module configured to: performing physical routing division on the clock interconnection line to obtain a plurality of physical branch nodes and a plurality of physical branch lines spaced by the plurality of physical branch nodes to obtain physical connection relation data between the target clock driving unit and the at least two target clock end point units, wherein the plurality of physical branch lines and the plurality of physical branch nodes respectively include a common physical branch line and a common physical branch node corresponding to a common physical path of the at least two target clock end point units,
a simulation module configured to: generating clock delay data corresponding to the plurality of physical segment segments and the plurality of physical segment nodes, respectively, by simulation based on the physical connection relation data and logical connection data included in the gate-level netlist,
a timing calculation module configured to: removing an amount of excess pessimism generated by the common physical path based on the clock delay data for the common physical segment and the common physical segment node to obtain the clock delay data for the clock path structure.
13. An electronic device, comprising: a processor and a memory, wherein the processor is capable of processing a plurality of data,
wherein the memory has stored thereon a computer-executable program that, when executed by the processor, implements the timing analysis method of any of claims 1 to 11.
14. A computer-readable storage medium having stored therein a computer-executable program which, when executed by a processor, implements the timing analysis method of any one of claims 1 to 11.
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