CN113157438A - Dynamic thermal management method of multi-core microprocessor with high energy efficiency ratio - Google Patents
Dynamic thermal management method of multi-core microprocessor with high energy efficiency ratio Download PDFInfo
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Abstract
The invention belongs to the technical field of information control, and particularly relates to a dynamic power budget estimation method for a high-energy-efficiency-ratio multi-core microprocessor based on combination of model predictive control and task migration and dynamic voltage frequency adjustment. The invention aims to provide a high-speed (even can be realized by a lookup table) microprocessor dynamic thermal management method which is actively adjusted according to different task loads (alpha) aiming at high algorithm complexity and lack of optimization of a dark silicon chip in the prior art. The existing power profile is then corrected by performing task migration and dynamic voltage frequency adjustment. The invention successfully integrates the advantages of the task migration, the dynamic voltage frequency regulation and the model prediction control method, and can efficiently enable the processor to operate the current working load in a high energy efficiency ratio mode.
Description
Technical Field
The invention belongs to the technical field of information control, and particularly relates to a dynamic power budget estimation method for a high-energy-efficiency-ratio multi-core microprocessor based on combination of model predictive control and task migration and dynamic voltage frequency adjustment.
Background
With the rapid development of modern integrated circuit technology, the feature size of integrated circuits is reduced and the performance requirements are increased, and the power density is also increased. Starting at 90 nm, semiconductor fabrication processes have progressed to the nanometer stage and now, more recently, to 7 nm, 5 nm. At this stage, the leakage current on the silicon-based chip is greatly increased and is seriously influenced by the temperature, and the static power consumption and the temperature generated on the basis of the leakage current are in a nonlinear relationship and occupy a considerable proportion of the total power consumption. In a multi-core chip, once a core with a temperature rise occurs inside the chip, leakage current in the core also increases rapidly, resulting in an increase in leakage power consumption and further in a rise in core temperature. In summary, high temperature caused by high power density on chip reduces chip reliability and limits processor performance, thus becoming one of the most important limitations that restrict microprocessor development.
At present, in the field of chip application, there are two main metrics, the first is the overall performance of a multi-core chip: how to improve processor performance at safe temperatures due to power wall limitations. In recent years, dynamic thermal management techniques have been widely adopted to alleviate the effectiveness problems caused by overheating, and effective dynamic thermal management methods include task migration techniques and dynamic voltage frequency regulation. The task migration technique minimizes temperature differences on-chip by migrating high-power heavy-duty tasks on a high-temperature core with low-power light-duty tasks on a low-temperature core. The strategy can keep the high performance of the processor, reduce the thermal spatial gradient and reduce the temperature peak value, but if no other temperature regulation technology participates, the task migration can not ensure that the temperature of the core in the chip is in a safe temperature range. The dynamic voltage frequency adjustment technology can reduce power consumption by reducing the working voltage and frequency in the core, so as to ensure that the core is in a safe temperature range, but at the same time, quite serious performance loss can be caused;
the second is the energy efficiency ratio of the multi-core microprocessor chip, that is, how to execute more instructions under the condition of consuming the same strategy, in the past, the traditional energy efficiency ratio optimization management method usually ignores or counts by a constant value due to the nonlinear relationship between static power consumption and temperature when processing static power consumption, but this kind of approximation is not feasible in the current semiconductor process with the line width of 7 nm or even 5 nm, because in this kind of process, the static power consumption of the MOS transistor nearly accounts for 1/4 of the total power consumption, and even takes a higher weight with the rise of temperature.
Through the search of documents in the prior art, on the basis of solving the problem of the optimal performance at the safe temperature, HaiWang and Diya Tang release an article GDP (GDP: A Green Based Dynamic Power budget management Method applied to a Multi-Core Dark Silicon chip) in IEEE Transactions on Computers (IEEE computer institute), the article iteratively finds out the optimal solution through a Greedy algorithm, and the local optimization Method maximizes the overall performance of the Multi-Core Dark Silicon chip at the safe temperature; in the method for solving the energy efficiency ratio optimization, Vinay Hanumaai and Sarma Vudhula issue an article of energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling (the multi-core processor is optimized by high energy efficiency ratio through DVFS technology, Task scheduling technology and Active Cooling technology) in IEEE Transactions on Computers (IEEE computer exchanges), and the optimal solution recursive search with the best energy efficiency ratio is realized through a gradient descent algorithm.
Disclosure of Invention
The invention aims to provide a high-speed (even can be realized by a lookup table) microprocessor dynamic thermal management method which is actively adjusted according to different task loads (alpha) aiming at high algorithm complexity and lack of optimization of a dark silicon chip in the prior art. The existing power profile is then corrected by performing task migration and dynamic voltage frequency adjustment. The invention successfully integrates the advantages of the task migration, the dynamic voltage frequency regulation and the model prediction control method, and can efficiently enable the processor to operate the current working load in a high energy efficiency ratio mode.
Drawings
FIG. 1 shows the variation trend of the energy efficiency ratio of a single core with frequency
FIG. 2 shows the results of the present invention Mente Carlo Scan
FIG. 3 shows simulation results of the present invention
FIG. 4 is a management cycle flow diagram of the present invention
Detailed description of the preferred embodiments
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and examples.
The invention provides a power estimation method for a high energy efficiency ratio multi-core microprocessor based on combination of model predictive control and task migration and dynamic voltage frequency adjustment, which comprises the following specific steps of:
step one, establishing a thermal model of a microprocessor, and acquiring corresponding model parameters;
specifically, in the embodiment of the present invention, it is necessary to establish a thermal model corresponding to the multi-core/many-core microprocessor, and under providing relevant physical parameters of the microprocessor (for example, the heat dissipation capability of the chip TIM, the package area of the chip, the heat dissipation coefficients between layers, the distances between chips, etc.), the relevant software Hotspot is used to calculate various parameters of the thermal model, and in the subsequent steps, the thermal model is used to practice the temperature and the power consumption. The concrete expression is as follows:
gt (t) + C dT/dT ═ BP; (formula one)
For a processor with n cores, G is a matrix of (4n +12) × (4n +12), and the dimension of C is the same as G, except that the G matrix stores the conductance and transconductance relations between chips, the C matrix stores the capacitance relations between chips, and in a steady state relation, the coefficient of the C matrix is 0, mainly the relation affecting temperature and power in transient analysis. The B matrix is a (4n +12) × n selection matrix aimed at projecting the P vector with n × 1 representing the power onto the dimension (4n +12), and T is a (4n +12) × 1 matrix representing the temperature of each layer of the chip containing the package. In the formula relation, the input is power, and the corresponding temperatures corresponding to the transient state and the steady state, namely the input power, the output temperature, the input temperature and the output power can be calculated, so that the relation except the temperature and the power is established. By scanning the frequency, the relationship between the frequency and the energy efficiency ratio can be obtained, as shown in the figure I. Looking at the graph, we can find that the highest energy efficiency ratio is neither the lowest point nor the highest point of the frequency, but is at a position in the middle, which we can calculate according to the present invention.
Secondly, scheduling tasks according to a kernel selection algorithm according to the number of the tasks distributed by the operating system;
specifically, in this embodiment, a multi-core microprocessor architecture is constructed, a standard test program is simulated on the chip architecture through microprocessor performance simulation software, and a power consumption analysis module is integrated on the chip architecture to calculate power consumption data of each core on the chip.
Furthermore, an Alpha 21264-based multi-core microprocessor architecture is constructed, a SPEC standard test program is simulated on the microprocessor architecture needing dynamic thermal management design through Wattch software, and power consumption data of each core on a microprocessor chip are calculated. For example, for a multi-core microprocessor with n cores, when a SPEC runs na benchmark tests, its current power set is [ P1P 2P 3 … … Pna ]; and our goal is to get the distribution with the lowest average temperature by determining the position of the nucleation.
To illustrate this problem, we need to list the expressions that contain the static power for further explanation.
GT + C dT/dT ═ B (P _ d + P _ s) (equation two)
Where Pd represents dynamic power and Ps represents static power, where we need to establish a relationship between static power and temperature-we are the two-dimensional functional relationship between temperature and VDD for static power consumption obtained by Hspice simulation in the example. The fitting can be done by linear approximation (or multi-terminal linear approximation) at this time. Then
P _ s as T + bs V + P0 (formula three)
Where as, bs is a linear approximation constant and P0 is a zero point constant. The campus is carried out by substituting the formula III into the formula II, and the temperature which can be obtained under a certain dynamic power can be obtained. Through a greedy algorithm, the object open-core positions and the tasks corresponding to the object open-core positions can be selected through multiple iterations.
Thirdly, calculating the suggested working frequency of the high energy efficiency ratio according to the current working load (alpha) on the selected core;
specifically, in the present invention, it is necessary to predict the task state at the next time according to the task load and the location thereof and the current task state thereof and calculate the operating frequency that achieves the optimal energy efficiency ratio.
To illustrate our calculation method, the derived formula is further described herein.
Target ═ (alpha x F)/(P _ d + P _ s) (formula four)
The aim is to maximize Target, wherein Pd is replaced by a power model containing F, Ps is replaced by three static power models of formulas, the three static power models are expressed as the relation between T and V, the temperature T and the total power can be linked by the formulas, so that the temperature T and the total power can be all expressed as one relation of F, and the maximum value can be obtained by deriving the F. The effect of the invention is shown in the second and third graphs, and by performing frequency monte carlo scanning on the determined workload on the core, we obtain the second graph, and the energy efficiency ratio of the invention is at the position of the top point, which proves that the invention is effective and excellent, and further, by comparing the invention with the method of fixing the frequency of 1.5GHz and gradient descent (accurate solution, but high time complexity) (the third graph), we can find that the effect of the invention and gradient descent is no two and is 3 times higher than that of fixing the frequency of 1.5 GHz.
In summary, the present invention realizes a dynamic thermal management method for a multi-core microprocessor with high energy efficiency ratio at a very low cost, and the above example describes the present invention in detail, but is not limited thereto, and then the technical solutions described in the previous examples can be modified, which does not mean that the essence of the corresponding technical solutions deviates from the spirit and scope of the technical solutions of the examples of the present invention.
Claims (4)
1. A dynamic thermal management method of a high-energy-efficiency multi-core microprocessor comprises the following steps:
step 1, establishing a thermal model of a microprocessor, and acquiring corresponding model parameters;
step 2, scheduling tasks according to a kernel selection algorithm according to the number of the tasks distributed by the operating system;
step 3, calculating the suggested working frequency of the high energy efficiency ratio according to the current working load (alpha) on the selected core;
step 4, calculating the ratio of the original task working frequency to the suggested working frequency in the step 3;
and 5, reducing the working frequency in the original task by adopting a dynamic voltage frequency adjustment technology according to a corresponding ratio.
2. The model according to step 1 of claim 1 is applicable in the present invention to any multi-core structured chip model.
3. The specific implementation of step 2 according to claim 1 is: the current power of the task is sequentially brought into a thermal model established by Hotspot (namely, the power and the temperature can be mutually calculated), and an open-core position (local optimum and sequential calculation iteration) which enables the temperature to rise to be minimum is iterated through a greedy algorithm.
4. The specific implementation of step 3 according to claim 1 is: and substituting into a calculation formula of a thermal model, converting the energy efficiency ratio into a frequency expression, and solving the partial derivative of the frequency to obtain the recommended working frequency with the priority of the energy efficiency ratio. In addition, the invention can be applied to any workload and any kernel mode.
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| CN117215394A (en) * | 2023-11-07 | 2023-12-12 | 北京数渡信息科技有限公司 | On-chip temperature and energy consumption control device for multi-core processor |
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Cited By (2)
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