CN113156862B - Bit-domain proportional observer and novel basic controller system - Google Patents
Bit-domain proportional observer and novel basic controller system Download PDFInfo
- Publication number
- CN113156862B CN113156862B CN202110447242.5A CN202110447242A CN113156862B CN 113156862 B CN113156862 B CN 113156862B CN 202110447242 A CN202110447242 A CN 202110447242A CN 113156862 B CN113156862 B CN 113156862B
- Authority
- CN
- China
- Prior art keywords
- signal
- input
- output
- output signal
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
The application discloses a bit domain proportion observer and a novel basic controller system, wherein the bit domain proportion observer comprises an input selection module and a bit domain control quantity, the input selection module is used for receiving an input signal and the bit domain control quantity, the input signal is a deviation signal of a secondary superheated steam temperature given value and a secondary superheated steam temperature of a thermal power generating unit, and the secondary superheated steam temperature given value and the secondary superheated steam temperature comprise per unit processing; the pulse unit is used for receiving an input signal and an input position and proportion observation signal and outputting a pulse signal; the accumulator is used for receiving the output signals and the pulse signals of the input selection module, accumulating the output signals of the input selection module for 1 time according to each 1 pulse signal and outputting the accumulated signals; and the proportion regulator is used for carrying out proportion regulation on the accumulated output to finally obtain an output signal of the bit domain proportion observer. The method and the device can be applied to process control of the thermal power generating unit, improve the suppression performance of external disturbance compared with the prior art, and are a major breakthrough in the current observation mechanism.
Description
Technical Field
The application relates to the technical field of thermal power generating unit process control, in particular to a position domain proportion observer and a novel basic controller system.
Background
In the field of process control of thermal power units, in order to improve the process control performance of the existing thermal power units, the prior art provides a novel basic controller (NFC for short). The novel basic controller is a cascade structure of a high-performance proportional-integral controller (HPPI for short) and a high-performance advanced observer (HPLO for short), and can make breakthrough on a constant observation mechanism and make great progress on an advanced observation mechanism.
But the novel basic controller does not make breakthrough on the current observation mechanism, for example, the problem of poor external disturbance suppression performance is solved.
Disclosure of Invention
The application provides a bit domain proportion observer and a novel basic controller system, which aim to solve the problem that the external disturbance inhibition performance is weak in the prior art.
In order to solve the above technical problem, the present application provides a bit domain scale observer, including: the input selection module is used for receiving an input signal and a bit domain control quantity, wherein the input signal is a deviation signal of a secondary superheated steam temperature given signal and a secondary superheated steam temperature signal of the thermal power generating unit, and the secondary superheated steam temperature given signal and the secondary superheated steam temperature signal contain per unit processing; the pulse unit is used for receiving an input signal and an input bit domain proportion observation signal and outputting a pulse signal; the accumulator is used for receiving the output signal and the pulse signal of the input selection module, accumulating the output signal of the input selection module for 1 time according to each 1 pulse signal and outputting the accumulated output signal; and the proportion regulator is used for carrying out proportion regulation on the accumulated output to finally obtain an output signal of the bit domain proportion observer.
Optionally, the input selection module comprises: the multiplier is provided with a first input end, a second input end and an output end, wherein the first input end is used for receiving the bit domain control quantity, the second input end is used for receiving a-1 value, and the output end is used for outputting the product of the bit domain control quantity and the-1 value; a greater than 0 judger for receiving the input signal, wherein when the input signal is greater than 0, the output signal is 1, and when the input signal is less than or equal to 0, the output signal is 0; and the 2-input selector is used for receiving the bit domain control quantity, receiving the output signal of the multiplier by the second input end, and selecting the signal of the first input end or the signal of the second input end as the output signal of the 2-input selector according to the output signal of the judging device which is larger than 0 to finally obtain the output signal of the input selection module.
Optionally, the pulse unit comprises: the absolute value arithmetic unit is used for receiving the input signal and carrying out absolute value arithmetic on the input signal to obtain an absolute value signal; the pulse unit comprises a plurality of groups of pulse units which are connected in parallel, wherein each group of pulse units is used for receiving an absolute value signal and selecting whether to output a pulse signal after size judgment; the input or logic arithmetic unit is used for receiving the output signals of each group of pulse units, and if at least one group of output signals in the pulse units are 1, the output signals of the input or logic arithmetic unit are 1; and the 2 input AND logic operator is used for receiving the pulse signal and the input bit domain proportion observation signal and allowing the pulse signal to be output when the input bit domain proportion observation signal is 1.
Optionally, the pulse unit comprises: the greater than judger is used for receiving the absolute value signal and the high judgment value, and outputting a signal of 1 when the absolute value signal is greater than the absolute value signal, otherwise, outputting a signal of 0; the less than judger is used for receiving the absolute value signal and the low judgment value, and outputting a signal of 1 when the absolute value signal is less than the absolute value signal, otherwise, outputting a signal of 0; the touch 1 input end of the S-R trigger receives an output signal larger than the judging device, the touch 0 input end of the S-R trigger receives an output signal smaller than the judging device, when the output signal larger than the judging device is 1, the output signal of the S-R trigger is 1 and is kept, when the output signal smaller than the judging device is 1, the output signal of the S-R trigger is 0 and is kept, and the output signal larger than the judging device and the output signal smaller than the judging device are not simultaneously 1; the pulse trigger is used for receiving the output signal of the S-R trigger, and outputting a pulse signal if the output signal of the S-R trigger jumps from 0 to 1, wherein the time width of the pulse signal is 1 digital operation period.
In order to solve the technical problem, the application provides a novel basic controller system, is applied to thermal power generating unit's second order superheated steam temperature control system optimization, include: a bit-space scale observer as described above; the high-performance proportional-integral controller is connected with the bit domain proportional observer in parallel, the input end of the high-performance proportional-integral controller receives an output signal of the negative feedback link, and the output end of the high-performance proportional-integral controller is connected with the first adder; the input end of the negative feedback link receives a process given signal, and the negative feedback end of the negative feedback link receives an output signal of the high-performance advanced observer; the process module receives an output signal of the first adder, and the output end of the process module is connected with the second adder; the input end of the second adder also receives an output signal which is input into the external disturbance coupling model through unit step external disturbance, and the output of the second adder is process output; the input end of the high-performance advanced observer receives process output, and the output end of the high-performance advanced observer is connected with the negative feedback end of the negative feedback link.
Optionally, the new base controller transfer function is: nfc(s) hppi(s) hplo(s); wherein nfc(s) is a novel base controller transfer function, hppi(s) is a high performance proportional-integral controller transfer function, and hplo(s) is a high performance advanced observer transfer function.
Optionally, the high performance proportional-integral controller transfer function is:
HPPI(s)＝KHPPI[1+HEI(s)],
where HPPI(s) is a high performance proportional-integral controller transfer function, KHPPIFor the proportional gain of the cascaded proportional controller, HEI(s) is the high efficiency integrator transfer function, THEIIs an efficient integrator time constant.
Optionally, the high performance lead observer transfer function is:
where HPLO(s) is a high performance lead observer transfer function, THPLOIs a high performance lead observer time constant.
Optionally, the transfer function p(s) of the process module is:
optionally, the transfer function edcm(s) of the external disturbance coupling model is:
the application provides a bit domain proportion observer and a novel basic controller system, wherein the bit domain proportion observer comprises an input selection module for receiving an input signal and a bit domain control quantity, wherein the input signal is a deviation signal of a secondary superheated steam temperature given value and a secondary superheated steam temperature of a thermal power unit, and the secondary superheated steam temperature given value and the secondary superheated steam temperature comprise per unit processing; the pulse unit is used for receiving an input signal and an input bit domain proportion observation signal and outputting a pulse signal; the accumulator is used for receiving the output signals and the pulse signals of the input selection module, accumulating the output signals of the input selection module for 1 time according to each 1 pulse signal and outputting the accumulated signals; and the proportion regulator is used for carrying out proportion regulation on the accumulated output to finally obtain an output signal of the bit domain proportion observer. Through the mode, the method and the device can be applied to process control of the thermal power generating unit, compared with the prior art, the suppression performance of external disturbance is improved, and the method and the device are a major breakthrough in the current observation mechanism.
Drawings
In order to more clearly illustrate the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an embodiment of a bit domain scale observer according to the present application;
FIG. 2 is a schematic structural diagram of another embodiment of a bit domain scale observer according to the present application;
FIG. 3 is a simulation experiment result of a bit-domain proportional observer observing process output of a process at unit step input according to the present application;
fig. 4 is a schematic diagram of an embodiment of the basic controller system of the present application;
FIG. 5 is a schematic diagram of a structure of a bit-domain scale observer according to the present application for observing process output of a process at a unit step input;
fig. 6 is a simulation experiment result of an embodiment of the novel basic controller system of the present application;
FIG. 7 is a schematic representation of the control characteristics obtained by a prior art base controller;
fig. 8 is a schematic diagram of the control characteristics obtained by the novel basic controller system of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present application, the bit domain scale observer and the novel basic controller system provided in the present application are further described in detail below with reference to the accompanying drawings and the detailed description.
The terms and their abbreviations of the present application:
a New Foundation Controller (NFC);
a Position Zone Proportionality Observer (PZPO);
a Proportional Regulator (PR);
a High performance proportional-integral controller (HPPI);
a High Efficiency Integrator (HEI);
a High Performance Lead Observer (HPLO);
process (P);
external Disturbance Coupling Model (EDCM);
high limit (HDV);
low Diagnostic Value (LDV);
input locus proportion observation (Input PZPO, IPZPO);
a Position Zone Control Quality (PZCQ);
Z-N method (Ziegler-Nichols of method, Z-N: M).
And declaring:
in the present application, unless otherwise specified, the unit of proportional gain is dimensionless, the unit of order is dimensionless, and the unit of time and time constant is second.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a bit domain scale observer according to the present application. In the present embodiment, the bit-domain scale observer 100 may include an input selection module 110, a pulse unit 120, an accumulator 130, and a scale adjuster 140.
The input selection module 110 is configured to receive an input signal and a bit domain control variable, where the input signal is a deviation signal between a secondary superheated steam temperature given signal and a secondary superheated steam temperature signal of the thermal power generating unit, and the secondary superheated steam temperature given signal and the secondary superheated steam temperature signal include per unit processing.
The pulse unit 120 is configured to receive the input signal and the input bit-domain ratio observation signal, and output a pulse signal.
The accumulator 130 is configured to receive the output signal of the input selection module 110 and the pulse signal, and accumulate the output signal of the input selection module 110 for 1 time according to each 1 pulse signal and output the accumulated signal.
And the proportion regulator 140 is used for performing proportion regulation on the accumulated output, wherein the proportion regulator 140 is specifically a proportion link, and finally an output signal of the bit domain scale observer 100 is obtained.
Optionally, the input selection block 110 includes a multiplier, a greater than 0 determiner, and a 2-input selector.
And the first input end of the multiplier is used for receiving the bit domain control quantity, the second input end of the multiplier is used for receiving a-1 value, and the output end of the multiplier is used for outputting the product of the bit domain control quantity and the-1 value.
And the greater than 0 judger is used for receiving the input signal, when the input signal is greater than 0, the output signal is 1, and when the input signal is less than or equal to 0, the output signal is 0.
And a 2-input selector, a first input end for receiving the bit domain control quantity, a second input end for receiving the output signal of the multiplier, and a selection control end for selecting the signal of the first input end or the signal of the second input end as the output signal of the 2-input selector according to the output signal of the determiner greater than 0, and finally obtaining the output signal of the input selection module 110.
Optionally, the pulse unit 120 includes: absolute value arithmetic unit, several groups of pulse units 120, input or logic arithmetic unit and 2 input and logic arithmetic unit which are connected in parallel.
And the absolute value arithmetic unit is used for receiving the input signal and carrying out absolute value arithmetic on the input signal to obtain an absolute value signal.
The pulse units 120 are connected in parallel, and each group of pulse units 120 is used for receiving an absolute value signal and selecting whether to output a pulse signal after size judgment;
an input or logic operator, configured to receive the output signals of each group of pulse units 120, and if at least one group of output signals in the pulse units 120 is 1, the output signal of the input or logic operator is 1;
and the 2 input AND logic operator is used for receiving the pulse signal and the input bit domain proportion observation signal and allowing the pulse signal to be output when the input bit domain proportion observation signal is 1.
Optionally, the pulse unit 120 of each group includes a greater than decider, a less than decider, an S-R flip-flop, and a pulse flip-flop.
The greater than judger is used for receiving the absolute value signal and the high judgment value, and outputting a signal of 1 when the absolute value signal is greater than the absolute value signal, otherwise, outputting a signal of 0;
the less than judger is used for receiving the absolute value signal and the low judgment value, and outputting a signal of 1 when the absolute value signal is less than the absolute value signal, otherwise, outputting a signal of 0;
the touch 1 input end of the S-R trigger receives an output signal larger than the judging device, the touch 0 input end of the S-R trigger receives an output signal smaller than the judging device, when the output signal larger than the judging device is 1, the output signal of the S-R trigger is 1 and is kept, when the output signal smaller than the judging device is 1, the output signal of the S-R trigger is 0 and is kept, and the output signal larger than the judging device and the output signal smaller than the judging device are not simultaneously 1;
and the pulse trigger is used for receiving the output signal of the S-R trigger, outputting a pulse signal if the output signal of the S-R trigger jumps from 0 to 1, and the time width of the pulse signal is 1 digital operation period.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of the bit domain scale observer of the present application, in which the bit domain scale observer may include four sets of pulse units.
The method comprises the following specific steps:
the 1 inputs the input signal to the input end of the greater than 0 judger, and the output signal of the greater than 0 judger is obtained at the output end of the greater than 0 judger and is the BOOL variable. The input signal is specifically a deviation signal of a secondary superheated steam temperature given signal and a secondary superheated steam temperature signal of the thermal power generating unit, and the per-unit processing is hidden in the secondary superheated steam temperature given signal and the secondary superheated steam temperature signal;
if the deviation signal is greater than 0, the greater than 0 judger output signal is 1, otherwise, the greater than 0 judger output signal is 0.
2, inputting the input signal to the input end of an absolute value operator, and obtaining the output signal of the absolute value operator at the output end of the absolute value operator;
and 3, inputting the deviation signal into the pulse unit A, and obtaining an output signal of the pulse output unit A at the output end of the pulse unit A. The method comprises the following steps:
3.1, the output signal of the absolute value operator is input to a judged input end of a greater than judger A, a high judgment value A is input to a judgment input end of the greater than judger A, and the output signal of the greater than judger A is obtained at the output end of the greater than judger A and is a BOOL variable;
if the output signal of the absolute value operator is greater than the high judgment value A, the output signal of the absolute value operator is greater than the judgment value A and is 1, otherwise, the output signal of the absolute value operator is greater than the judgment value A and is 0.
3.2, the output signal of the absolute value operator is input to a judged input end of a smaller than judger A, a low judgment value A is input to a judging input end of the lower than judger A, and the output signal of the smaller than judger A is obtained at an output end of the smaller than judger A and is taken as a BOOL variable;
if the output signal of the absolute value arithmetic unit is less than the low judgment value A, the output signal of the absolute value arithmetic unit is less than the judgment value A and is 1, otherwise, the output signal of the absolute value arithmetic unit is less than the judgment value A and is 0.
3.3, the output signal of the larger judgment device A is input to the touch 1 input end of the S-R trigger A, the output signal of the smaller judgment device A is input to the touch 0 input end of the S-R trigger A, and the output signal of the S-R trigger A is obtained at the output end of the S-R trigger and is a BOOL variable;
if the output signal of the trigger A is greater than the output signal of the judger A, the output signal of the trigger A is 1 and the trigger A is kept. If the output signal of the trigger A is less than the output signal of the decider A, the output signal of the trigger A is 0 and is kept. The greater than determiner a output signal and the less than determiner a output signal are not both simultaneously 1.
3.4, inputting the output signal of the S-R trigger A to the input end of the pulse trigger A, and obtaining the output signal of the pulse trigger A at the output end of the pulse trigger A, wherein the output signal is a BOOL variable;
if the output signal of the S-R trigger A jumps from 0 to 1, a pulse signal is output at the output end of the pulse trigger A, and the time width of the output pulse signal is 1 digital operation period.
And 4, inputting the deviation signal into the pulse unit B, and obtaining an output signal of the pulse output unit B at the output end of the pulse unit B. The method comprises the following steps:
4.1, the output signal of the absolute value operator is input to a judged input end of a greater than judger B, a high judgment value B is input to a judgment input end of the greater than judger B, and the output signal of the greater than judger B is obtained at the output end of the greater than judger B and is a BOOL variable;
if the output signal of the absolute value arithmetic unit is larger than the high judgment value B, the output signal of the absolute value arithmetic unit is larger than the output signal of the judgment unit B and is 1, otherwise, the output signal of the absolute value arithmetic unit is larger than the output signal of the judgment unit B and is 0.
4.2, the output signal of the absolute value operator is input to a judged input end of a smaller than judger B, a low judgment value B is input to a judging input end of the lower than judger B, and the output signal of the smaller than judger B is obtained at an output end of the smaller than judger B and is taken as a BOOL variable;
if the output signal of the absolute value arithmetic unit is less than the low judgment value B, the output signal of the absolute value arithmetic unit is less than the judgment value B and is 1, otherwise, the output signal of the absolute value arithmetic unit is less than the judgment value B and is 0.
4.3, the output signal of the larger judgment device B is input to the touch 1 input end of the S-R trigger B, the output signal of the smaller judgment device B is input to the touch 0 input end of the S-R trigger B, and the output signal of the S-R trigger B is obtained at the output end of the S-R trigger and is a BOOL variable;
if the output signal of the trigger B is greater than the output signal of the judger B, the output signal of the trigger B of the S-R is 1. If the output signal of the trigger B is less than the judging device B and is 1, the output signal of the trigger B is 0 and is kept. The greater than determiner B output signal and the less than determiner B output signal are not both simultaneously 1.
4.4, inputting the output signal of the S-R trigger B to the input end of the pulse trigger B, and obtaining the output signal of the pulse trigger B at the output end of the pulse trigger B, wherein the output signal is a BOOL variable;
if the S-R trigger B output signal jumps from 0 to 1, a pulse signal is output at the output end of the pulse trigger B, and the time width of the output pulse signal is 1 digital operation period.
And 5, inputting the deviation signal into the pulse unit C, and obtaining an output signal of the pulse output unit C at the output end of the pulse unit C. The method comprises the following steps:
5.1, the output signal of the absolute value arithmetic unit is input to the judged input end of the larger than judging unit C, the high judging value C is input to the judging input end of the larger than judging unit C, and the output signal of the larger than judging unit C is obtained at the output end of the larger than judging unit C and is taken as a BOOL variable;
if the output signal of the absolute value arithmetic unit is larger than the high judgment value C, the output signal of the absolute value arithmetic unit is larger than that of the judgment unit C and is 1, otherwise, the output signal of the absolute value arithmetic unit is larger than that of the judgment unit C and is 0.
5.2, the output signal of the absolute value arithmetic device is input to the judged input end of the smaller than judger C, the low judgment value C is input to the judging input end of the lower than judger C, and the output signal of the smaller than judger C is obtained at the output end of the smaller than judger C and is taken as the BOOL variable;
if the output signal of the absolute value arithmetic unit is less than the low judgment value C, the output signal of the absolute value arithmetic unit is less than the judgment value C and is 1, otherwise, the output signal of the absolute value arithmetic unit is less than the judgment value C and is 0.
5.3, inputting the output signal of the trigger C larger than the judging device into a touch 1 input end of the S-R trigger C, inputting the output signal of the trigger C smaller than the judging device into a touch 0 input end of the S-R trigger C, and obtaining the output signal of the S-R trigger C which is a BOOL variable at an output end of the S-R trigger;
if the output signal of the trigger C is greater than the output signal of the judger C and is 1, the output signal of the trigger C is 1. If the output signal of the less than decider C is 1 and is kept, the output signal of the S-R trigger C is 0 and is kept. The greater than determiner C output signal and the less than determiner C output signal are not both simultaneously 1.
5.4, inputting the output signal of the S-R trigger C to the input end of the pulse trigger C, and obtaining the output signal of the pulse trigger C at the output end of the pulse trigger C, wherein the output signal is a BOOL variable;
if the output signal of the S-R trigger C jumps from 0 to 1, a pulse signal is output at the output end of the pulse trigger C, and the time width of the output pulse signal is 1 digital operation period.
And 6, inputting the deviation signal into a pulse unit D, and obtaining an output signal of the pulse output unit D at the output end of the pulse unit D. The method comprises the following steps:
6.1, the output signal of the absolute value operator is input to a judged input end of a larger than judger D, a high judgment value D is input to a judgment input end of the larger than judger D, and the output signal of the larger than judger D is obtained at the output end of the larger than judger D and is a BOOL variable;
if the output signal of the absolute value arithmetic device is larger than the high judgment value D, the output signal of the absolute value arithmetic device is larger than the judgment value D and is 1, otherwise, the output signal of the absolute value arithmetic device is larger than the judgment value D and is 0.
6.2, the output signal of the absolute value operator is input to the judged input end of the smaller than judger D, the low judgment value D is input to the judging input end of the lower than judger D, and the output signal of the smaller than judger D is obtained at the output end of the smaller than judger D and is taken as a BOOL variable;
if the output signal of the absolute value arithmetic unit is less than the low judgment value D, the output signal of the absolute value arithmetic unit is less than the judgment value D and is 1, otherwise, the output signal of the absolute value arithmetic unit is less than the judgment value D and is 0.
6.3, the output signal of the larger judgment device D is input to the touch 1 input end of the S-R trigger D, the output signal of the smaller judgment device D is input to the touch 0 input end of the S-R trigger D, and the output signal of the S-R trigger D is obtained at the output end of the S-R trigger and is a BOOL variable;
if the output signal of the D is more than the judging device and is 1, the output signal of the S-R trigger D is 1. If the output signal of the less than decider D is 1 and is kept, the output signal of the S-R trigger D is 0 and is kept. The greater than and smaller than decider D output signals are not both 1.
6.4, inputting the output signal of the S-R trigger D to the input end of the pulse trigger D, and obtaining the output signal of the pulse trigger D at the output end of the pulse trigger D, wherein the output signal is a BOOL variable;
if the S-R trigger D outputs a signal with the jump from 0 to 1, a pulse signal is output at the output end of the pulse trigger D, and the time width of the output pulse signal is 1 digital operation period.
7, inputting an output signal of a pulse trigger A to a 1 st input end of a 4-input or logic arithmetic unit, inputting an output signal of a pulse trigger B to a 2 nd input end of the 4-input or logic arithmetic unit, inputting an output signal of a pulse trigger C to a 3 rd input end of the 4-input or logic arithmetic unit, inputting an output signal of a pulse trigger D to a 4 th input end of the 4-input or logic arithmetic unit, and obtaining an output signal of the 4-input or logic arithmetic unit at an output end of the 4-input or logic arithmetic unit, wherein the output signal is a BOOL variable;
if any one of the output signals of the pulse trigger A, the pulse trigger B, the pulse trigger C and the pulse trigger D is a pulse signal, the output signal of the 4-input OR logic arithmetic unit is a pulse signal.
And 8, inputting the output signal of the 4-input OR logic operator to the 1 st input end of the 2-input AND logic operator, inputting the input bit domain proportion observation signal to the 2 nd input end of the 2-input AND logic operator, and obtaining the output signal of the 2-input AND logic operator at the output end of the 2-input AND logic operator. Inputting a bit domain proportion observation signal and a 2-input and logic operator output signal as BOOL variables;
if the input bit-domain ratio observation signal is 1, the 4-input or logic operator output signal is allowed to be output at the 2-input and logic operator output terminal.
9, inputting the bit domain control quantity to the input end of a multiplicand of the multiplier, inputting a-1 value to the input end of the multiplier, and obtaining an output signal of the multiplier at the output end of the multiplier;
10, inputting a bit domain control quantity to an input 1 end of a 2-input selector, inputting an output signal of a multiplier to an input 2 end of the 2-input selector, inputting an output signal of a judger greater than 0 to an input S end (selection control) of the 2-input selector, and obtaining an output signal of the 2-input selector at an output end of the 2-input selector;
if the signal at the input S terminal of the 2-input selector is 1, the signal at the input 1 terminal of the 2-input selector is selected to be output at the output terminal of the 2-input selector, and otherwise, the signal at the input 2 terminal of the 2-input selector is selected to be output at the output terminal of the 2-input selector.
11, inputting the output signal of the 2-input selector to an accumulation input end of an accumulator, inputting the output signal of the 2-input and logic arithmetic unit to an accumulation control input end of the accumulator, and obtaining an output signal of a bit-domain scale observer at an output end of the accumulator;
if every 1 pulse signal is received at the accumulation control input of the accumulator, the signal at the accumulation number input of the accumulator is accumulated 1 time into the accumulator output signal.
In this embodiment, the present invention further includes a proportional regulator, the proportional regulator is connected to the output end of the accumulator, and the output signal of the bit scale observer is finally obtained after being processed by the proportional regulator.
In this embodiment, the simulation experiment result obtained by setting the high determination value a to 0.2, the low determination value a to 0.18, the high determination value B to 0.4, the low determination value B to 0.38, the high determination value C to 0.6, the low determination value C to 0.58, the high determination value D to 0.8, the low determination value D to 0.78, the bit-domain control amount to 0.2, the proportional regulator gain to 1.0, and the input bit-domain ratio observation signal to 1 is shown in fig. 3, which is a simulation experiment result obtained by the present application in which a bit-domain ratio observer observes the process output of the process at the unit step input.
In FIG. 3, PVP(t) Process output at Unit step input for Process, PVPZPO(t) is a bit domain scale observer pair PVP(t) observed output. Visible, PVPZPO(t) is with PVPThere is a certain error between (t), which is an inherent defect of the proportional action, but it is not important because a position domain proportional observer mainly plays a role of a deviation elimination speed after an acceleration process is disturbed externally, and does not require accurate control.
Fig. 4 is a schematic structural diagram of an embodiment of a novel basic controller system according to the present application. A novel basic controller system can be applied to optimization of a secondary superheated steam temperature control system of a thermal power generating unit.
A novel base controller system may include: as described above in terms of bit field scaleThe system comprises a detector, a high-performance proportional-integral controller, a high-performance advanced observer, a first adder, a second adder, a negative feedback link, a process module and an external disturbance coupling model, wherein the transfer function P(s) of the process module is as follows:
the transfer function EDCM(s) of the external disturbance coupling model is:
and the high-performance proportional-integral controller is connected with the bit domain proportion observer in parallel, the input end of the high-performance proportional-integral controller receives an output signal of the negative feedback link, the output end of the high-performance proportional-integral controller is connected with the first adder, and the output signal of the negative feedback link is a deviation signal of the process given signal and the output signal of the high-performance advance observer.
The process module receives an output signal of the first adder, and the output end of the process module is connected with the second adder; the input end of the second adder also receives an output signal which is input into the external disturbance coupling model through unit step external disturbance, and the output of the second adder is process output.
The input end of the high-performance advanced observer receives process output, and the output end of the high-performance advanced observer is connected with the negative feedback end of the negative feedback link.
The method comprises the following specific steps:
1. inputting the process setting to the input end of the negative feedback link, and obtaining an output signal of the negative feedback link at the output end of the negative feedback link;
2. inputting the output signal of the negative feedback link to the input end of the high-performance proportional-integral controller, and obtaining the output signal of the high-performance proportional-integral controller at the output end of the high-performance proportional-integral controller;
3. inputting an output signal of the negative feedback link to an input end of the bit domain proportion observer, and obtaining the output signal of the bit domain proportion observer at an output end of the bit domain proportion observer;
4. inputting an output signal of the novel basic controller to an addend input end of a first adder, inputting an output signal of the bit domain proportion observer to an addend input end of the first adder, and obtaining an output signal of the first adder at an output end of the first adder;
5. inputting an output signal of the first adder to an input end of the process, inputting an output signal of the process to an addend input end of the second adder, inputting an output signal of the external disturbance coupling model to an addend input end of the second adder, and obtaining a process output signal at an output end of the second adder;
6. and inputting the process output signal to the input end of the high-performance advanced observer, and obtaining the output signal of the high-performance advanced observer at the output end of the high-performance advanced observer.
7. And the output signal of the high-performance advanced observer is input to a negative feedback input end of a negative feedback link.
Optionally, the novel base controller transfer function is:
NFC(s)＝HPPI(s)HPLO(s)……(1)
wherein nfc(s) is a novel base controller transfer function, hppi(s) is a high performance proportional-integral controller transfer function, and hplo(s) is a high performance advanced observer transfer function.
Optionally, the high performance proportional-integral controller transfer function is:
HPPI(s)＝KHPPI[1+HEI(s)],
where HPPI(s) is a high performance proportional-integral controller transfer function, KHPPIFor the proportional gain of the cascaded proportional controller, HEI(s) is the high efficiency integrator transfer function, THEIIs an efficient integrator time constant.
The high performance advanced observer transfer function is:
where HPLO(s) is a high performance lead observer transfer function, THPLOIs a high performance lead observer time constant.
In one embodiment, for a process module, a bit-domain scale observer of the present application is used to observe the process output of the process at a unit step input, as shown in FIG. 5.
It should be noted that, in the above formula, s represents a laplacian, and those skilled in the art can understand that details are not described herein.
In the prior art, a Z-N method is used for acquiring Z-N parameters of a process, the Z-N parameters are used for setting parameters of a novel basic controller, and the parameter setting method of the novel basic controller comprises the following steps
Wherein, KHPPIProportional gain, K, for cascaded proportional controllersZ-NIs the gain of the Z-N method, THEITime constant, T, of a high-efficiency integratorZ-NIs the time constant of the Z-N method, τZ-NIs the pure lag time constant of the Z-N method, THPLOIs the time constant of the high performance lead observer.
According to the process module transfer function and formula (4), the new basic controller parameters are obtained as follows: proportional gain K of cascade proportional controllerHPPI1.0, high efficiency integrator time constant THEI590s, high Performance advanced observer time constant THPLO250 s. Setting the high judgment value A to 0.2, the low judgment value A to 0.18, the high judgment value B to 0.4, the low judgment value B to 0.38, the high judgment value C to 0.6, the low judgment value C to 0.58, the high judgment value D to 0.8, the low judgment value D to 0.78, setting the range control amount to 0.2 and setting the gain of the proportional regulator to 0.75. The setting process is given as unit step at the beginning of time 0s, the external disturbance is set as unit step at the beginning of time 2000s, the input bit domain proportion observation signal is set as 1 at the beginning of time 1500s, and the simulation is obtainedExperimental results, as shown in fig. 6, fig. 6 is a simulation experimental result of an embodiment of the novel basic controller system of the present application.
In FIG. 6, PVNFC(t) Process output, PV, of the control Process of the existing novel basic controllerNFC+PNPOAnd (t) is the process output of the control process of the novel basic controller plus-field proportional observer. As is apparent from fig. 6, a novel basic controller plus domain scale observer significantly improves the suppression performance of external disturbances. A novel basic controller position-adding domain proportion observer is mainly suitable for a constant value control system, namely, the process is given to be constant, and most control systems of thermal power generating units belong to the constant value control system.
The novel basic controller position adding domain proportion observer is applied to optimization of a secondary superheated steam temperature control system of a 1000MW thermal power generating unit. Wherein the control characteristics obtained by the new basic controller of the prior art are shown in figure 7. The control characteristics obtained by adopting the novel basic controller plus domain proportion observer are shown in fig. 8.
Fig. 7 shows that with the existing new basic controller, the given deviation of the secondary superheated steam temperature from the secondary superheated steam temperature is +9.5 ℃/-6.3 ℃ in the given trend range. Fig. 8 shows that, in the trend range given by the new basic controller plus domain proportional observer of the present application, the deviation given by the secondary superheated steam temperature relative to the secondary superheated steam temperature is +5.9 ℃/-4.5 ℃.
In conclusion, a bit domain scale observer makes a major breakthrough in the current observation mechanism, and a novel basic controller plus bit domain scale observer obviously improves the suppression performance on external disturbance.
The application provides a bit domain proportion observer and a novel basic controller system, wherein the bit domain proportion observer comprises an input selection module for receiving an input signal and a bit domain control quantity, the input signal is a deviation signal of a secondary superheated steam temperature given signal and a secondary superheated steam temperature signal of a thermal power unit, and the secondary superheated steam temperature given signal and the secondary superheated steam temperature signal contain per unit processing; the pulse unit is used for receiving an input signal and an input bit domain proportion observation signal and outputting a pulse signal; the accumulator is used for receiving the output signal and the pulse signal of the input selection module, accumulating the output signal of the input selection module for 1 time according to each 1 pulse signal and outputting the accumulated output signal; and the proportion regulator is used for carrying out proportion regulation on the accumulated output to finally obtain an output signal of the bit domain proportion observer. Through the mode, the method and the device can be applied to process control of the thermal power generating unit, compared with the prior art, the suppression performance of external disturbance is improved, and the method and the device are a major breakthrough in the current observation mechanism.
It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. In addition, for convenience of description, only a part of structures related to the present application, not all of the structures, are shown in the drawings. The step numbers used herein are also for convenience of description only and are not intended as limitations on the order in which the steps are performed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (9)
1. A bit-domain scale observer, comprising:
the input selection module is used for receiving an input signal and a bit domain control quantity, wherein the input signal is a deviation signal of a secondary superheated steam temperature given signal and a secondary superheated steam temperature signal of the thermal power generating unit, and the secondary superheated steam temperature given signal and the secondary superheated steam temperature signal contain per unit processing;
the input selection module comprises:
a multiplier, a first input end is used for receiving the bit domain control quantity, a second input end is used for receiving a-1 value, and an output end is used for outputting the product of the bit domain control quantity and the-1 value;
a greater than 0 judger for receiving an input signal, wherein when the input signal is greater than 0, the output signal is 1, and when the input signal is less than or equal to 0, the output signal is 0;
a 2-input selector, having a first input end for receiving the bit-domain control quantity, a second input end for receiving an output signal of the multiplier, and a selection control end for selecting, according to the output signal greater than 0 judger, a signal at the first input end or a signal at the second input end as an output signal of the 2-input selector, and finally obtaining an output signal of the input selection module;
the pulse unit is used for receiving an input signal and an input bit domain proportion observation signal and outputting a pulse signal;
the accumulator is used for receiving the output signal of the input selection module and the pulse signal, and accumulating the output signal of the input selection module for 1 time according to each 1 pulse signal and then outputting the accumulated signal;
and the proportion regulator is used for carrying out proportion regulation on the accumulated output to finally obtain an output signal of the bit domain proportion observer.
2. The bit-domain scale observer according to claim 1, wherein the pulse unit comprises:
the absolute value arithmetic unit is used for receiving the input signal and carrying out absolute value arithmetic on the input signal to obtain an absolute value signal;
the pulse units are connected in parallel, each group of pulse units is used for receiving the absolute value signal and selecting whether to output a pulse signal after size judgment;
the input OR logic arithmetic unit is used for receiving the output signals of each group of pulse units, and if at least one group of output signals in the pulse units are 1, the output signals of the input OR logic arithmetic unit are 1;
and the 2 input AND logic operator is used for receiving the pulse signal and the input bit domain proportion observation signal and allowing the pulse signal to be output when the input bit domain proportion observation signal is 1.
3. The bit-domain scale observer according to claim 2, wherein the pulse unit comprises:
the greater than judger is used for receiving the absolute value signal and the high judgment value, and outputting a signal to be 1 when the absolute value signal is greater than the high judgment value, otherwise, outputting a signal to be 0;
a less than judger for receiving the absolute value signal and a low judgment value, and outputting a signal of 1 when the absolute value signal is less than the low judgment value, otherwise outputting a signal of 0;
the touch 1 input end of the S-R trigger receives the output signal larger than the judger, the touch 0 input end of the S-R trigger receives the output signal smaller than the judger, when the output signal larger than the judger is 1, the output signal of the S-R trigger is 1 and is kept, when the output signal smaller than the judger is 1, the output signal of the S-R trigger is 0 and is kept, and the output signal larger than the judger and the output signal smaller than the judger do not exist and are simultaneously 1;
and the pulse trigger is used for receiving the output signal of the S-R trigger, outputting a pulse signal if the output signal of the S-R trigger jumps from 0 to 1, and the time width of the pulse signal is 1 digital operation period.
4. The utility model provides a novel basic controller system, is applied to thermal power generating unit's second grade superheated steam temperature control system and optimizes, a serial communication port, include:
the bit domain scale observer of any one of claims 1-3;
the negative feedback link is used for receiving the process given signal at the input end and receiving the output signal of the high-performance advanced observer at the negative feedback end;
the high-performance proportional-integral controller is connected with the bit domain proportional observer in parallel, the input end of the high-performance proportional-integral controller receives an output signal of the negative feedback link, and the output end of the high-performance proportional-integral controller is connected with the first adder;
the process module receives the output signal of the first adder, and the output end of the process module is connected with the second adder; the input end of the second adder also receives an output signal which is input into an external interference coupling model through unit step external interference, and the output of the second adder is process output;
the input end of the high-performance advanced observer receives the process output, and the output end of the high-performance advanced observer is connected with the negative feedback end of the negative feedback link.
5. The novel base controller system of claim 4, wherein the novel base controller transfer function is:
NFC(s)＝HPPI(s)HPLO(s)
wherein NFC(s) is the novel base controller transfer function, HPPI(s) is a high performance proportional-integral controller transfer function, and HPLO(s) is a high performance advanced observer transfer function.
6. The novel basic controller system of claim 5, wherein the high performance proportional-integral controller transfer function is:
HPPI(s)＝KHPPI[1+HEI(s)],
wherein HPPI(s) is the high-performance proportional-integral controller transfer function, KHPPIFor the proportional gain of the cascaded proportional controller, HEI(s) is the high efficiency integrator transfer function, THEIIs an efficient integrator time constant.
7. The novel base controller system of claim 5, wherein the high performance lead observer transfer function is:
wherein HPLO(s) is the high performance advanced observer transfer function, THPLOIs a high performance lead observer time constant.
8. The novel basic controller system of claim 4, wherein the transfer function P(s) of the process module is:
9. the novel basic controller system according to claim 4, wherein the transfer function EDCM(s) of the external disturbance coupling model is:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110447242.5A CN113156862B (en) | 2021-04-23 | 2021-04-23 | Bit-domain proportional observer and novel basic controller system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110447242.5A CN113156862B (en) | 2021-04-23 | 2021-04-23 | Bit-domain proportional observer and novel basic controller system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113156862A CN113156862A (en) | 2021-07-23 |
| CN113156862B true CN113156862B (en) | 2022-06-17 |
Family
ID=76870446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110447242.5A Active CN113156862B (en) | 2021-04-23 | 2021-04-23 | Bit-domain proportional observer and novel basic controller system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113156862B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9595896B1 (en) * | 2015-12-16 | 2017-03-14 | Rockwell Automation Technologies, Inc. | Methods and systems for sensorless closed loop motor speed and torque control |
| CN109932898A (en) * | 2019-03-29 | 2019-06-25 | 广东电网有限责任公司 | A kind of adjustable look-ahead device |
| CN110442026A (en) * | 2019-08-16 | 2019-11-12 | 北京工商大学 | Extended state observer, disturbance rejection control system and design method based on error correction |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4411796B2 (en) * | 2001-04-27 | 2010-02-10 | 富士電機システムズ株式会社 | Control system, observer and control method for induction motor drive without speed sensor |
| CN108732924B (en) * | 2018-08-21 | 2021-03-12 | 广东电网有限责任公司 | Advanced cascade control method and device |
| CN109521786A (en) * | 2019-01-23 | 2019-03-26 | 南京邮电大学 | Quadrotor drone Sliding Mode Attitude control method based on Proportional integral observer |
| CN109901385B (en) * | 2019-03-19 | 2023-03-17 | 广东电网有限责任公司 | Advanced observation method and device |
| CN111552177A (en) * | 2020-04-22 | 2020-08-18 | 深圳市科润宝实业有限公司 | Method and device for improving performance of controller, computer equipment and storage medium |
-
2021
- 2021-04-23 CN CN202110447242.5A patent/CN113156862B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9595896B1 (en) * | 2015-12-16 | 2017-03-14 | Rockwell Automation Technologies, Inc. | Methods and systems for sensorless closed loop motor speed and torque control |
| CN109932898A (en) * | 2019-03-29 | 2019-06-25 | 广东电网有限责任公司 | A kind of adjustable look-ahead device |
| CN110442026A (en) * | 2019-08-16 | 2019-11-12 | 北京工商大学 | Extended state observer, disturbance rejection control system and design method based on error correction |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113156862A (en) | 2021-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Zhang et al. | New results on $ H_ {\infty} $ filtering for fuzzy time-delay systems | |
| Tan et al. | H∞ and L2-to-L∞ gain control of linear parameter-varying systems with parameter-varying delays | |
| Çelik et al. | Enhanced speed control of a DC servo system using PI+ DF controller tuned by stochastic fractal search technique | |
| CN103760768A (en) | Generator set multivariable system identification method based on normal operating data | |
| CN113156862B (en) | Bit-domain proportional observer and novel basic controller system | |
| CN110048410A (en) | Realize the frequency conversion load control method of network of ship stable operation | |
| Wróbel et al. | Continuous and finite set model predictive control of induction motor drive | |
| CN108110779A (en) | Energy-storage system is to the response method of plant load deviation in a kind of power station | |
| CN115149873B (en) | Servo motor set control method based on neural network model and related equipment | |
| CN116184811A (en) | Engineering reconstruction feedback controller, equipment and storage medium | |
| CN105573269B (en) | The parameter monitoring system and method for semiconductor manufacturing board | |
| Duan et al. | A simple tuning method for fuzzy PID control | |
| Sun et al. | Delay-dependent H∞ control for LPV systems with time delays | |
| Lipp | The application of a fuzzy Petri net for controlling complex industrial processes | |
| Park et al. | Decentralized output-feedback controller for uncertain large-scale nonlinear systems using higher-order switching differentiator | |
| Verma et al. | Fuzzy gain scheduled automatic generation control of two area multi unit power system | |
| Liu et al. | PID-MPC Based Automatic Voltage Regulator Design in Wide-Area Interconnect Power System | |
| CN110703690A (en) | Operation method of intelligent control and monitoring system for machining process | |
| CN108400738B (en) | Modular motor control method and device | |
| Daftari et al. | Analysing stability of time delayed synchronous generator and designing optimal stabilizer fractional order PID controller using partical swarm optimization technique | |
| CN108733910A (en) | A method of realizing POWER SYSTEM STATE equation automatic deduction | |
| Liu et al. | Multiple model internal model control based on fuzzy membership function | |
| CN116984665B (en) | Milling system based on squirrel-cage asynchronous motor and fuzzy logic control method | |
| CN108983597A (en) | A kind of method and device of approximation purely retarded | |
| Mureşan et al. | Control of the 18O isotope separation process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |