CN113141204B - Feedback channel multiplexing method and device - Google Patents
Feedback channel multiplexing method and device Download PDFInfo
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- CN113141204B CN113141204B CN202010054859.6A CN202010054859A CN113141204B CN 113141204 B CN113141204 B CN 113141204B CN 202010054859 A CN202010054859 A CN 202010054859A CN 113141204 B CN113141204 B CN 113141204B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0619—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal using feedback from receiving side
- H04B7/0621—Feedback content
- H04B7/0623—Auxiliary parameters, e.g. power control [PCB] or not acknowledged commands [NACK], used as feedback information
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0619—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal using feedback from receiving side
- H04B7/0636—Feedback format
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0619—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal using feedback from receiving side
- H04B7/0652—Feedback error handling
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Abstract
The application discloses a feedback channel multiplexing method and a feedback channel multiplexing device, aiming at the problem of low utilization rate of a feedback channel caused by long-time occupation of the feedback channel by a DPD process, the method comprises the following steps: the FPGA calls a feedback channel, and after corresponding first feedback data are collected, the first feedback data are sent to the DSP, so that the DSP calculates a first parameter; the FPGA triggers the ASIC to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired feedback channel control right so as to generate a second parameter for carrying out local oscillation and mirror image calibration; and when the FPGA determines that the first parameter is calculated, performing predistortion processing on the first transmitting channel based on the first parameter. In the method, after the FPGA acquires the corresponding feedback data, the ASIC is triggered to execute the specified operation, so that the utilization rate of the feedback channel is effectively improved, the local oscillator and mirror image calibration flow is ensured to be carried out in real time, and the local oscillator and mirror image calibration performance of each transmitting channel is improved.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a feedback channel multiplexing method and apparatus.
Background
With the rapid development of communication technology, Multi-Input Multi-Output (MIMO) technology has formed a basic consensus in the industry, and Multi-channel base stations are becoming mainstream. At present, a radio frequency channel needs to call a feedback channel when performing Digital Pre-Distortion (DPD), Output Power Detection (OPD), Reflected Power Detection (RPD) and other processes, and a method of multiplexing one feedback channel by multiple transmission channels in a time-sharing manner is generally adopted because the number of channels is large and the area of a board is limited.
At present, the feedback channel multiplexing method of the multi-channel base station mainly includes the following two methods:
the first method comprises the following steps: and calling a feedback channel periodically.
The processes such as DPD, OPD, and RPD call the feedback channels periodically, for example, at an interval period of one hour, each transmission channel calls the feedback channels in sequence to execute the processes such as DPD, OPD, and RPD.
The second method comprises the following steps: the DPD invokes the feedback channel in real time.
In order to improve the linear performance of the power amplifier, when the feedback channel does not perform other services, the DPD calls the feedback channel in real time, and the OPD, RPD and other processes call the feedback channel periodically.
The method comprises the steps that a processor of a base station sequentially carries out DPD flows of all transmitting channels according to the sequence number of the transmitting channels, for example, when the DPD calls a feedback channel in real time, a Field Programmable Gate Array (FPGA) selects a corresponding feedback channel to collect feedback data according to an instruction sent by the processor, after the DPD flow of one transmitting channel is finished, the processor sends an antenna switching instruction, and the FPGA switches to one transmitting channel to carry out the DPD flow of one transmitting channel. If other processes in the base station need to call the feedback channel for a short time, such as OPD and RPD functions, the processor suspends DPD application, releases the feedback channel and performs other processes.
However, for the first method, since the signal bandwidth of the multi-channel base station is too wide, the feedback channel is periodically called to execute the DPD procedure, which cannot meet the linear requirement of the base station system on the power amplifier.
For the second method:
firstly, when the base station performs the DPD procedure, after the DPD procedure of one transmission channel is completed, the processor issues an antenna switching instruction, the FPGA will switch to one transmission channel to perform the DPD procedure of one transmission channel, and the channel utilization rate is too low.
Secondly, when the radio frequency channel uses an integrated zero intermediate frequency architecture, local oscillation and image interference signals exist in the transmitting channel. If local oscillation and mirror image calibration is not performed, local oscillation and mirror image effects of a transmitting channel are deteriorated, and further, Error Vector Magnitude (EVM) and Adjacent Channel Power Ratio (ACPR) indexes are deteriorated, and performance of a base station is affected. Especially in the rf high frequency band, such as 4.9G band, the local oscillator and image degradation is more severe. The periodic local oscillator and mirror image calibration cannot meet the system requirements, and local oscillator and mirror image deterioration still occurs when the radio frequency gain changes rapidly, so that only real-time local oscillator and mirror image calibration can be adopted. However, the real-time local oscillator and mirror calibration needs to occupy a large number of feedback channels, and due to the original real-time DPD requirement, the feedback channels are insufficient, and hardware can only add feedback channels for use in both, which causes the area of the board PCB to be more tense, and increases the hardware cost.
Finally, the current system master is a processor, and the processor controls the processing of each software flow. Because the processor needs to control the real-time DPD process of each transmitting channel, the processor can not be used for controlling the real-time local oscillator and mirror image calibration process of each transmitting channel, and therefore, the processor and the transmitting channel are subjected to time-sharing mutual exclusion processing through switch control on hardware. However, the processing time of each algorithm of the DPD is uncertain, and the simple mutual exclusion processing still causes the problem that the waiting time of the local oscillator and mirror image calibration process of the transmitting channel is too long, which causes the suppression index of the local oscillator and the mirror image to be not in line with the requirement, thereby affecting the system index.
It follows that a new solution needs to be devised to overcome the above drawbacks.
Disclosure of Invention
The application provides a feedback channel multiplexing method and a feedback channel multiplexing device, which are used for solving the problem of low utilization rate of a feedback channel due to the fact that a DPD process occupies the feedback channel for a long time.
The embodiment of the application provides the following specific technical scheme:
a feedback channel multiplexing method comprises the following steps:
the method comprises the steps that an FPGA (field programmable gate array) acquires a first training sequence and a first sequence number from a first flow starting instruction generated by a processor, transmits the first training sequence through a first transmitting channel corresponding to the first sequence number, calls a feedback channel and acquires corresponding first feedback data;
the FPGA sends the first feedback data to a Digital Signal Processor (DSP), so that the DSP calculates a first parameter based on the first feedback data and the training sequence;
the FPGA triggers an application specific integrated chip ASIC to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired feedback channel control right so as to generate a second parameter for carrying out local oscillation and mirror image calibration;
and when the FPGA determines that the first parameter calculation is completed, performing predistortion processing on the first transmitting channel based on the first parameter.
Optionally, the invoking, by the FPGA, a feedback channel, acquiring corresponding first feedback data, and then sending the first feedback data to the digital signal processor DSP, so that before the DSP calculates the first parameter based on the first feedback data and the training sequence, the method further includes:
when the FPGA determines that the first feedback data is completely acquired, releasing the feedback channel and acquiring a feedback channel control right, wherein the feedback channel control right is used for selecting and calling a transmitting channel of the feedback channel;
after the FPGA pre-distorts the first transmit channel based on the first parameter, the method further includes:
and when the FPGA receives a first flow ending instruction generated by the processor, the control right of the feedback channel is released.
Optionally, the FPGA, based on the acquired control right of the feedback channel, triggers the ASIC to perform a designated operation on each transmission channel and the feedback channel, so as to generate a second parameter for local oscillation and mirror image calibration, specifically including:
the FPGA determines a switching interval and a switching sequence based on the acquired feedback channel control right and each transmitting channel arranged in the system;
the FPGA sequentially switches the transmitting channels according to the time interval and the switching sequence, and triggers the ASIC to execute the following operations during each switching: determining a transmitting channel corresponding to a feedback channel currently, transmitting a preset second training sequence through the corresponding transmitting channel, calling the feedback channel, and acquiring corresponding second feedback data, wherein the ASIC calculates a second parameter of the corresponding transmitting channel by using the second feedback data, and performs local oscillation and mirror image calibration on the corresponding transmitting channel by using the second parameter.
Optionally, the determining, by the FPGA, that the calculation of the first parameter is completed specifically includes:
and the FPGA determines that the calculation of the first parameter is completed and acquires the first parameter when receiving a calculation completion instruction returned by the DSP within a preset flow time limit, wherein the calculation completion instruction comprises a storage address of the first parameter.
Optionally, the first parameter at least includes one or any combination of a temperature compensation coefficient, a frequency compensation coefficient, and a generated power compensation coefficient.
A feedback channel multiplexing device, comprising:
a memory for storing executable instructions;
a processor for reading and executing the executable instructions stored in the memory, performing the following processes:
acquiring a first training sequence and a first sequence number from a first flow starting instruction generated by a processor, transmitting the first training sequence through a first transmitting channel corresponding to the first sequence number, calling a feedback channel, and acquiring corresponding first feedback data;
sending the first feedback data to a Digital Signal Processor (DSP) so that the DSP calculates a first parameter based on the first feedback data and the training sequence;
triggering an application specific integrated chip ASIC to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired control right of the feedback channel so as to generate a second parameter for carrying out local oscillation and mirror image calibration;
and when the first parameter is determined to be calculated, performing predistortion processing on the first transmitting channel based on the first parameter.
Optionally, a feedback channel is called, after corresponding first feedback data is collected, the first feedback data is sent to the DSP, so that before the DSP calculates a first parameter based on the first feedback data and the training sequence, the processor is further configured to:
when the first feedback data is determined to be acquired, releasing the feedback channel, and acquiring a feedback channel control right, wherein the feedback channel control right is used for selecting and calling a transmitting channel of the feedback channel;
after pre-distorting the first transmit channel based on the first parameter, the processor is further configured to:
and when a first flow ending instruction generated by the processor is received, releasing the control right of the feedback channel.
Optionally, when triggering the ASIC to execute a designated operation for each transmission channel and the feedback channel based on the acquired feedback channel control right to generate a second parameter for local oscillation and mirror image calibration, the processor is specifically configured to:
determining a switching interval and a switching sequence based on the acquired feedback channel control right and each transmitting channel set in the system;
and sequentially switching the transmitting channels according to the time interval and the switching sequence, and triggering the ASIC to execute the following operations during each switching: determining a transmitting channel corresponding to a feedback channel currently, transmitting a preset second training sequence through the corresponding transmitting channel, calling the feedback channel, and acquiring corresponding second feedback data, wherein the ASIC calculates a second parameter of the corresponding transmitting channel by using the second feedback data, and performs local oscillation and mirror image calibration on the corresponding transmitting channel by using the second parameter.
Optionally, when it is determined that the calculation of the first parameter is completed, the processor is specifically configured to:
and determining that the calculation of the first parameter is completed and acquiring the first parameter when a calculation completion instruction returned by the DSP is received within a preset flow time limit, wherein the calculation completion instruction comprises a storage address of the first parameter.
Optionally, the first parameter at least includes one or any combination of a temperature compensation coefficient, a frequency compensation coefficient, and a generated power compensation coefficient.
A feedback channel multiplexing device, comprising:
the acquisition unit is used for acquiring a first training sequence and a first sequence number from a first flow starting instruction generated by a processor, transmitting the first training sequence through a first transmitting channel corresponding to the first sequence number, calling a feedback channel and acquiring corresponding first feedback data;
a sending unit, configured to send the first feedback data to a digital signal processor DSP, so that the DSP calculates a first parameter based on the first feedback data and the training sequence;
the control unit is used for triggering the ASIC to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired control right of the feedback channel so as to generate a second parameter for carrying out local oscillation and mirror image calibration;
and the processing unit is used for performing predistortion processing on the first transmitting channel based on the first parameter when the first parameter is determined to be calculated.
A storage medium having instructions which, when executed by a processor, enable the processor to perform a feedback channel multiplexing method as claimed in any one of the preceding claims.
In the embodiment of the application, the FPGA calls the feedback channel, acquires corresponding first feedback data, and then sends the first feedback data to the DSP, so that the DSP calculates a first parameter; then, the FPGA triggers the ASIC to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired control right of the feedback channel so as to generate a second parameter for carrying out local oscillation and mirror image calibration; and when the FPGA determines that the first parameter is calculated, performing predistortion processing on the first transmitting channel based on the first parameter. Therefore, after the FPGA acquires corresponding feedback data, the ASIC is triggered to execute specified operation so as to generate a second parameter for local oscillator and mirror image calibration, the utilization rate of a feedback channel can be effectively improved, the local oscillator and mirror image calibration flow is carried out in real time while the first flow is carried out in real time, the local oscillator and mirror image calibration performance of each transmitting channel is improved, and the system performance of the base station is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a feedback channel multiplexing method provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a feedback channel multiplexing apparatus provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of a feedback channel multiplexing apparatus provided in an embodiment of the present application.
Detailed Description
Aiming at the problems that in the prior art, as the DPD process occupies the feedback channel for a long time, the utilization rate of the feedback channel is low, and local oscillation and mirror image calibration cannot be carried out simultaneously, in order to improve the utilization rate of the feedback channel and optimize the system performance, in the embodiment of the application, a solution for feedback channel multiplexing is provided.
The scheme is as follows: the method comprises the steps that an FPGA calls a feedback channel, after corresponding first feedback data are collected, the first feedback data are sent to a Digital Signal Processor (DSP) to be calculated, then the FPGA triggers an Application Specific Integrated Circuit (ASIC) to execute specified operation aiming at each transmitting channel and the feedback channel based on the obtained feedback channel control right, so that second parameters for local oscillation and mirror image calibration are generated, and then when the FPGA determines that the first parameters are calculated, pre-distortion processing is carried out on the first transmitting channel.
In order to make the technical solutions of the present application better understood by those of ordinary skill in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
Referring to fig. 1, in the embodiment of the present application, a process of multiplexing a feedback channel is as follows:
step S101: the FPGA acquires a first training sequence and a first sequence number from a first flow starting instruction generated by a processor, transmits the first training sequence through a first transmitting channel corresponding to the first sequence number, calls a feedback channel and acquires corresponding first feedback data.
In the embodiment of the present application, the first procedure is taken as a DPD procedure for example, and for convenience of description, all the transmit channels appearing hereinafter are multiplexed with one feedback channel 1.
For example, the FPGA acquires a first training sequence and a first sequence number from a first flow start instruction generated by the processor, where the first sequence number corresponds to the transmission channel 1, and then transmits the first training sequence through a first transmission channel corresponding to the first sequence number, that is, the transmission channel 1, and invokes the feedback channel 1 to acquire corresponding first feedback data.
Further, when the FPGA determines that the first feedback data is completely acquired, the feedback channel is released, and a feedback channel control right is acquired, wherein the feedback channel control right is used for selecting and calling a transmitting channel of the feedback channel.
For example, assuming that the transmitting channel 1, the transmitting channel 2, the transmitting channel 3, and the transmitting channel 4 multiplex the feedback channel 1, when the FPGA determines that the first feedback data is completely acquired, the FPGA releases the feedback channel 1 and obtains a feedback channel control right of the feedback channel 1, where the feedback channel control right is used to select and call the transmitting channel of the feedback channel 1.
Step S102: the FPGA sends the first feedback data to the DSP, so that the DSP calculates a first parameter based on the first feedback data and the training sequence.
In the embodiment of the present application, the first parameter includes, but is not limited to, a temperature compensation coefficient, a frequency compensation coefficient, a generated power compensation coefficient, and may also be any combination of the above.
For example, assuming that the first parameter is a temperature compensation coefficient, a frequency compensation coefficient, and a generated power compensation coefficient, the FPGA sends the first feedback data to the DSP, so that the DSP calculates the temperature compensation coefficient, the frequency compensation coefficient, and the generated power compensation coefficient based on the first feedback data and the training sequence.
Step S103: and the FPGA triggers the ASIC to execute specified operation aiming at each transmitting channel and each feedback channel based on the acquired control right of the feedback channel so as to generate a second parameter for carrying out local oscillation and mirror image calibration.
Specifically, the FPGA determines the switching interval and the switching sequence based on the acquired control right of the feedback channel and each transmission channel set in the system.
For example, the FPGA determines that the switching interval is 500 milliseconds based on the acquired feedback channel control right of the feedback channel 1 and the transmitting channel 1, the transmitting channel 2, the transmitting channel 3, and the transmitting channel 4 set in the system, and determines that the switching sequence is the transmitting channel 4, the transmitting channel 3, the transmitting channel 2, and the transmitting channel 1 in turn.
Further, the FPGA switches each transmitting channel according to the time interval and the switching sequence, and triggers the ASIC to perform the following operations each time switching occurs: and determining a transmitting channel currently corresponding to the feedback channel, transmitting a preset second training sequence through the corresponding transmitting channel, calling the feedback channel, and acquiring corresponding second feedback data, wherein the ASIC calculates a second parameter of the corresponding transmitting channel by using the second feedback data, and performs local oscillation and mirror image calibration on the corresponding transmitting channel by using the second parameter.
For example, the FPGA switches according to the sequence of the transmitting channel 4, the transmitting channel 3, the transmitting channel 2, and the transmitting channel 1 every 500 milliseconds according to the time interval and the switching sequence, first, when switching to the transmitting channel 4, the ASIC is triggered to determine to transmit the preset second training sequence 1 through the transmitting channel 4 and call the feedback channel 1, and acquire the second feedback data 1, then, when switching to the transmitting channel 3, the ASIC is triggered to determine to transmit the preset second training sequence 2 through the transmitting channel 3 and call the feedback channel 1 and acquire the second feedback data 2, then, when switching to the transmitting channel 2, the ASIC is triggered to determine to transmit the preset second training sequence 3 through the transmitting channel 2 and call the feedback channel 1 and acquire the second feedback data 3, and finally, when switching to the transmitting channel 1, the ASIC is triggered to determine to transmit the preset second training sequence 4 through the transmitting channel 1, and invokes the feedback channel 1 to collect the second feedback data 4.
Step S104: and when the FPGA determines that the calculation of the first parameter is finished, carrying out predistortion treatment on the first transmitting channel based on the first parameter.
Specifically, the FPGA determines that the calculation of the first parameter is completed and acquires the first parameter when receiving a calculation completion instruction returned by the DSP within a preset flow time limit, wherein the calculation completion instruction includes a storage address of the first parameter.
For example, the FPGA determines that the calculation of the first parameter is completed when a calculation completion instruction returned by the DSP is received within 10 seconds of a preset flow time limit, the calculation completion instruction includes a storage address 1 of the first parameter, and the FPGA acquires the first parameter based on the storage address 1.
Further, the FPGA performs predistortion processing on the first transmit channel based on the first parameter.
For example, assuming that the temperature compensation coefficient, the frequency compensation coefficient, and the generated power compensation coefficient in the first parameter are 0.01, 0.02, and 0.03, respectively, the FPGA performs predistortion processing on the transmission channel 1 based on the temperature compensation coefficient 0.01, the frequency compensation coefficient 002, and the generated power compensation coefficient 0.03.
Further, when receiving a first flow ending instruction generated by the processor, the FPGA releases the control right of the feedback channel.
For example, when the FPGA receives a first flow end instruction generated by the processor, the feedback channel control right of the feedback channel 1 is released.
Based on the same inventive concept, in the embodiment of the present application, a feedback channel multiplexing apparatus is provided, as shown in fig. 2, and at least includes:
a memory 201 for storing executable instructions;
a processor 202 for reading and executing executable instructions stored in the memory, and performing the following processes:
acquiring a first training sequence and a first sequence number from a first flow starting instruction generated by a processor, transmitting the first training sequence through a first transmitting channel corresponding to the first sequence number, calling a feedback channel, and acquiring corresponding first feedback data;
sending the first feedback data to a Digital Signal Processor (DSP) so that the DSP calculates a first parameter based on the first feedback data and the training sequence;
triggering an Application Specific Integrated Chip (ASIC) to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired control right of the feedback channel so as to generate a second parameter for carrying out local oscillation and mirror image calibration;
and when the first parameter is determined to be calculated, performing predistortion processing on the first transmitting channel based on the first parameter.
Optionally, a feedback channel is called, and after corresponding first feedback data is acquired, the first feedback data is sent to the DSP, so that before the DSP calculates a first parameter based on the first feedback data and the training sequence, the processor 202 is further configured to:
when the first feedback data is determined to be acquired, releasing the feedback channel and acquiring a feedback channel control right, wherein the feedback channel control right is used for selecting and calling a transmitting channel of the feedback channel;
after pre-distorting the first transmit channel based on the first parameter, the processor 202 is further configured to:
and when a first flow ending instruction generated by the processor is received, releasing the control right of the feedback channel.
Optionally, when triggering the ASIC to perform a designated operation on each transmission channel and the feedback channel based on the obtained control right of the feedback channel, so as to generate a second parameter for local oscillation and mirror calibration, the processor 202 is specifically configured to:
determining a switching interval and a switching sequence based on the acquired feedback channel control right and each transmitting channel set in the system;
and sequentially switching the transmitting channels according to the time interval and the switching sequence, and triggering the ASIC to execute the following operations during each switching: determining a transmitting channel corresponding to a feedback channel currently, transmitting a preset second training sequence through the corresponding transmitting channel, calling the feedback channel, and acquiring corresponding second feedback data, wherein the ASIC calculates a second parameter of the corresponding transmitting channel by using the second feedback data, and performs local oscillation and mirror image calibration on the corresponding transmitting channel by using the second parameter.
Optionally, when it is determined that the calculation of the first parameter is completed, the processor 202 is specifically configured to:
and determining that the calculation of the first parameter is completed and acquiring the first parameter when a calculation completion instruction returned by the DSP is received within a preset flow time limit, wherein the calculation completion instruction comprises a storage address of the first parameter.
Optionally, the first parameter at least includes one or any combination of a temperature compensation coefficient, a frequency compensation coefficient, and a generated power compensation coefficient.
A transceiver 203 for receiving and transmitting data under the control of the processor 202.
Wherein in fig. 2 the bus architecture may include any number of interconnected buses and bridges, with one or more processors, represented in particular by processor 202, and various circuits of memory, represented by memory 201, being linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The transceiver 203 may be a plurality of elements, including a transmitter and a transceiver, providing a means for communicating with various other apparatus over a transmission medium. The processor 202 is responsible for managing the bus architecture and general processing, and the memory 201 may store data used by the processor 202 in performing operations.
Based on the same inventive concept, in the embodiment of the present application, a feedback channel multiplexing apparatus is provided, as shown in fig. 3, and at least includes: an acquisition unit 301, a transmission unit 302, a control unit 303 and a processing unit 304, wherein,
an acquisition unit 301, configured to obtain a first training sequence and a first sequence number from a first flow start instruction generated by a processor, transmit the first training sequence through a first transmission channel corresponding to the first sequence number, call a feedback channel, and acquire corresponding first feedback data;
a sending unit 302, configured to send the first feedback data to a digital signal processor DSP, so that the DSP calculates a first parameter based on the first feedback data and the training sequence;
a control unit 303, configured to trigger an ASIC to perform a specified operation on each transmission channel and the feedback channel based on the acquired control right of the feedback channel, so as to generate a second parameter for local oscillation and mirror image calibration;
a processing unit 304, configured to perform predistortion processing on the first transmission channel based on the first parameter when it is determined that the first parameter is calculated.
The acquisition unit 301, the sending unit 302, the control unit 303 and the processing unit 304 cooperate with each other to achieve the functions of the apparatus in the various embodiments described above.
Based on the same inventive concept, embodiments of the present application provide a storage medium, and when instructions in the storage medium are executed by a processor, the processor is enabled to execute any one of the methods implemented by the feedback channel multiplexing apparatus in the above-described flow.
In the embodiment of the application, the FPGA calls the feedback channel, acquires corresponding first feedback data, and then sends the first feedback data to the DSP, so that the DSP calculates a first parameter; then, the FPGA triggers the ASIC to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired control right of the feedback channel so as to generate a second parameter for carrying out local oscillation and mirror image calibration; and when the FPGA determines that the first parameter is calculated, performing predistortion processing on the first transmitting channel based on the first parameter. Therefore, after the FPGA acquires corresponding feedback data, the ASIC is triggered to execute specified operation so as to generate a second parameter for local oscillator and mirror image calibration, the utilization rate of a feedback channel can be effectively improved, the local oscillator and mirror image calibration flow is carried out in real time while the first flow is carried out in real time, the local oscillator and mirror image calibration performance of each transmitting channel is improved, and the system performance of the base station is improved.
For the system/apparatus embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference may be made to some descriptions of the method embodiments for relevant points.
It is to be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any actual such relationship or order between such entities or operations.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (12)
1. A feedback channel multiplexing method, comprising:
the method comprises the steps that a Field Programmable Gate Array (FPGA) acquires a first training sequence and a first sequence number from a first flow starting instruction generated by a processor, transmits the first training sequence through a first transmitting channel corresponding to the first sequence number, calls a feedback channel and acquires corresponding first feedback data;
the FPGA sends the first feedback data to a Digital Signal Processor (DSP), so that the DSP calculates a first parameter based on the first feedback data and the training sequence;
the FPGA triggers an ASIC to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired control right of the feedback channel so as to generate a second parameter for carrying out local oscillation and mirror image calibration;
and when the FPGA determines that the first parameter calculation is completed, performing predistortion processing on the first transmitting channel based on the first parameter.
2. The method of claim 1, wherein the FPGA invoking the feedback channel, after acquiring the corresponding first feedback data, sending the first feedback data to a Digital Signal Processor (DSP), such that before the DSP calculates the first parameter based on the first feedback data and the training sequence, further comprises:
when the FPGA determines that the first feedback data is completely acquired, releasing the feedback channel and acquiring a feedback channel control right, wherein the feedback channel control right is used for selecting and calling a transmitting channel of the feedback channel;
after the FPGA pre-distorts the first transmit channel based on the first parameter, the method further includes:
and when the FPGA receives a first flow ending instruction generated by the processor, releasing the control right of the feedback channel.
3. The method according to claim 1 or 2, wherein the FPGA, based on the acquired control right of the feedback channel, triggers an application specific integrated chip ASIC to perform a specified operation for each transmission channel and the feedback channel to generate a second parameter for local oscillation and mirror calibration, specifically comprising:
the FPGA determines a switching interval and a switching sequence based on the acquired feedback channel control right and each transmitting channel arranged in the system;
the FPGA sequentially switches the transmitting channels according to the switching intervals and the switching sequence, and triggers the ASIC to execute the following operations during each switching: determining a transmitting channel corresponding to a feedback channel currently, transmitting a preset second training sequence through the corresponding transmitting channel, calling the feedback channel, and acquiring corresponding second feedback data, wherein the ASIC calculates a second parameter of the corresponding transmitting channel by using the second feedback data, and performs local oscillation and mirror image calibration on the corresponding transmitting channel by using the second parameter.
4. The method according to claim 1 or 2, wherein the FPGA determining that the first parameter calculation is completed specifically comprises:
and the FPGA determines that the calculation of the first parameter is completed and acquires the first parameter when receiving a calculation completion instruction returned by the DSP within a preset flow time limit, wherein the calculation completion instruction comprises a storage address of the first parameter.
5. The method of claim 4, wherein the first parameter comprises at least one of a temperature compensation coefficient, a frequency compensation coefficient, a generated power compensation coefficient, or any combination thereof.
6. A feedback channel multiplexing device, comprising:
a memory for storing executable instructions;
a processor for reading and executing the executable instructions stored in the memory, performing the following processes:
acquiring a first training sequence and a first sequence number from a first flow starting instruction generated by a processor, transmitting the first training sequence through a first transmitting channel corresponding to the first sequence number, calling a feedback channel, and acquiring corresponding first feedback data;
sending the first feedback data to a Digital Signal Processor (DSP) so that the DSP calculates a first parameter based on the first feedback data and the training sequence;
triggering an application specific integrated chip ASIC to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired control right of the feedback channel so as to generate a second parameter for carrying out local oscillation and mirror image calibration;
and when the first parameter is determined to be calculated, performing predistortion processing on the first transmitting channel based on the first parameter.
7. The apparatus of claim 6, wherein a feedback channel is invoked, wherein after acquiring the corresponding first feedback data, the first feedback data is sent to a DSP, such that before the DSP calculates the first parameter based on the first feedback data and the training sequence, the processor is further configured to:
when the first feedback data is determined to be acquired, releasing the feedback channel, and acquiring a feedback channel control right, wherein the feedback channel control right is used for selecting and calling a transmitting channel of the feedback channel;
after pre-distorting the first transmit channel based on the first parameter, the processor is further configured to:
and when a first flow ending instruction generated by the processor is received, releasing the control right of the feedback channel.
8. The apparatus according to claim 6 or 7, wherein, when triggering the ASIC to perform a specified operation for each transmit channel and the feedback channel based on the acquired control right of the feedback channel to generate the second parameter for local oscillation and mirror calibration, the processor is specifically configured to:
determining a switching interval and a switching sequence based on the acquired feedback channel control right and each transmitting channel set in the system;
and sequentially switching the transmitting channels according to the switching intervals and the switching sequence, and triggering the ASIC to execute the following operations during each switching: and determining a transmitting channel corresponding to the feedback channel currently, transmitting a preset second training sequence through the corresponding transmitting channel, calling the feedback channel, and acquiring corresponding second feedback data, wherein the ASIC adopts the second feedback data to calculate a second parameter of the corresponding transmitting channel, and adopts the second parameter to carry out local oscillation and mirror image calibration on the corresponding transmitting channel.
9. The apparatus of claim 6 or 7, wherein the processor is specifically configured to, upon determining that the first parameter calculation is complete:
and determining that the calculation of the first parameter is completed and acquiring the first parameter when a calculation completion instruction returned by the DSP is received within a preset flow time limit, wherein the calculation completion instruction comprises a storage address of the first parameter.
10. The apparatus of claim 9, wherein the first parameter comprises at least one of a temperature compensation coefficient, a frequency compensation coefficient, a generated power compensation coefficient, or any combination thereof.
11. A feedback channel multiplexing device, comprising:
the device comprises an acquisition unit, a processing unit and a feedback unit, wherein the acquisition unit is used for acquiring a first training sequence and a first serial number from a first flow starting instruction generated by a processor, transmitting the first training sequence through a first transmission channel corresponding to the first serial number, calling a feedback channel and acquiring corresponding first feedback data;
a sending unit, configured to send the first feedback data to a digital signal processor DSP, so that the DSP calculates a first parameter based on the first feedback data and the training sequence;
the control unit is used for triggering the ASIC to execute specified operation aiming at each transmitting channel and the feedback channel based on the acquired control right of the feedback channel so as to generate a second parameter for carrying out local oscillation and mirror image calibration;
and the processing unit is used for performing predistortion processing on the first transmitting channel based on the first parameter when the first parameter is determined to be calculated.
12. A storage medium, wherein instructions in the storage medium, when executed by a processor, enable the processor to perform the feedback channel multiplexing method of any one of claims 1 to 5.
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