CN113138798A - Instruction execution method, device and equipment under multiple scenes and storage medium - Google Patents
Instruction execution method, device and equipment under multiple scenes and storage medium Download PDFInfo
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Abstract
The application discloses a method, a device, equipment and a storage medium for executing instructions under multiple scenes, wherein the method comprises the following steps: acquiring at least one instruction corresponding to a plurality of scenes in the current execution cycle of an execution thread; executing the at least one instruction in the current execution cycle, and if the at least one instruction comprises a delay instruction, determining a target execution cycle corresponding to a next instruction of the delay instruction; after the current execution cycle is finished, taking the next execution cycle as the current execution cycle, and returning to the step of executing at least one instruction corresponding to a plurality of scenes in the current execution cycle of the acquired execution thread; when the current execution cycle reaches the target execution cycle, the next instruction of the delay instruction is executed, and the instruction execution efficiency is greatly improved.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a storage medium for executing instructions in multiple scenarios.
Background
Generally, when a scene triggers multiple actions continuously, a delay operation needs to be added between the actions, for example, for the scene, "turn on the television box switch → wait for 3s (television on) → switch to play news", there is a delay operation waiting for 3s between turning on the television box switch and switching to play news, when the execution thread executes the instruction of the scene, the instruction to turn on the television box switch is executed first, then the delay instruction waiting for 3s is executed, and finally the instruction to switch to play news is executed, and after all the instructions are executed, the instruction of the next scene is executed according to the method. Since many times the delayed instruction is executed and no effective operation is performed, the instruction execution is not efficient.
Disclosure of Invention
The embodiment of the application provides an instruction execution method, device, equipment and storage medium under multiple scenes, and can improve the efficiency of executing scene instructions.
In a first aspect, an embodiment of the present application provides an instruction execution method in multiple scenarios, including:
acquiring at least one instruction corresponding to a plurality of scenes in the current execution cycle of an execution thread;
executing the at least one instruction in the current execution cycle, and if the at least one instruction comprises a delay instruction, determining a target execution cycle corresponding to a next instruction of the delay instruction;
after the current execution cycle is finished, taking the next execution cycle as the current execution cycle, and returning to the step of executing at least one instruction corresponding to a plurality of scenes in the current execution cycle of the acquired execution thread; wherein the next instruction of the delayed instructions is executed when the current execution cycle reaches the target execution cycle.
In a second aspect, an embodiment of the present application provides an instruction execution apparatus under multiple scenarios, including a processor and a memory, where the memory stores a computer program, and the processor executes the instruction execution method under multiple scenarios when calling the computer program in the memory.
In a third aspect, an embodiment of the present application provides an electronic device, which includes a body, a power supply disposed in the body, and an instruction execution apparatus under the foregoing multiple scenarios.
In a fourth aspect, the present application further provides a computer-readable storage medium, where the computer-readable storage medium is used for storing a computer program, and when the computer program is executed by a processor, the processor is caused to implement the instruction execution method in the foregoing multiple scenarios.
The embodiment of the application provides an instruction execution method, an instruction execution device and a storage medium under multiple scenes, wherein at least one instruction corresponding to multiple scenes in a current execution cycle of an execution thread is obtained, the at least one instruction is executed, when the executed at least one instruction contains a delay instruction, a target execution cycle corresponding to a next instruction of the delay instruction is determined, and after the current execution cycle is finished, other corresponding instructions of the multiple scenes are executed in the next execution cycle.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic block diagram of an electronic device provided in an embodiment of the present application;
FIG. 2 is a flowchart illustrating steps of a method for executing instructions in multiple scenarios according to an embodiment of the present application;
FIG. 3 is a diagram illustrating a default list according to an embodiment of the present application;
fig. 4 is a schematic block diagram of an instruction execution apparatus in multiple scenarios according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The flow diagrams depicted in the figures are merely illustrative and do not necessarily include all of the elements and operations/steps, nor do they necessarily have to be performed in the order depicted. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
It is to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
When a scene triggers multiple actions continuously, delay operation is usually required to be added between the actions, for example, for the scene, "turn on the television box switch → wait for 3s (television on) → switch to play news", there is delay operation waiting for 3s between turning on the television box switch and switching to play news, when the execution thread executes the instruction of the scene, the instruction to turn on the television box switch is executed first, then the delay instruction waiting for 3s is executed, finally the instruction to switch to play news is executed again, and after all the instructions are executed, the instruction of the next scene is executed according to the method. Since many times the delayed instruction is executed and no effective operation is performed, the instruction execution is not efficient.
In order to solve the above problem, embodiments of the present application provide an instruction execution method, an apparatus, a device, and a storage medium in multiple scenarios, which are used to improve efficiency of executing a scenario instruction.
Referring to fig. 1, fig. 1 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure. As shown in fig. 1, the electronic device 100 may include a body 110, a power source 120, and a control device 130, wherein the power source 120 and the control device 130 are both disposed in the body 110, the power source 120 is connected to the control device 130, and the power source 120 is used for supplying power to the control device 130.
The control device 130 includes a processor for executing various scene instructions triggered by the electronic apparatus 100 to implement various control operations of the electronic apparatus 100.
The Processor may be a Central Processing Unit (CPU), and the Processor may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
By way of example, the electronic device 100 may include, but is not limited to, various types of electronic devices such as a smart phone, a tablet computer, a personal computer, a smart television, a smart refrigerator, an air conditioner, and the like.
It is to be understood that the above-mentioned names for the components of the electronic device are only for identification purposes, and do not limit the embodiments of the present application accordingly.
The following describes in detail an instruction execution method under multiple scenarios provided by an embodiment of the present application based on an electronic device.
Referring to fig. 2, fig. 2 is a schematic flowchart illustrating steps of a method for executing instructions under multiple scenarios according to an embodiment of the present application. The instruction execution method under multiple scenes is specifically applied to the electronic device provided by the embodiment, so that the instruction execution efficiency is improved.
As shown in fig. 2, the instruction execution method under multiple scenarios specifically includes steps S101 to S103.
S101, acquiring at least one instruction corresponding to a plurality of scenes in the current execution cycle of the execution thread.
When the electronic device triggers multiple scenes, that is, multiple instructions of the multiple scenes need to be executed by the execution thread, the execution thread sequentially executes the multiple instructions of the multiple scenes according to a preset execution cycle and the execution cycle. Specifically, according to the instruction of each scene, if the scene includes multiple instructions, the multiple instructions correspond to a sequential execution order, and at least one instruction corresponding to multiple scenes in the current execution cycle is determined, that is, at least one instruction of multiple scenes to be executed by the execution thread in the current execution cycle is determined. For example, for the first execution cycle, the first instruction corresponding to each scene is taken as the instruction to be executed by the execution thread in the first execution cycle.
At least one instruction corresponding to a plurality of scenes in the current execution cycle comprises effective instructions, for example, an instruction for opening a television box switch, an instruction for switching to news playing and the like, and the effective instructions are executed for effective operation; it is also possible that the at least one instruction corresponding to the plurality of scenarios in the current execution cycle further includes a delay instruction, for example, an instruction waiting for 3 s.
S102, executing the at least one instruction in the current execution cycle, and if the at least one instruction comprises a delay instruction, determining a target execution cycle corresponding to a next instruction of the delay instruction.
When executing the instructions, the execution thread executes the instructions of one scene, which are different from the instructions of the existing one scene, in sequence, and executes at least one instruction of the determined multiple scenes in the current execution cycle. For example, if the triggered scenario includes scenario one and scenario two, where the instruction corresponding to scenario one includes instruction one and instruction two, and the instruction corresponding to scenario two includes instruction three and instruction four. And if at least one instruction of the plurality of scenes corresponding to the current execution cycle is determined to be the first instruction and the third instruction, the execution thread executes the first instruction and the third instruction in the current execution cycle.
Optionally, when the execution thread executes the multiple instructions of the multiple determined scenes in the current execution cycle, the multiple instructions may be executed synchronously or asynchronously.
When the execution thread executes at least one instruction of a plurality of scenes in the current execution cycle, the delayed instruction may be executed or may not be executed. If the execution thread does not execute the delay instruction, that is, at least one instruction of the multiple scenes executed in the current execution cycle does not contain the delay instruction, after the current execution cycle is finished, the execution thread continues to execute other instructions of the multiple scenes corresponding to the next execution cycle.
If the execution thread executes the delay instruction, that is, at least one instruction of the plurality of scenes executed in the current execution cycle includes the delay instruction, the execution cycle corresponding to the next instruction of the delay instruction is determined according to the delay instruction. For the convenience of description, the execution cycle corresponding to the next instruction is hereinafter referred to as a target execution cycle. Optionally, the target execution cycle corresponding to the next instruction is determined according to the delay duration corresponding to the delay instruction and the cycle duration corresponding to the execution cycle. For example, if the delay time corresponding to the delay instruction is 3s, and the cycle time corresponding to the execution cycle is 1s, it is determined that the target execution cycle corresponding to the next instruction is the third execution cycle after the current execution cycle.
S103, after the current execution cycle is finished, taking the next execution cycle as the current execution cycle, and returning to the step of executing at least one instruction corresponding to a plurality of scenes in the current execution cycle of the acquired execution thread; wherein the next instruction of the delayed instructions is executed when the current execution cycle reaches the target execution cycle.
After the current execution cycle is finished, the execution thread obtains at least one instruction to be executed corresponding to the multiple scenes in the next execution cycle according to the operation of the above steps, and executes at least one other instruction in the next execution cycle. That is, the execution thread sequentially executes at least one instruction of the plurality of scenes corresponding to each execution cycle according to the execution cycle.
And along with the progress of the execution thread, when the current execution cycle reaches the target execution cycle corresponding to the next instruction, the execution thread executes the next instruction of the delayed instruction. For example, if the next instruction of the first delay instruction corresponds to the first target execution cycle and the next instruction of the second delay instruction corresponds to the second target execution cycle, the execution thread executes the next instruction of the first delay instruction when the current execution cycle reaches the first target execution cycle; when the current execution cycle reaches the second target execution cycle, the execution thread executes the next instruction of the second delay instruction.
In some embodiments, a corresponding preset list is pre-established, where the preset list includes a plurality of buffer areas, and each buffer area is used for buffering a corresponding instruction. For example, a List-type array table is established in redis with a key of delay _ command _ { id }, where id is a unique address identifier corresponding to each cache region, and optionally the value of id is incremented from 0.
Optionally, a quotient m of the delay duration divided by the cycle duration is calculated according to the delay duration corresponding to the delay instruction and the cycle duration corresponding to each execution cycle of the execution thread, and then a preset list including m cache regions is established. For example, based on the fact that the maximum delay time between instructions does not exceed 60 seconds under normal conditions, the delay time corresponding to the delay instruction is set to be 60s, and the cycle time corresponding to the execution cycle of the execution thread is set to be 1s, a preset list including 60 cache regions is established, as shown in fig. 3. And traversing the preset list by the execution thread according to the execution cycle, and sequentially polling each cache region in the preset list.
If at least one instruction executed in the current execution cycle comprises a delay instruction, caching the next instruction of the delay instruction to a corresponding target cache region in a preset list. And when the current execution cycle reaches the target execution cycle, the execution thread polls a target cache region of a preset list and executes a next instruction cached in the target cache region.
In some embodiments, based on the current cache region polled by the execution thread in the current execution cycle, after determining that the target execution cycle has elapsed, the execution thread will poll the cache region, determine the cache region as the target cache region, and cache the next instruction of the delayed instruction into the target cache region.
In some embodiments, according to the determined target execution cycle, the number n of buffer areas separated between the current buffer area polled by the execution thread in the current execution cycle and the target buffer area for caching the next instruction is determined, and the nth buffer area after the current buffer area polled by the execution thread in the current execution cycle is determined as the target buffer area corresponding to the next instruction. For example, if the target execution cycle corresponding to the next instruction of the delayed instruction is the third execution cycle after the current execution cycle, it is determined that the number n of cache areas spaced between the current cache area and the target cache area polled by the execution thread in the current execution cycle is 3, and the 3 rd cache area after the current cache area is determined as the target cache area for caching the next instruction of the delayed instruction.
Optionally, each buffer of the preset list is provided with a unique address identifier, such as an ID address. The method comprises the steps of acquiring a first address identifier of a current cache region polled by an execution thread in a current execution cycle, adding n to the first address identifier based on a target execution cycle corresponding to a next instruction of a delay instruction to acquire a second address identifier corresponding to the target cache region for caching the next instruction, determining the cache region corresponding to the second address identifier as the target cache region according to the second address identifier, and caching the next instruction of the delay instruction in the target cache region.
In the embodiment, at least one instruction corresponding to multiple scenes in the current execution cycle of the execution thread is obtained, the at least one instruction is executed, when the executed at least one instruction contains a delay instruction, a target execution cycle corresponding to a next instruction of the delay instruction is determined, and after the current execution cycle is finished, other corresponding instructions of the multiple scenes are executed in the next execution cycle, wherein when the execution cycle reaches the target execution cycle, the next instruction of the delay instruction is executed, all instructions of the multiple scenes are executed in this way, compared with a mode that one instruction is executed sequentially after another instruction, when the delay instruction is executed, only a waiting mode can be performed, and the instruction execution efficiency is greatly improved.
Referring to fig. 4, fig. 4 is a schematic block diagram of an instruction execution device under multiple scenarios according to an embodiment of the present disclosure. As shown in fig. 4, the instruction execution apparatus 400 in multiple scenarios may include a processor 410 and a memory 420. The processor 410 and the memory 420 are connected by a bus, such as an I2C (Inter-integrated Circuit) bus.
Specifically, the Processor 410 may be a Micro-controller Unit (MCU), a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or the like.
Specifically, the Memory 420 may be a Flash chip, a Read-Only Memory (ROM) magnetic disk, an optical disk, a usb disk, or a removable hard disk.
Wherein the processor is configured to run a computer program stored in the memory and to implement the following steps when executing the computer program:
acquiring at least one instruction corresponding to a plurality of scenes in the current execution cycle of an execution thread;
executing the at least one instruction in the current execution cycle, and if the at least one instruction comprises a delay instruction, determining a target execution cycle corresponding to a next instruction of the delay instruction;
after the current execution cycle is finished, taking the next execution cycle as the current execution cycle, and returning to the step of executing at least one instruction corresponding to a plurality of scenes in the current execution cycle of the acquired execution thread; wherein the next instruction of the delayed instructions is executed when the current execution cycle reaches the target execution cycle.
In some embodiments, after implementing the executing of the at least one instruction in the current execution cycle, and if the at least one instruction includes a delay instruction, determining a target execution cycle corresponding to a next instruction of the delay instruction, the processor further implements:
caching the next instruction to a corresponding target cache region in a preset list according to the target execution cycle;
the executing the next instruction of the deferred instruction when the current execution cycle reaches the target execution cycle comprises:
and when the current execution cycle reaches the target execution cycle, polling the target cache region and executing the next instruction.
In some embodiments, before the caching the next instruction to the corresponding target cache region in the preset list according to the target execution cycle, the processor further includes:
calculating a quotient m of the delay duration divided by the cycle duration according to the delay duration corresponding to the delay instruction and the cycle duration corresponding to each execution cycle of the execution thread;
and establishing the preset list comprising m cache regions.
In some embodiments, the cycle duration comprises 1 second.
In some embodiments, when the processor caches the next instruction to a corresponding target cache region in a preset list according to the target execution cycle, the following is specifically implemented:
according to the current cache region polled by the execution thread in the current execution period, determining the target cache region to be polled by the execution thread after the target execution period;
and caching the next instruction to the target cache region.
In some embodiments, the processor, when implementing that the target cache region to be polled by the execution thread after the target execution period is determined according to the current cache region polled by the execution thread in the current execution period, specifically implements:
determining the number n of buffer areas separated between the current buffer area and the target buffer area according to the target execution cycle;
and determining the nth cache region after the current cache region as the target cache region.
In some embodiments, each cache region of the preset list corresponds to a unique address identifier, and when the processor determines that an nth cache region after the current cache region is the target cache region, the following steps are specifically implemented:
according to a first address identifier corresponding to the current cache region, performing n addition calculation on the first address identifier to obtain a second address identifier;
and determining the cache region corresponding to the second address identifier as the target cache region.
An embodiment of the present application further provides an electronic device, which may be, for example, the electronic device shown in fig. 1, where the electronic device includes a body, a power supply disposed in the body, and an instruction execution device in multiple scenarios. It should be noted that the instruction execution device in multiple scenarios may be the instruction execution device in multiple scenarios illustrated in fig. 4.
For the specific operation of the electronic device in executing the triggered instructions of the multiple scenes, reference may be made to the foregoing embodiments, which are not described herein again.
An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, where the computer program includes program instructions, and the processor executes the program instructions to implement the steps of the instruction execution method in multiple scenarios provided in the foregoing embodiment.
The computer-readable storage medium may be an internal storage unit of the electronic device of the foregoing embodiment, for example, a hard disk or a memory of the electronic device. The computer readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk provided on the electronic device, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like.
Since the computer program stored in the computer-readable storage medium can execute the instruction execution method in any of the multiple scenarios provided in the embodiments of the present application, beneficial effects that can be achieved by the instruction execution method in any of the multiple scenarios provided in the embodiments of the present application can be achieved, for details, see the foregoing embodiments, and are not described herein again.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An instruction execution method under multiple scenes is characterized by comprising the following steps:
acquiring at least one instruction corresponding to a plurality of scenes in the current execution cycle of an execution thread;
executing the at least one instruction in the current execution cycle, and if the at least one instruction comprises a delay instruction, determining a target execution cycle corresponding to a next instruction of the delay instruction;
after the current execution cycle is finished, taking the next execution cycle as the current execution cycle, and returning to the step of executing at least one instruction corresponding to a plurality of scenes in the current execution cycle of the acquired execution thread; wherein the next instruction of the delayed instructions is executed when the current execution cycle reaches the target execution cycle.
2. The method according to claim 1, wherein the executing the at least one instruction in the current execution cycle, and if the at least one instruction includes a delay instruction, after determining a target execution cycle corresponding to a next instruction of the delay instruction, further comprises:
caching the next instruction to a corresponding target cache region in a preset list according to the target execution cycle;
the executing the next instruction of the deferred instruction when the current execution cycle reaches the target execution cycle comprises:
and when the current execution cycle reaches the target execution cycle, polling the target cache region and executing the next instruction.
3. The method of claim 2, wherein the caching the next instruction to a corresponding target cache region in a preset list according to the target execution cycle further comprises:
calculating a quotient m of the delay duration divided by the cycle duration according to the delay duration corresponding to the delay instruction and the cycle duration corresponding to each execution cycle of the execution thread;
and establishing the preset list comprising m cache regions.
4. The method of claim 3, wherein the cycle duration comprises 1 second.
5. The method according to any one of claims 2 to 4, wherein the caching the next instruction to a corresponding target cache region in a preset list according to the target execution cycle comprises:
according to the current cache region polled by the execution thread in the current execution period, determining the target cache region to be polled by the execution thread after the target execution period;
and caching the next instruction to the target cache region.
6. The method of claim 5, wherein the determining the target cache region to be polled by the execution thread after the target execution period according to the current cache region polled by the execution thread in the current execution period comprises:
determining the number n of buffer areas separated between the current buffer area and the target buffer area according to the target execution cycle;
and determining the nth cache region after the current cache region as the target cache region.
7. The method of claim 6, wherein each cache region of the preset list corresponds to a unique address identifier, and the determining an nth cache region after the current cache region as the target cache region comprises:
according to a first address identifier corresponding to the current cache region, performing n addition calculation on the first address identifier to obtain a second address identifier;
and determining the cache region corresponding to the second address identifier as the target cache region.
8. A multi-scenario instruction execution device, comprising a processor and a memory, wherein the memory stores a computer program, and the processor executes the multi-scenario instruction execution method according to any one of claims 1 to 7 when calling the computer program in the memory.
9. An electronic device comprising a body, a power supply provided in the body, and an instruction execution apparatus according to claim 8 under multiple scenarios.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, which, when executed by a processor, causes the processor to implement the instruction execution method in the multi-scenario of any one of claims 1 to 7.
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| CN107766120A (en) * | 2016-08-23 | 2018-03-06 | 华为技术有限公司 | The recording method of object information and relevant device in a kind of virtual machine |
| CN107992517A (en) * | 2017-10-26 | 2018-05-04 | 深圳市金立通信设备有限公司 | A kind of data processing method, server and computer-readable medium |
| CN109885857A (en) * | 2018-12-26 | 2019-06-14 | 苏州中晟宏芯信息科技有限公司 | Instruction issue control method, instruction execution verification method, system and storage medium |
| CN109936489A (en) * | 2019-03-25 | 2019-06-25 | 美的智慧家居科技有限公司 | The control method and system, gateway and storage medium of scene linkage |
| CN110515709A (en) * | 2019-07-25 | 2019-11-29 | 北京达佳互联信息技术有限公司 | Task scheduling system, method, apparatus, electronic equipment and storage medium |
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