CN113132250B - Data packet transmission method, device, electronic equipment and medium - Google Patents

Data packet transmission method, device, electronic equipment and medium Download PDF

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Publication number
CN113132250B
CN113132250B CN201911424655.0A CN201911424655A CN113132250B CN 113132250 B CN113132250 B CN 113132250B CN 201911424655 A CN201911424655 A CN 201911424655A CN 113132250 B CN113132250 B CN 113132250B
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node
hop
determining
interface
time delay
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CN113132250A (en
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王志伟
孙宝良
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Qianxin Technology Group Co Ltd
Secworld Information Technology Beijing Co Ltd
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Qianxin Technology Group Co Ltd
Secworld Information Technology Beijing Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/12—Avoiding congestion; Recovering from congestion
    • H04L47/125—Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/2483—Traffic characterised by specific attributes, e.g. priority or QoS involving identification of individual flows
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/625—Queue scheduling characterised by scheduling criteria for service slots or service orders
    • H04L47/626—Queue scheduling characterised by scheduling criteria for service slots or service orders channel conditions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/70—Admission control; Resource allocation
    • H04L47/82—Miscellaneous aspects
    • H04L47/825—Involving tunnels, e.g. MPLS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

The present disclosure provides a data packet transmission method. The method comprises the steps of obtaining a plurality of next hop nodes of an initial node; determining an interface type of each next-hop node in the plurality of next-hop nodes; determining time delay information of a communication link between an initial node and each next-hop node according to the interface type; determining a target node from a plurality of next-hop nodes according to the time delay information; and transmitting the target data packet from the initial node to the target node. The disclosure also provides a data packet transmission device, an electronic device and a medium.

Description

Data packet transmission method, device, electronic equipment and medium
Technical Field
The disclosure relates to a data packet transmission method, a data packet transmission device, electronic equipment and a data packet transmission medium.
Background
Enterprise or entity access to critical resources may use redundant links. When one link fails, the redundant link switches the service to the other link, so that the stability of the service can be ensured. But the redundant links are idle during normal access, resulting in wasted link bandwidth.
The related art performs load balancing on the active and standby links according to the link bandwidth, that is, distributes the traffic to the corresponding links according to the bandwidth proportion of the links. When the links fail, the links act as backup. This scheme, although improving the bandwidth utilization, cannot guarantee the quality of service.
Disclosure of Invention
One aspect of the present disclosure provides a data packet transmission method, including: acquiring a plurality of next hop nodes of an initial node; determining an interface type of each next-hop node of the plurality of next-hop nodes; determining time delay information of a communication link between the initial node and each next-hop node according to the interface type; determining a target node from the plurality of next-hop nodes according to the time delay information; and transmitting a target data packet from the initial node to the target node.
Optionally, the determining the interface type of each next-hop node in the plurality of next-hop nodes includes: for each next-hop node in the plurality of next-hop nodes, acquiring a gateway address of the next-hop node; and determining the interface type of the next hop node according to the gateway address.
Optionally, the interface type includes a tunnel interface and a normal route interface; the determining the interface type of the next hop node according to the gateway address comprises the following steps: determining whether the gateway address is a normal gateway address; and if the gateway address is a common gateway address, determining the interface type of the next hop node as a common routing interface, otherwise, determining the interface type of the next hop node as a tunnel interface.
Optionally, the determining, according to the interface type, delay information of a communication link between the initial node and each next hop node includes: under the condition that the interface type is a tunnel interface, acquiring two tunnel end nodes corresponding to the next hop node, and detecting time delay between the two tunnel end nodes as the time delay information; and under the condition that the interface type is a common routing interface, acquiring a destination address, and detecting the time delay from the initial node to a terminal node corresponding to the destination address as the time delay information.
Optionally, the determining a target node from the plurality of next-hop nodes according to the delay information includes: for each next-hop node of the plurality of next-hop nodes, a weight of the next-hop node is calculated according to the following formula: w (W) n ＝T lcm /T n Wherein the W is n The T is the weight of the next hop node n For the time delay corresponding to the next hop node, the T is as follows lcm The least common multiple of the time delay corresponding to the next hop nodes is obtained; and determining a target node from the plurality of next-hop nodes according to the weight.
Another aspect of the present disclosure provides a data packet transmission device, including a first acquisition module, configured to acquire a plurality of next-hop nodes of an initial node; a first determining module, configured to determine an interface type of each next-hop node in the plurality of next-hop nodes; the second determining module is used for determining time delay information of a communication link between the initial node and each next-hop node according to the interface type; a third determining module, configured to determine a target node from the plurality of next-hop nodes according to the delay information; and the sending module is used for sending the target data packet from the initial node to the target node.
Optionally, the first determining module includes: a second obtaining sub-module, configured to obtain, for each next-hop node in the plurality of next-hop nodes, a gateway address of the next-hop node; and a fourth determining submodule, configured to determine an interface type of the next hop node according to the gateway address.
Optionally, the interface type includes a tunnel interface and a normal route interface; the fourth determination sub-module includes: a fifth determining unit, configured to determine whether the gateway address is a normal gateway address; and a sixth determining unit, configured to determine that an interface type of a next hop node is a normal routing interface when the gateway address is a normal gateway address, and determine that an interface type of the next hop node is a tunnel interface when the gateway address is not a normal gateway address.
Optionally, the second determining module includes: the first detection module is used for acquiring two tunnel end nodes corresponding to the next hop node under the condition that the interface type is a tunnel interface, and detecting time delay between the two tunnel end nodes as the time delay information; and the second detection module is used for acquiring a destination address under the condition that the interface type is a common routing interface, and detecting the time delay from the initial node to the terminal node corresponding to the destination address as the time delay information.
Optionally, the third determining module includes: a calculation sub-module forFor each next-hop node of the plurality of next-hop nodes, a weight of the next-hop node is calculated according to the following formula: w (W) n ＝T lcm /T n Wherein the W is n The T is the weight of the next hop node n For the time delay corresponding to the next hop node, the T is as follows lcm The least common multiple of the time delay corresponding to the next hop nodes is obtained; and a seventh determining submodule, configured to determine a target node from the plurality of next-hop nodes according to the weight.
Another aspect of the present disclosure provides an electronic device, comprising: one or more processors; a memory for storing one or more computer programs, wherein the one or more computer programs, when executed by the one or more processors, cause the one or more processors to implement the method as described above.
Another aspect of the present disclosure provides a computer-readable storage medium storing computer-executable instructions that, when executed, are configured to implement a method as described above.
Another aspect of the present disclosure provides a computer program comprising computer executable instructions which when executed are for implementing a method as described above.
According to the embodiment of the disclosure, the interface types of a plurality of next-hop nodes of the initial node are determined, the time delay information of a communication link between the initial node and each next-hop node is determined according to the interface types, the target node is determined from the plurality of next-hop nodes according to the time delay information, and the target data packet is sent from the initial node to the target node, so that more traffic can run on links with lower time delay of the links, and the service quality is ensured. Meanwhile, the communication links between the initial node and the next hop nodes can mutually realize backup, so that the communication is ensured not to be interrupted.
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For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
fig. 1 schematically illustrates an exemplary system to which a packet transmission method and a packet transmission apparatus may be applied according to an embodiment of the present disclosure;
fig. 2 schematically illustrates a flow chart of a data packet transmission method according to an embodiment of the disclosure;
fig. 3 schematically illustrates a block diagram of a data packet transmission device according to an embodiment of the present disclosure;
FIG. 4 schematically illustrates a block diagram of a first determination module according to another embodiment of the disclosure;
FIG. 5 schematically illustrates a block diagram of a fourth determination sub-module according to another embodiment of the present disclosure;
FIG. 6 schematically illustrates a block diagram of a second determination module according to another embodiment of the disclosure;
FIG. 7 schematically illustrates a block diagram of a third determination module according to another embodiment of the disclosure; and
fig. 8 schematically illustrates a block diagram of a computer system suitable for implementing the above-described method according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.
Where expressions like at least one of "A, B and C, etc. are used, the expressions should generally be interpreted in accordance with the meaning as commonly understood by those skilled in the art (e.g.," a system having at least one of A, B and C "shall include, but not be limited to, a system having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.). Where a formulation similar to at least one of "A, B or C, etc." is used, in general such a formulation should be interpreted in accordance with the ordinary understanding of one skilled in the art (e.g. "a system with at least one of A, B or C" would include but not be limited to systems with a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).
Some of the block diagrams and/or flowchart illustrations are shown in the figures. It will be understood that some blocks of the block diagrams and/or flowchart illustrations, or combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the instructions, when executed by the processor, create means for implementing the functions/acts specified in the block diagrams and/or flowchart. The techniques of this disclosure may be implemented in hardware and/or software (including firmware, microcode, etc.). Additionally, the techniques of this disclosure may take the form of a computer program product on a computer-readable storage medium having instructions stored thereon, the computer program product being for use by or in connection with an instruction execution system.
The embodiment of the disclosure provides a data packet transmission method and a data packet transmission device capable of applying the method. The method comprises the following steps: acquiring a plurality of next-hop nodes of an initial node, and determining the interface type of each next-hop node in the plurality of next-hop nodes; determining time delay information of a communication link between an initial node and each next-hop node according to the interface type; determining a target node from a plurality of next-hop nodes according to the time delay information; and transmitting the target data packet from the initial node to the target node.
Fig. 1 schematically illustrates an exemplary system to which a packet transmission method and a packet transmission apparatus may be applied according to an embodiment of the present disclosure. It should be noted that fig. 1 is merely an example of a scenario in which embodiments of the present disclosure may be applied to assist those skilled in the art in understanding the technical content of the present disclosure, but does not mean that embodiments of the present disclosure may not be used in other devices, systems, environments, or scenarios.
As shown in fig. 1, the exemplary system includes a packet receiving module 101, a rule matching module 102, a routing module 103, a packet sending module 104, a configuration issuing module 105, and a link probing module 106.
The packet receiving module 101 may be, for example, a network card, and the packet receiving processing logic may be a kernel, or may directly process in a user mode by using a DPDK technology or other technologies. The DPDK is a data plane development suite (Data Plane Development Kit) developed by 6WIND, intel and other companies, is mainly based on LINUX system operation, and is used for fast data packet processing function library and drive set, so that data processing performance and throughput can be greatly improved, and working efficiency of a data plane application program can be improved.
The rule matching module 102 is configured to process the packet received in the packet receiving module 101, where the rule matching module 102 obtains information of each dimension in the data packet and compares the information with information set by a user. Specific information includes source address, destination address, user, area, etc. All information is satisfied means that the rule is matched.
And the routing module 103 is used for performing routing processing after the specific rules are matched. The main logic of the routing is to select the most suitable next hop from a plurality of next hops according to a routing algorithm.
The packet sending module 104 is configured to fill the next hop MAC with the data packet after the next hop is selected, and send the data packet to the network card. One logic is that the next hop is the tunnel module, and the physical network card needs to be sent out by encapsulation.
The configuration issuing module 105 is configured to store the configuration of the user and issue the configuration to a specific execution module.
The link probing module 106 is configured to obtain specific probing information from the configuration module. And after the detection of the detection object is completed, feeding back the result to the configuration module.
Fig. 2 schematically illustrates a flow chart of a data packet transmission method according to an embodiment of the present disclosure.
As shown in fig. 2, the method includes operations S210 to S230.
In operation S210, a plurality of next-hop nodes of an initial node are acquired.
According to embodiments of the present disclosure, all next-hop nodes for an initial node may be obtained by reading the routing table of that node.
In operation S220, an interface type of each of the plurality of next-hop nodes is determined.
According to embodiments of the present disclosure, interface types may include, for example, a tunnel type and a normal route type.
According to the embodiment of the disclosure, the gateway address of the next-hop node can be obtained, and the interface type of the next-hop node is determined according to the gateway address. More specifically, the interface type of the next hop node can be distinguished by judging whether the gateway address of the node is a normal gateway address, if the gateway address of the node is the normal gateway address, the interface type of the node is a normal routing interface, and if the gateway address of the node is not the normal gateway address, the interface type of the node is a tunnel interface.
In operation S230, delay information of a communication link between the initial node and each next-hop node is determined according to the interface type.
According to the embodiment of the disclosure, the method can be applied to the next-hop node of the tunnel type and the next-hop node of the common route type. And under the condition that the interface type is a tunnel interface, acquiring two tunnel end nodes corresponding to the next hop node, and detecting the time delay between the two tunnel end nodes as time delay information. Under the condition that the interface type is a common routing interface, a destination address is obtained, and the time delay from the initial node to the terminal node corresponding to the destination address is detected and used as time delay information.
According to embodiments of the present disclosure, the delay between nodes may be detected, for example, by ICMP Ping packets or TCP Ping packets, and the delay of a node may also be obtained by testing the DNS delay of the node.
In operation S240, a target node is determined from among a plurality of next-hop nodes according to the delay information.
According to an embodiment of the present disclosure, operation S240 may include, for example, for each next-hop node, first calculating a weight according to a delay feedback algorithm, and then selecting one from among a plurality of next-hop nodes as a target node according to the weight of each next-hop node.
According to the embodiment of the disclosure, the delay feedback algorithm can acquire the delay information of the detection message according to the link quality detection and report the delay information to the configuration issuing module, the configuration issuing module stores the delay information of the detection message received in the link detection database, calculates a plurality of next-hop weight values of the load strategy according to the reported delay information, and performs delay load balancing according to the load weight value proportion of each next-hop.
According to embodiments of the present disclosure, the weight of the next hop node may be calculated, for example, according to the following formula:
W n ＝T lcm /T n ，
wherein W is n Is the weight of the nth next hop node, T n T is the time delay corresponding to the next hop node lcm The least common multiple of the time delay corresponding to the next hop nodes.
For example, the next-hop nodes of the initial node include node 1, node 2 and node 3, the delay of node 1 is 2s, the delay of node 2 is 4s, and the delay of node 3 is 8s. First, the least common multiple T of the three time delays is calculated lcm ＝[2，4，8]=8, and then calculates the weight W of the node 1 according to the weight calculation formula 1 Weight W of node 2 =8/2=4 2 Weight W of node 3 =8/4=2 3 ＝8/8＝1。
According to embodiments of the present disclosure, the smaller the delay, the greater the weight, and the greater the probability of being selected as the target node. Under the condition that the weight of each next-hop node is known, the value range corresponding to each next-hop node can be divided according to the proportion of the weight of the next-hop node to the total weight, then the hash value of the source address of the target data packet to be transmitted is obtained, the total weight of a plurality of next-hop nodes and the hash value of the source address are subjected to the remainder operation (the hash value of the source address is%=the total weight of a plurality of next-hop delay weight values of a load strategy), and the obtained remainder falls into the weight range of the next-hop node to select which next-hop node is used as the target node.
In operation S250, a target data packet is transmitted from the initial node to the target node.
According to the embodiment of the disclosure, when a data packet request arrives at an initial node, session information is firstly queried, and for an established session, a packet is sent according to a last packet sending interface. For the newly created session to enter the routing module, firstly, inquiring whether the selection conditions of the routing are matched or not, and the user can route the traffic through dimensions of source ip, destination ip, application and the like. And selecting the route for the traffic matched with the route selection rule according to the weight of the next hop node at the time, so that most traffic is ensured to run on the link with low time delay.
According to the embodiment of the disclosure, the interface types of a plurality of next-hop nodes of the initial node are determined, the time delay information of a communication link between the initial node and each next-hop node is determined according to the interface types, the target node is determined from the plurality of next-hop nodes according to the time delay information, and the target data packet is sent from the initial node to the target node, so that more traffic can run on links with lower time delay of the links, and the service quality is ensured. Meanwhile, the communication links between the initial node and the next hop nodes can mutually realize backup, so that the communication is ensured not to be interrupted.
According to other embodiments of the present disclosure, the above method may be set to a load balancing policy, and matching conditions may be set for the load balancing policy, where the matching conditions include, for example, a specific source address, destination address, ISP name, source security domain, source user, application, and the like. When a data packet is received, determining whether the data packet matches the matching condition, if the matching condition matches, indicating that the data packet can apply the load balancing strategy, and transmitting the data packet according to the data packet transmission method. If not, the packet is routed according to other routing logic, such as static routing. Therefore, after the data packet is received, the load balancing strategy matched with the data packet can be automatically selected according to the data packet, and the system is more intelligent.
Operation S230 is further described below in conjunction with example 1.
According to the embodiment of the disclosure, when the next hop is a common gateway address, a common link detection object may be added according to the next hop gateway address, where the detection object specifies a detection destination address, and the destination address may be a destination IP of a peer device or an IP address of a certain device node on a specified link, and the on-off and time delay information of the destination address is detected through a detection packet, so that each next hop configuration of the load policy refers to a link detection object, and the link detection object returns time delay information for the next hop link quality of the load policy.
According to other embodiments of the present disclosure, specific parameters of the link probe object may be set, mainly including a probe interval, a timeout time, a retry number, a probe address, and the like. To ensure that the probe object exits the designated probe path, interface plus next hop gateway information may be designated.
According to the embodiment of the disclosure, when the next hop is a tunnel interface, the interface to be designated is the tunnel interface, and meanwhile, a link detection object in the tunnel is added, wherein the detection object can be an IP address of the opposite end of the tunnel, so that the next hop is the tunnel interface and references the link detection object. Therefore, only the detection interval, the overtime time and the retry times are required to be set for the detection in the tunnel, and the detection address and the detection route are not required to be set.
According to the embodiment of the disclosure, all the probe information is sent to the link probe module, the link probe module starts corresponding probe, the probe module creates a socket according to the probe destination address of the probe configuration and sends an ICMP request message to the probe destination address, the message format is consistent with the Linux Ping request message format, a timeout timer is started while sending, and ICMP sending time is recorded. The socket is an abstract layer through which an application program can send or receive data, and can perform operations such as opening, reading and writing, closing, and the like, like a file. Sockets allow applications to insert I/O into the network and communicate with other applications in the network. A web socket is a combination of an IP address and a port. Illustratively, the timeout of the timer may be 1 second by default. When the transmitted ICMP request message has a response within the timeout time, subtracting the receiving time of the ICMP response message according to the transmitting time of the ICMP request message is the link delay time of the link detection message to the detection destination address. If the ICMP request message times out, the link is considered to be not through.
According to another embodiment of the present disclosure, the next hop cannot be used when the link is disconnected, and after the link delay changes, the corresponding weight of the next hop also needs to be changed, and these changes are sent back to the routing module by the configuration module.
The method of link delay probing and redistributing load balancing next hops is further described in conjunction with embodiment 2.
According to an embodiment of the present disclosure, link probing is initiated according to a setting. The detection module can detect a plurality of objects at the same time, each detection object creates a socket according to detection configuration, and starts an ICMP request timer, and the ICMP request message sends a detection message through a socket interface, and starts an ICMP detection response timer, and waits for overtime or ICMP detection message return.
According to the embodiment of the disclosure, after a data packet is received or a timer is overtime, when an ICMP detection response message is received before the ICMP response timer is overtime, detection delay information is calculated according to the ICMP detection message sending time minus the detection message response receiving time, so that the ICMP detection message can be used as a sampling sample after the ICMP detection message is returned, each sample has delay information, and a detection module sends the delay information of the samples to a configuration issuing module according to the reporting timer time interval timing.
According to embodiments of the present disclosure, a packet timeout is considered a packet loss, but cannot be equated to a link disconnection. The number of retries may be preset, and if the number of consecutive packet losses exceeds the number of retries, the link is considered to be disconnected, and the configuration module is notified. The on-off information of the link and the time delay information of the link are notified to the configuration module. If the data packet is received, the link delay information is obtained through the sampling result, and the average delay is calculated together with the history information.
After the configuration module receives the notification, the configuration module resends the next hop to the routing module.
According to the embodiment of the disclosure, the interface types of a plurality of next-hop nodes of the initial node are determined, the time delay information of a communication link between the initial node and each next-hop node is determined according to the interface types, the target node is determined from the plurality of next-hop nodes according to the time delay information, and the target data packet is sent from the initial node to the target node, so that more traffic can run on links with lower time delay of the links, and the service quality is ensured. Meanwhile, the communication links between the initial node and the next hop nodes can mutually realize backup, so that the communication is ensured not to be interrupted.
Fig. 3 schematically illustrates a block diagram of a data packet transmission device according to an embodiment of the present disclosure.
As shown in fig. 3, the packet transmission apparatus 300 includes a first acquisition module 310, a first determination module 320, a second determination module 330, a third determination module 340, and a transmission module 350. The packet transfer device 300 may perform the method described above with reference to fig. 2.
Specifically, the first obtaining module 310 is configured to obtain a plurality of next hop nodes of the initial node.
A first determining module 320 is configured to determine an interface type of each next-hop node in the plurality of next-hop nodes.
A second determining module 330 is configured to determine delay information of a communication link between the initial node and each next-hop node according to the interface type.
A third determining module 340, configured to determine the target node from the plurality of next-hop nodes according to the delay information.
A sending module 350, configured to send the target data packet from the initial node to the target node.
According to the embodiment of the disclosure, the interface types of a plurality of next-hop nodes of the initial node are determined, the time delay information of a communication link between the initial node and each next-hop node is determined according to the interface types, the target node is determined from the plurality of next-hop nodes according to the time delay information, and the target data packet is sent from the initial node to the target node, so that more traffic can run on links with lower time delay of the links, and the service quality is ensured. Meanwhile, the communication links between the initial node and the next hop nodes can mutually realize backup, so that the communication is ensured not to be interrupted.
Fig. 4 schematically illustrates a block diagram of a first determination module according to another embodiment of the disclosure.
As shown in fig. 4, the first determining module 320 includes:
a second obtaining sub-module 421, configured to obtain, for each next-hop node of the plurality of next-hop nodes, a gateway address of the next-hop node.
A fourth determining submodule 422 is configured to determine an interface type of the next hop node according to the gateway address.
Fig. 5 schematically illustrates a block diagram of a fourth determination sub-module according to another embodiment of the present disclosure.
As shown in fig. 5, the fourth determination sub-module 422 includes: a fifth determining unit 5221 is configured to determine whether the gateway address is a normal gateway address.
A sixth determining unit 5222, configured to determine that the interface type of the next-hop node is a normal routing interface if the gateway address is a normal gateway address, and determine that the interface type of the next-hop node is a tunnel interface if the gateway address is not a normal gateway address.
Fig. 6 schematically illustrates a block diagram of a second determination module according to another embodiment of the disclosure.
As shown in fig. 6, the second determining module 330 includes:
the first detecting module 631 is configured to obtain two tunnel end nodes corresponding to a next hop node, and detect a time delay between the two tunnel end nodes as time delay information when the interface type is a tunnel interface.
The second detection module 632 is configured to obtain the destination address, and detect a delay from the initial node to the terminal node corresponding to the destination address as delay information when the interface type is a normal routing interface.
Fig. 7 schematically illustrates a block diagram of a third determination module according to another embodiment of the disclosure.
As shown in fig. 7, the third determining module 340 includes: a calculating sub-module 741 for calculating, for each next-hop node of the plurality of next-hop nodes, a weight of the next-hop node according to the following formula: w (W) n ＝T lcm /T n Wherein W is n T is the weight of the next hop node n T is the time delay corresponding to the next hop node lcm The least common multiple of the time delay corresponding to the next hop nodes.
A seventh determining sub-module 742 is configured to determine the target node from the plurality of next-hop nodes according to the weights.
Any number of modules, sub-modules, units, sub-units, or at least some of the functionality of any number of the sub-units according to embodiments of the present disclosure may be implemented in one module. Any one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure may be implemented as split into multiple modules. Any one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure may be implemented at least in part as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system-on-chip, a system-on-substrate, a system-on-package, an Application Specific Integrated Circuit (ASIC), or in any other reasonable manner of hardware or firmware that integrates or encapsulates the circuit, or in any one of or a suitable combination of three of software, hardware, and firmware. Alternatively, one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure may be at least partially implemented as computer program modules, which when executed, may perform the corresponding functions.
For example, any of the first acquisition module 310, the first determination module 320, the second determination module 330, the third determination module 340, and the transmission module 350 may be combined in one module to be implemented, or any one of the modules may be split into a plurality of modules. Alternatively, at least some of the functionality of one or more of the modules may be combined with at least some of the functionality of other modules and implemented in one module. According to embodiments of the present disclosure, at least one of the first acquisition module 310, the first determination module 320, the second determination module 330, the third determination module 340, and the transmission module 350 may be implemented at least in part as hardware circuitry, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or as hardware or firmware in any other reasonable manner of integrating or packaging the circuitry, or as any one of or a suitable combination of any of the three. Alternatively, at least one of the first acquisition module 310, the first determination module 320, the second determination module 330, the third determination module 340, and the transmission module 350 may be at least partially implemented as a computer program module, which when executed, may perform the corresponding functions.
Fig. 8 schematically illustrates a block diagram of a computer system suitable for implementing the above-described method according to an embodiment of the present disclosure. The computer system illustrated in fig. 8 is merely an example, and should not be construed as limiting the functionality and scope of use of the embodiments of the present disclosure.
As shown in FIG. 8, computer system 800 includes a processor 810 and a computer-readable storage medium 820. The computer system 800 may perform methods according to embodiments of the present disclosure.
In particular, processor 810 may include, for example, a general purpose microprocessor, an instruction set processor and/or an associated chipset and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), or the like. Processor 810 may also include on-board memory for caching purposes. The processor 810 may be a single processing unit or multiple processing units for performing the different actions of the method flows according to embodiments of the disclosure.
Computer-readable storage medium 820, which may be, for example, a non-volatile computer-readable storage medium, specific examples include, but are not limited to: magnetic storage devices such as magnetic tape or hard disk (HDD); optical storage devices such as compact discs (CD-ROMs); a memory, such as a Random Access Memory (RAM) or a flash memory; etc.
The computer-readable storage medium 820 may comprise a computer program 821, which computer program 821 may comprise code/computer-executable instructions, which when executed by the processor 810, cause the processor 810 to perform a method according to an embodiment of the present disclosure or any variation thereof.
The computer program 821 may be configured with computer program code comprising, for example, computer program modules. For example, in an example embodiment, code in the computer program 821 may include one or more program modules, including 821A, 821B, … …, for example. It should be noted that the division and number of modules is not fixed, and that a person skilled in the art may use suitable program modules or combinations of program modules according to the actual situation, which when executed by the processor 810, enable the processor 810 to perform the method according to the embodiments of the present disclosure or any variations thereof.
According to an embodiment of the present invention, at least one of the first acquisition module 310, the first determination module 320, the second determination module 330, the third determination module 340 and the transmission module 350 may be implemented as computer program modules described with reference to fig. 8, which when executed by the processor 810, may implement the respective operations described above.
The present disclosure also provides a computer-readable storage medium that may be embodied in the apparatus/device/system described in the above embodiments; or may exist alone without being assembled into the apparatus/device/system. The computer-readable storage medium carries one or more programs which, when executed, implement methods in accordance with embodiments of the present disclosure.
According to embodiments of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example, but is not limited to: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be combined in various combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.
While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. The scope of the disclosure should, therefore, not be limited to the above-described embodiments, but should be determined not only by the following claims, but also by the equivalents of the following claims.

Claims (5)

1. A data packet transmission method, comprising:
acquiring a plurality of next hop nodes of an initial node;
determining an interface type of each next-hop node of the plurality of next-hop nodes;
determining time delay information of a communication link between the initial node and each next-hop node according to the interface type;
determining a target node from the plurality of next-hop nodes according to the time delay information; and
transmitting a target data packet from the initial node to the target node;
the determining an interface type of each next-hop node of the plurality of next-hop nodes includes:
for each next-hop node in the plurality of next-hop nodes, acquiring a gateway address of the next-hop node; and
determining the interface type of the next hop node according to the gateway address;
the interface type comprises a tunnel interface and a common routing interface; the determining the interface type of the next hop node according to the gateway address comprises the following steps:
determining whether the gateway address is a normal gateway address; and
if the gateway address is a common gateway address, determining the interface type of the next hop node as a common routing interface, otherwise, determining the interface type of the next hop node as a tunnel interface;
and determining delay information of a communication link between the initial node and each next-hop node according to the interface type, wherein the delay information comprises the following steps:
under the condition that the interface type is a tunnel interface, acquiring two tunnel end nodes corresponding to the next hop node, and detecting time delay between the two tunnel end nodes as the time delay information; and
and under the condition that the interface type is a common routing interface, acquiring a destination address, and detecting the time delay from the initial node to a terminal node corresponding to the destination address as the time delay information.
2. The method of claim 1, wherein the determining a target node from the plurality of next-hop nodes based on the latency information comprises:
for each next-hop node of the plurality of next-hop nodes, a weight of the next-hop node is calculated according to the following formula:
W n ＝T lcm /T n ，
wherein the W is n The T is the weight of the next hop node n For the time delay corresponding to the next hop node, the T is as follows lcm The least common multiple of the time delay corresponding to the next hop nodes is obtained; and
and determining a target node from the plurality of next-hop nodes according to the weight.
3. A data packet transmission apparatus comprising:
the first acquisition module is used for acquiring a plurality of next hop nodes of the initial node;
a first determining module, configured to determine an interface type of each next-hop node in the plurality of next-hop nodes;
the second determining module is used for determining time delay information of a communication link between the initial node and each next-hop node according to the interface type;
a third determining module, configured to determine a target node from the plurality of next-hop nodes according to the delay information; and
the sending module is used for sending a target data packet from the initial node to the target node;
the first determining module includes:
a second obtaining sub-module, configured to obtain, for each next-hop node in the plurality of next-hop nodes, a gateway address of the next-hop node; and
a fourth determining submodule, configured to determine an interface type of the next hop node according to the gateway address;
the fourth determination sub-module includes: a fifth determining unit, configured to determine whether the gateway address is a normal gateway address;
a sixth determining unit, configured to determine that, when the gateway address is a normal gateway address, an interface type of the next-hop node is a normal routing interface, and determine that, when the gateway address is not a normal gateway address, the interface type of the next-hop node is a tunnel interface;
the second determining module includes:
the first detection module is used for acquiring two tunnel end nodes corresponding to the next hop node under the condition that the interface type is a tunnel interface, and detecting time delay between the two tunnel end nodes as time delay information;
and the second detection module is used for acquiring the destination address under the condition that the interface type is a common routing interface, and detecting the time delay from the initial node to the terminal node corresponding to the destination address as time delay information.
4. An electronic device, comprising:
one or more processors;
a memory for storing one or more computer programs,
wherein the one or more computer programs, when executed by the one or more processors, cause the one or more processors to implement the method of claim 1 or 2.
5. A computer readable storage medium having stored thereon executable instructions which, when executed by a processor, cause the processor to implement the method of claim 1 or 2.
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