CN113132240B

CN113132240B - Data packet processing and forwarding method, device, integrated chip, switch and system

Info

Publication number: CN113132240B
Application number: CN202110432614.7A
Authority: CN
Inventors: 张腾; 宁锋
Original assignee: Beijing ByteDance Network Technology Co Ltd
Current assignee: Beijing ByteDance Network Technology Co Ltd
Priority date: 2021-04-21
Filing date: 2021-04-21
Publication date: 2023-02-10
Anticipated expiration: 2041-04-21
Also published as: CN113132240A

Abstract

The disclosure discloses a data packet processing and forwarding method, a data packet processing and forwarding device, an integrated chip, a switch and a system. The data packet processing method comprises the following steps: receiving a traffic data packet forwarded by a switch, and extracting quintuple information from the traffic data packet; searching a connection table according to the quintuple information; and if the information of the target server corresponding to the quintuple information is found in the connection table, updating a packet header of the flow data packet according to the information of the target server, and sending the updated flow data packet to the switch, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a virtual expanded local area network message and forwarding the virtual expanded local area network message to the target server. According to the technical scheme, the flow processing and forwarding functions in the load balancing network are distributed to hardware, the operation of updating the packet header and the operation of encapsulating the message are respectively executed by the integrated chip and the switch, and the flow data packet does not need to be uploaded to a software layer for processing, so that the forwarding efficiency of the flow data packet is improved.

Description

Data packet processing and forwarding method, device, integrated chip, switch and system

Technical Field

The embodiment of the disclosure relates to the technical field of network traffic processing, and in particular, to a method and a device for processing and forwarding a data packet, an integrated chip, a switch and a system.

Background

The four-layer load balancing gateway is deployed at an entrance of a data center and is mainly used for forwarding a traffic data packet of a client to a server in the data center by modifying address information of the data packet after receiving the traffic of the client. In the existing traffic forwarding process, traffic of a client can be forwarded only after being processed by software of a switch, a gateway and a Central Processing Unit (CPU), and the forwarding process is low in throughput, large in delay and low in forwarding efficiency.

Disclosure of Invention

The present disclosure provides a method and an apparatus for processing and forwarding a data packet, an integrated chip, a switch, and a system, which can implement forwarding of a traffic data packet without software processing by a central processing unit, thereby improving forwarding efficiency of the traffic data packet.

In a first aspect, an embodiment of the present disclosure provides a data packet processing method, applied to an integrated chip, including:

receiving a flow data packet forwarded by a switch, and extracting quintuple information from the flow data packet;

searching a connection table according to the quintuple information;

if the information of the destination server corresponding to the quintuple information is found in the connection table, updating a packet header of the flow data packet according to the information of the destination server, and sending the updated flow data packet to the switch, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a Virtual extended local area network (VxLAN) message and forwarding the VxLAN message to the destination server.

In a second aspect, an embodiment of the present disclosure further provides a data packet forwarding method, including:

forwarding a flow data packet of a client to an integrated chip;

receiving a flow data packet returned by the integrated chip after updating the packet header according to the information of the target server;

and encapsulating the updated flow data packet into a VxLAN message according to the updated packet header, and forwarding the VxLAN message to the destination server.

In a third aspect, an embodiment of the present disclosure further provides a data packet processing apparatus, including:

the extraction module is used for receiving the traffic data packet forwarded by the switch and extracting quintuple information from the traffic data packet;

the table look-up module is used for looking up a connection table according to the quintuple information;

and the data packet updating module is used for updating a packet header of the flow data packet according to the information of the target server and sending the updated flow data packet to the switch if the information of the target server corresponding to the quintuple information is found in the connection table, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a VxLAN message and forwarding the VxLAN message to the target server.

In a fourth aspect, an embodiment of the present disclosure further provides a data packet forwarding apparatus, including:

the data packet forwarding module is used for forwarding the flow data packet of the client to the integrated chip;

the data packet receiving module is used for receiving a flow data packet returned by the integrated chip after updating the packet header according to the information of the destination server;

and the message forwarding module is used for encapsulating the updated flow data packet into a VxLAN message according to the updated packet header and forwarding the VxLAN message to the target server.

In a fifth aspect, an embodiment of the present disclosure further provides an integrated chip, including:

one or more processors;

storage means for storing one or more programs;

when executed by the one or more processors, cause the one or more processors to implement the packet processing method according to the first aspect.

In a sixth aspect, an embodiment of the present disclosure further provides a switch, including:

one or more processors;

storage means for storing one or more programs;

when executed by the one or more processors, cause the one or more processors to implement the traffic packet forwarding method of the first aspect.

In a seventh aspect, an embodiment of the present disclosure further provides a data packet forwarding system, including:

a client, a switch as in the sixth aspect, an integrated chip as in the fifth aspect, and at least one server; the switch is respectively connected with the client, the integrated chip and each server;

the switch is used for forwarding the flow data packet of the client to the integrated chip;

the integrated chip is used for extracting quintuple information from the flow data packet; searching a connection table according to the quintuple information;

if the information of the target server corresponding to the quintuple information is found in the connection table, updating the packet header of the traffic data packet according to the information of the target server, and sending the updated traffic data packet to the switch;

and the switch is also used for encapsulating the updated flow data packet into a VxLAN message according to the updated packet header and forwarding the VxLAN message to the destination server.

The embodiment of the disclosure provides a method, a device, an integrated chip, a switch and a system for processing and forwarding a data packet. The data packet processing method comprises the following steps: receiving a traffic data packet forwarded by a switch, and extracting quintuple information from the traffic data packet; searching a connection table according to the quintuple information; and if the information of the target server corresponding to the quintuple information is found in the connection table, updating a packet header of the flow data packet according to the information of the target server, and sending the updated flow data packet to the switch, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a virtual extended local area network message and forwarding the virtual extended local area network message to the target server. According to the technical scheme, the flow processing and forwarding functions in the load balancing network are distributed to hardware, the operation of updating the packet header and the operation of encapsulating the message are respectively executed by the integrated chip and the switch, and the flow data packet does not need to be uploaded to a software layer for processing, so that the forwarding efficiency of the flow data packet is improved.

Drawings

Fig. 1 is a schematic flowchart of a data packet processing method according to an embodiment of the present disclosure;

fig. 2 is a schematic flow chart of a data packet processing method according to a second embodiment of the present disclosure;

fig. 3 is a schematic diagram of a packet forwarding path according to a second embodiment of the present disclosure;

fig. 4 is a schematic diagram of a packet processing procedure according to a second embodiment of the disclosure;

fig. 5 is a schematic diagram of a packet processing and forwarding process according to a second embodiment of the present disclosure;

fig. 6 is a schematic flow chart of a data packet forwarding method according to a third embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a packet processing apparatus according to a fourth embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a packet forwarding device according to a fifth embodiment of the present disclosure;

fig. 9 is a schematic diagram of a hardware structure of an integrated chip according to a sixth embodiment of the present disclosure;

fig. 10 is a schematic hardware structure diagram of a switch according to a seventh embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a packet forwarding system according to an eighth embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and the embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.

The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment".

It is noted that references to "a" or "an" in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will appreciate that references to "one or more" are intended to be exemplary and not limiting unless the context clearly indicates otherwise.

The names of messages or information exchanged between devices in the embodiments of the present disclosure are for illustrative purposes only, and are not intended to limit the scope of the messages or information.

In the following embodiments, optional features and examples are provided in each embodiment, and various features described in the embodiments may be combined to form multiple alternatives, and each numbered embodiment should not be regarded as only one technical solution. Furthermore, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict.

Example one

Fig. 1 is a schematic flowchart of a data packet processing method according to an embodiment of the present disclosure. The method can be applied to the condition that the load balancing network forwards the traffic data packet of the client, and particularly is used for forwarding the traffic of the client to a server in a data center by modifying the address information of the data packet. The method may be performed by a packet processing device, wherein the device may be implemented by software and/or hardware and integrated on an integrated chip. The integrated chip in this embodiment mainly refers to a Field Programmable Gate Array (FPGA).

As shown in fig. 1, a data packet processing method provided in the first embodiment of the present disclosure may be applied to an integrated chip. The method specifically comprises the following steps:

s110, receiving the traffic data packet forwarded by the switch, and extracting quintuple information from the traffic data packet.

In this embodiment, the traffic of the client is forwarded to the FPGA by the switch, and the FPGA extracts quintuple information from the traffic data packet. The quintuple information includes a source Internet Protocol (IP) address, a source port, a destination IP address, a destination port, and a transport Protocol. According to the quintuple information, a destination server can be selected for each flow data packet, so that load balancing is realized.

And S120, searching a connection table according to the quintuple information.

In this embodiment, the connection table is stored in the FPGA, and the connection table stores a corresponding relationship between the five-tuple information and the server, for example, a flow packet specifying each five-tuple information (i.e., a combination of a source IP address, a source port, a destination IP address, a destination port, and a transport protocol) is forwarded to a destination server of a specific address. On the basis, when the flow data packet reaches the FPGA, the destination server of the flow data packet can be determined by extracting quintuple information and searching the connection table. In one embodiment, the connection table may be created by a software layer (CPU) of the load balancing network and issued to the FPGA.

And S130, if the information of the destination server corresponding to the quintuple information is found in the connection table, updating the packet header of the flow data packet according to the information of the destination server, and sending the updated flow data packet to the switch, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a VxLAN (virtual extensible local area network) message and forwarding the VxLAN message to the destination server.

In this embodiment, when the traffic data packet reaches the FPGA, if the destination server corresponding to the quintuple information of the traffic data packet is stored in the connection table, the FPGA instructs the switch to forward the traffic data packet according to the table lookup result, and the traffic data packet does not need to be uploaded to the software layer for processing. The specific indication mode may be: and the FPGA inserts information about the searched target server into a packet header of the flow data packet, and then sends the updated flow data packet to the switch so as to instruct the switch to carry out message encapsulation and forward the encapsulated message to the target server. On the basis, the data packet processing and forwarding function of the load balancing network is split between the FPGA and the switch to be executed, the FPGA supports large bandwidth, the whole processing amount and the forwarding flow support large bandwidth, and delay of flow forwarding can be reduced.

In the data packet processing method provided in this embodiment, a switch and an FPGA architecture are used to implement a traffic processing and forwarding function of a load balancing network, and the main idea is to divide the traffic processing and forwarding function into two parts: and (5) connecting the table and encapsulating the message. The connection table is responsible for searching a destination server of the traffic data packet, and the packet encapsulation is to encapsulate the traffic data packet into a VxLAN message. The connection table is maintained by the FPGA, the package is completed by the programmable switch, and the flow data packet does not need to be uploaded to a software layer for processing, so that the forwarding efficiency of the flow data packet is improved, and the delay is reduced.

Example two

Fig. 2 is a schematic flowchart of a data packet processing method according to a second embodiment of the present disclosure. In the second embodiment, the processing procedure of the traffic data packet is embodied on the basis of the first embodiment. The integrated chip in this embodiment mainly refers to an FPGA.

In this embodiment, if the information of the destination server corresponding to the quintuple information is not found in the connection table, the traffic data packet is sent to the CPU; receiving information of a destination server corresponding to the quintuple information and transmitted by the CPU; and updating the connection table according to the information of the destination server. The CPU software layer is used for processing the bottom, the flow data packet can be forwarded for the first processed quintuple information, and the connection table is updated for the FPGA to subsequently process the flow data packet of the same quintuple information, so that effective hardware acceleration and comprehensive load balance are realized.

As shown in fig. 2, a second data packet processing method provided in the embodiment of the present disclosure includes the following steps:

s210, receiving the traffic data packet forwarded by the switch, and extracting quintuple information from the traffic data packet.

And S220, searching the connection table according to the quintuple information.

S230, finding the information of the destination server corresponding to the quintuple information in the connection table? If yes, go to step S270; otherwise, S240 is performed.

And S240, sending the flow data packet to a central processing unit.

And S250, receiving the information of the destination server corresponding to the quintuple information, which is sent by the central processing unit.

And S260, updating the connection table according to the information of the destination server.

In this embodiment, if a destination server corresponding to the quintuple information of a traffic data packet is not found in the connection table when the traffic data packet reaches the FPGA, the FPGA may upload the traffic data packet to the CPU, the CPU determines the destination server of the traffic data packet, and issues the quintuple information of the traffic data packet and the corresponding destination server to the FPGA to update the connection table stored in the FPGA. When the next flow data packet with the same quintuple information reaches the FPGA, the FPGA can determine the target server by searching the latest connection table.

And S270, updating the packet head of the flow data packet according to the information of the destination server.

In this embodiment, if the connection table stores the destination server corresponding to the quintuple information of the traffic data packet, the FPGA updates the packet header of the traffic data packet according to the table lookup result to instruct the switch to perform packet encapsulation and complete forwarding. If the connection table does not have the destination server corresponding to the quintuple information of the flow data packet, after the FPGA receives the information of the destination server corresponding to the quintuple information sent by the CPU, the FPGA updates the packet head of the flow data packet according to the information of the destination server so as to indicate the switch to perform message encapsulation and complete forwarding.

And S280, sending the updated flow data packet to the exchanger.

It should be noted that, a packet processed from the client to the switch and then to the FPGA is called an inbound packet, and the inbound packet may be forwarded to the destination server through the switch under the condition that the destination server can be found in the connection table. The message fed back to the client after the destination server receives the message is called a return message, and the return message can be directly forwarded to the client by the switch without passing through an FPGA.

The switch in this embodiment mainly refers to a programmable switch, that is, a Packet processor (P4) switch that is not related to a Programming Protocol.

Fig. 3 is a schematic diagram of a packet forwarding path according to a second embodiment of the present disclosure. The forwarding paths for the three packets are shown in fig. 3 with three arrows. The path (1) is consistent with the existing flow forwarding flow, and the flow data packet of the client is processed by a P4 switch, an FPGA and a CPU software layer and then is forwarded by the FPGA and the P4 switch; the path (2) represents that the flow data packet of the client is processed by the P4 switch and the FPGA and then can be forwarded by the P4 switch, so that the flow of software layer processing is avoided; path (3) indicates that the packet can be forwarded through the P4 switch, for example, the above backward packet. Both the paths (2) and (3) have the effect of hardware acceleration, which can improve forwarding efficiency and reduce delay.

In one embodiment, the number of Ethernet (ETH) interfaces for receiving the traffic data packets is at least one, and each ETH interface corresponds to a set of object Mapping framework (HBM) files; the connection table is stored in each HBM file in the form of a hash table.

In this embodiment, there may be a plurality of ETH interfaces for receiving the traffic data packet. Each ETH interface corresponds to a group of HBM files, and quintuple information sent by a CPU and a destination server corresponding to each quintuple information are stored in the HBM files in a hash table mode.

Fig. 4 is a schematic diagram of a packet processing procedure according to a second embodiment of the disclosure. As shown in FIG. 4, the two EGH interfaces are respectively denoted as 100G-ETH-0 and 100G-ETH-1, and correspond to HBM-0 and HBM-1. The FPGA receives the flow data packets through the ETH interface and stores the flow data packets in the message buffer area, and then analyzes the flow data packets to extract quintuple information for table lookup and count the number of the flow data packets at the same time.

In one embodiment, the lookup of the connection table according to the five-tuple information comprises: calculating a hash value according to the quintuple information; and accessing the information of the server stored in the corresponding address in the connection table according to the hash value.

In this embodiment, the connection table is stored in the HBM file in the form of a hash table, and each time a flow data packet comes, the FPGA calculates a hash value according to the quintuple information of the flow data packet, points to a certain address in the connection table, and accesses the HBM according to the hash value to read the content on the address, where the content includes information of the destination server.

In one embodiment, the information of the destination server corresponding to the five tuple information includes: a first field for indicating a destination server address, and a second field for indicating a destination port. On this basis, the FPGA can instruct the P4 switch to forward the encapsulated packet to the destination port of the destination server.

In one embodiment, updating the header of the traffic data packet according to the information of the destination server includes: the first field and the second field are inserted into a Metadata (Metadata) header, which is located between an ethernet header and an IP header of the traffic data packet.

Fig. 5 is a schematic diagram of a packet processing and forwarding process according to a second embodiment of the present disclosure. As shown in fig. 5, a first field (rs _ index) in the connection table (Session _ table) is used to indicate the destination server address to the P4 switch, and a second field (rs _ port) is used to indicate the destination port to the P4 switch. And the FPGA acquires the rs _ index and the rs _ port through table lookup and inserts the rs _ index and the rs _ port into a Metadata packet header positioned between the Ethernet packet header and the IP packet header. After the flow data packet with the updated packet header is sent to the P4 switch, the P4 switch takes out the Metadata packet header, obtains information required for packet encapsulation and information of the destination server according to the rs _ index (for example, address conversion is performed by translating the rs _ index to obtain a physical machine address (rs _ IP), a virtual machine address (rs _ vtep _ IP) and/or a Media Access Control (MAC) address (rs _ MAC) of the destination server), and obtains information of the destination port according to the rs _ port.

EXAMPLE III

Fig. 6 is a schematic flow chart of a data packet forwarding method provided in the third embodiment of the present disclosure. The method can be applied to the condition that the load balancing network forwards the flow data packet of the client, in particular to the condition that the packet is packaged and forwarded according to the indication of the packet header updated by the FPGA. The method may be performed by a traffic packet forwarding device, wherein the device may be implemented by software and/or hardware and integrated on a switch. The integrated chip in this embodiment mainly refers to an FPGA. It should be noted that technical details that are not described in detail in the present embodiment may be referred to any of the above embodiments.

As shown in fig. 6, a packet forwarding method provided in the first embodiment of the present disclosure may be applied to a switch. The method specifically comprises the following steps:

and S310, forwarding the flow data packet of the client to the integrated chip.

And S320, receiving a flow data packet returned by the integrated chip after updating the packet header according to the information of the destination server.

And S330, encapsulating the updated flow data packet into a VxLAN message according to the updated packet header, and forwarding the VxLAN message to a destination server.

In one embodiment, the updated packet header includes an ethernet packet header, a metadata packet header, and an IP packet header; the metadata packet header includes a first field for indicating an address of a destination server and a second field for indicating a destination port.

In an embodiment, encapsulating the updated traffic data packet into a VxLAN packet according to the updated packet header, and forwarding the VxLAN packet to a destination server, includes: performing network address conversion on the first field to obtain the address of the destination server, and performing VxLAN message encapsulation according to the first field; determining a destination port according to the second field; and forwarding the VxLAN message to a destination port of a destination server. Wherein the first field is, for example, rx _ index, the second field is, for example, rs _ port, and the address of the destination server includes a physical machine address, an IP address, and/or a MAC address.

In the data packet forwarding method provided in this embodiment, a switch and an FPGA architecture are used to implement a traffic processing and forwarding function of a load balancing network, and the main idea is to divide the traffic processing and forwarding function into two parts: and (5) packaging the connection table and the message. The connection table is responsible for searching a destination server of the traffic data packet, and the packet encapsulation is to encapsulate the traffic data packet into a VxLAN message. The connection table is maintained by the FPGA, the package encapsulation is completed by the programmable switch, and the flow data packet does not need to be sent to a software layer for processing, so that the forwarding efficiency of the flow data packet is improved, and the delay is reduced.

Example four

Fig. 7 is a schematic structural diagram of a packet processing apparatus according to a fourth embodiment of the present disclosure. For a detailed description of the present embodiment, please refer to the above embodiments.

As shown in fig. 7, the apparatus includes:

an extracting module 410, configured to receive a traffic packet forwarded by a switch, and extract quintuple information from the traffic packet;

a table look-up module 420 for looking up a connection table according to the quintuple information;

and a data packet updating module 430, configured to update a packet header of the traffic data packet according to the information of the destination server if the information of the destination server corresponding to the quintuple information is found in the connection table, and send the updated traffic data packet to the switch, where the updated packet header is used to instruct the switch to encapsulate the updated traffic data packet into a virtual extensible local area network VxLAN packet and forward the packet to the destination server.

The packet processing apparatus of this embodiment uses the switch and FPGA architecture to implement the traffic processing and forwarding functions of the load balancing network, and the main idea is to divide the traffic processing and forwarding functions into two parts: and (5) connecting the table and encapsulating the message. The connection table is responsible for searching a destination server of the traffic data packet, and the packet encapsulation is to encapsulate the traffic data packet into a VxLAN message. The connection table is maintained by the FPGA, the package encapsulation is completed by the programmable switch, and the flow data packet does not need to be sent to a software layer for processing, so that the forwarding efficiency of the flow data packet is improved, and the delay is reduced.

On the basis, the device further comprises:

the uploading module is used for sending the flow data packet to a central processing unit if the information of the destination server corresponding to the quintuple information is not found in the connection table;

the information receiving module is used for receiving the information of the destination server which is sent by the central processing unit and corresponds to the quintuple information;

and the connection table updating module is used for updating the connection table according to the information of the destination server.

On the basis, at least one Ethernet interface for receiving the flow data packet is provided, and each Ethernet interface is corresponding to a group of object relationship mapping frameworks to configure an HBM file; the connection table is stored in each HBM file in the form of a hash table.

Based on the above, the table lookup module 420 includes:

the calculating unit is used for calculating a hash value according to the quintuple information;

and the access unit is used for accessing the information of the server stored in the corresponding address in the connection table according to the hash value.

On the basis, the information of the destination server corresponding to the five tuple information includes: a first field for indicating a destination server address, and a second field for indicating a destination port.

On the basis, the packet update module 430 is specifically configured to: inserting the first field and the second field into a metadata packet header, where the metadata packet header is located between an ethernet packet header and an Internet Protocol (IP) packet header of the traffic data packet.

The data packet processing device can execute the data packet processing method provided by any embodiment of the disclosure, and has corresponding functional modules and beneficial effects of the execution method.

EXAMPLE five

Fig. 8 is a schematic structural diagram of a packet forwarding device according to a fifth embodiment of the present disclosure. For a detailed description of the present embodiment, please refer to the above embodiments.

As shown in fig. 8, the apparatus includes:

a packet forwarding module 510, configured to forward a traffic packet of a client to an integrated chip;

a data packet receiving module 520, configured to receive a flow data packet returned by the ic after updating the packet header according to the information of the destination server;

and the message forwarding module 530 is configured to encapsulate the updated traffic data packet into a VxLAN message according to the updated packet header, and forward the VxLAN message to the destination server.

The traffic packet forwarding device of this embodiment uses a switch and an integrated chip architecture to implement traffic processing and forwarding functions of a load balancing network, and the main idea is to divide the traffic processing and forwarding functions into two parts: and (5) connecting the table and encapsulating the message. The connection table is responsible for searching a destination server of the traffic data packet, and the packet encapsulation is to encapsulate the traffic data packet into a VxLAN message. The connection table is maintained by the integrated chip, the package is completed by the programmable switch, and the flow data packet does not need to be sent to a software layer for processing, so that the forwarding efficiency of the flow data packet is improved, and the delay is reduced.

On the basis, the updated packet header comprises an Ethernet packet header, a metadata packet header and an IP packet header;

the metadata packet header includes a first field indicating an address of a destination server and a second field indicating a destination port.

On the above basis, the message forwarding module 510 includes:

the address conversion unit is used for carrying out network address conversion on the first field to obtain the address of the destination server and carrying out VxLAN message encapsulation according to the first field;

a port determining unit, configured to determine a destination port according to the second field;

and the forwarding unit is used for forwarding the VxLAN message to a destination port of the destination server.

The traffic data packet forwarding device can execute the traffic data packet forwarding method provided by any embodiment of the disclosure, and has corresponding functional modules and beneficial effects of the execution method.

Example six

Fig. 9 is a schematic diagram of a hardware structure of an integrated chip according to a sixth embodiment of the present disclosure. The integrated chip 600 in the embodiment of the present disclosure mainly refers to an FPGA. The integrated chip 600 shown in fig. 9 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 9, the integrated chip 600 may include one or more processing devices (e.g., central processing unit, graphics processor, etc.) 601 that may perform various appropriate actions and processes in accordance with programs stored in a Read Only Memory (ROM) 602 or loaded from a storage device 608 into a Random Access Memory (RAM) 603. One or more processing devices 601 implement a packet processing method as provided by the present disclosure. In the RAM603, various programs and data necessary for the operation of the integrated chip 600 are also stored. The processing device 601, the ROM602, and the RAM603 are connected to each other via a bus 605. An input/output (I/O) interface 604 is also connected to bus 605.

Generally, the following devices may be connected to the I/O interface 604: input devices 606 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 607 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 608, including, for example, magnetic tape, hard disk, etc., storage 608 for storing one or more programs; and a communication device 609. The communication means 609 may allow the integrated chip 600 to communicate with other integrated chips wirelessly or by wire to exchange data. While fig. 9 shows an integrated chip 600 having various means, it is to be understood that not all of the means shown are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.

In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 609, or may be installed from the storage means 608, or may be installed from the ROM 602. The computer program, when executed by the processing device 601, performs the above-described functions defined in the methods of embodiments of the present disclosure.

EXAMPLE seven

Fig. 10 is a schematic hardware structure diagram of a switch according to a seventh embodiment of the present disclosure. Fig. 10 shows a schematic block diagram of a switch 700 suitable for implementing embodiments of the present disclosure. The switch 700 in the disclosed embodiment includes, but is not limited to, an access gateway, a load balancer, and the like. The switch 700 shown in fig. 10 is only an example and should not bring any limitation to the function and the scope of use of the embodiments of the present disclosure.

As shown in fig. 10, the switch 700 may include one or more processing devices (e.g., central processing units, graphics processors, etc.) 701 that may perform various appropriate actions and processes according to programs stored in a Read Only Memory (ROM) 702 or loaded from a storage device 708 into a Random Access Memory (RAM) 703. One or more processing devices 701 implement a traffic packet forwarding method as provided by the present disclosure. In the RAM703, various programs and data necessary for the operation of the switch 700 are also stored. The processing device 701, the ROM702, and the RAM703 are connected to each other through a bus 705. An input/output (I/O) interface 704 is also connected to bus 705.

Generally, the following devices may be connected to the I/O interface 704: input devices 706 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 707 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 708, including, for example, magnetic tape, hard disk, etc., storage 708 for storing one or more programs; and a communication device 709. The communication means 709 may allow the switch 700 to communicate wirelessly or by wire with other devices to exchange data. While fig. 10 illustrates a switch 700 having various devices, it is to be understood that not all of the illustrated devices are required to be implemented or provided. More or fewer devices may be alternatively implemented or provided.

In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such embodiments, the computer program may be downloaded and installed from a network via the communication means 709, or may be installed from the storage means 708, or may be installed from the ROM 702. The computer program, when executed by the processing device 701, performs the above-described functions defined in the methods of the embodiments of the present disclosure.

Example eight

Fig. 11 is a schematic structural diagram of a packet forwarding system according to an eighth embodiment of the present disclosure. The system is applicable to the condition that a load balancing network forwards the traffic data packet of the client, and particularly is used for forwarding the traffic of the client to a server in a data center by modifying the address information of the data packet. It should be noted that technical details that are not described in detail in the present embodiment may be referred to any of the above embodiments.

As shown in fig. 11, the system includes: a client 810, a switch 820, an integrated chip 830, and at least one server 840; the switch 820 is respectively connected with the client 810, the integrated chip 830 and each server 840; the switch 820 is used for forwarding the traffic data packet of the client 810 to the integrated chip 830; the integrated chip 830 is configured to extract quintuple information from the traffic data packet; searching a connection table according to the quintuple information; if the information of the destination server corresponding to the quintuple information is found in the connection table, updating the packet header of the traffic data packet according to the information of the destination server, and sending the updated traffic data packet to the switch 820;

the switch 820 is further configured to encapsulate the updated traffic data packet into a VxLAN packet according to the updated packet header, and forward the VxLAN packet to the destination server.

In the traffic data packet forwarding system of this embodiment, the P4 switch replaces the conventional switch, and the FPGA replaces the gateway in the conventional load balancing network, so that the traffic processing and forwarding functions in the load balancing network are allocated to the hardware, the operations of updating the packet header and encapsulating the packet are respectively performed by the FPGA and the switch, and the traffic data packet does not need to be uploaded to a software layer for processing, thereby improving the forwarding efficiency of the traffic data packet and reducing the delay.

On the basis of the above, the system further comprises: a central processing unit;

the ic 830 is further configured to send the traffic data packet to the central processing unit if the information of the destination server corresponding to the quintuple information is not found in the connection table; the central processing unit is used for generating and issuing information of a destination server corresponding to the quintuple information; the FPGA is also used for updating the connection table according to the information of the destination server corresponding to the quintuple information.

On the basis, updating the packet header of the flow data packet according to the information of the destination server comprises the following steps: inserting a first field for indicating a destination server address and a second field for indicating a destination port into a metadata packet header, the metadata packet header being located between an ethernet packet header and an IP packet header of a traffic packet.

On the basis, the method comprises the following steps of encapsulating the updated flow data packet into a VxLAN message according to the updated packet header and forwarding the VxLAN message to a target server, wherein the method comprises the following steps:

performing network address conversion on the first field to obtain the address of the destination server, and performing VxLAN message encapsulation according to the first field; determining a destination port according to the second field; and forwarding the VxLAN message to a destination port of a destination server.

The traffic data packet forwarding system can realize the data packet processing method and the forwarding method provided by any embodiment of the disclosure, and has the corresponding functional modules and beneficial effects of the execution method.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. Each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The modules described in the embodiments of the present disclosure may be implemented by software or hardware. Wherein the name of a module in some cases does not constitute a limitation on the module itself.

The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), complex Programmable Logic Devices (CPLDs), and the like.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Example 1 provides a packet processing method applied to an integrated chip, including:

searching a connection table according to the quintuple information;

and if the information of the target server corresponding to the quintuple information is found in the connection table, updating a packet header of the flow data packet according to the information of the target server, and sending the updated flow data packet to the switch, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a VxLAN message and forwarding the VxLAN message to the target server.

Example 2 the method of example 1, according to one or more embodiments of the present disclosure, further comprising:

if the information of the destination server corresponding to the quintuple information is not found in the connection table, sending the flow data packet to a central processing unit;

receiving information of a destination server corresponding to the quintuple information and issued by the central processing unit;

and updating the connection table according to the information of the destination server.

Example 3 the method of example 1, the ethernet interfaces for receiving traffic packets are at least one, each ethernet interface corresponding to a set of object relational mapping framework configuration HBM files; the connection table is stored in each of the HBM files in the form of a hash table.

Example 4 the method of example 3, the looking up a connection table according to the five-tuple information, according to one or more embodiments of the present disclosure, comprising: calculating a hash value according to the quintuple information; and accessing the information of the server stored in the corresponding address in the connection table according to the hash value.

Example 5 the method of example 1, the information of the destination server corresponding to the five-tuple information comprising: a first field for indicating a destination server address, and a second field for indicating a destination port.

Example 6 the method of example 5, the updating the header of the traffic packet according to the information of the destination server, comprising:

inserting the first field and the second field into a metadata packet header, where the metadata packet header is located between an ethernet packet header and an IP packet header of the traffic data packet.

Example 7 provides a packet forwarding method, applied to a switch, according to one or more embodiments of the present disclosure, including:

forwarding a flow data packet of a client to an integrated chip;

Example 8 the method of example 7, the updated packet header comprising an ethernet packet header, a metadata packet header, and an IP packet header;

the metadata packet header includes a first field for indicating a destination server address and a second field for indicating a destination port.

Example 9 the method of example 8, wherein encapsulating the updated traffic packet into a VxLAN packet according to the updated packet header and forwarding the VxLAN packet to the destination server according to the updated packet header, comprises: performing network address conversion on the first field to obtain the address of the destination server, and performing VxLAN message encapsulation according to the first field; determining a destination port according to the second field; and forwarding the VxLAN message to a destination port of the destination server.

Example 10 provides, in accordance with one or more embodiments of the present disclosure, a data packet processing apparatus comprising:

and the data packet updating module is used for updating the packet header of the flow data packet according to the information of the target server and sending the updated flow data packet to the switch if the information of the target server corresponding to the quintuple information is found in the connection table, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a VxLAN message and forwarding the VxLAN message to the target server.

Example 11 provides, in accordance with one or more embodiments of the present disclosure, a packet forwarding apparatus comprising:

Example 12 provides, in accordance with one or more embodiments of the present disclosure, an integrated chip comprising:

one or more processors;

storage means for storing one or more programs;

when executed by the one or more processors, cause the one or more processors to implement the packet processing method as in any of examples 1-6.

Example 13 provides, in accordance with one or more embodiments of the present disclosure, a switch, comprising:

one or more processors;

storage means for storing one or more programs;

when executed by the one or more processors, cause the one or more processors to implement a traffic packet forwarding method as in any of examples 7-9.

Example 14 provides, in accordance with one or more embodiments of the present disclosure, a packet forwarding system, comprising a client, a switch, an integrated chip, and at least one server; the switch is respectively connected with the client, the integrated chip and each server;

the integrated chip is used for extracting quintuple information from the flow data packet; searching a connection table according to the quintuple information; if the information of the target server corresponding to the quintuple information is found in the connection table, updating the packet header of the traffic data packet according to the information of the target server, and sending the updated traffic data packet to the switch;

Example 15 the system of example 14, according to one or more embodiments of the present disclosure, further comprising: a central processing unit; the integrated chip is further configured to send the traffic data packet to the central processing unit if the information of the destination server corresponding to the quintuple information is not found in the connection table;

the central processing unit is used for generating and issuing information of a destination server corresponding to the quintuple information;

the integrated chip is also used for updating the connection table according to the information of the destination server corresponding to the five-tuple information.

Example 16 the system of example 14, the updating the header of the traffic data packet according to the information of the destination server, according to one or more embodiments of the present disclosure, includes:

inserting a first field for indicating a destination server address and a second field for indicating a destination port into a metadata packet header, the metadata packet header being located between an ethernet packet header and an IP packet header of the traffic data packet.

Example 17 the system of example 16, the encapsulating the updated traffic data packet into a VxLAN packet according to the updated packet header, and forwarding the VxLAN packet to the destination server, according to one or more embodiments of the present disclosure, includes:

performing network address conversion on the first field to obtain the address of the destination server, and performing VxLAN message encapsulation according to the first field;

determining a destination port according to the second field;

and forwarding the VxLAN message to a destination port of the destination server.

The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure herein is not limited to the particular combination of features described above, but also encompasses other combinations of features described above or equivalents thereof without departing from the spirit of the disclosure. For example, the above features and the technical features disclosed in the present disclosure (but not limited to) having similar functions are replaced with each other to form the technical solution.

Claims

1. A method of packet processing, the method being performed by a packet processing device, the device being integrated in an integrated chip, comprising:

receiving a traffic data packet forwarded by a switch, and extracting quintuple information from the traffic data packet;

searching a connection table according to the quintuple information;

if the information of the target server corresponding to the quintuple information is found in the connection table, updating a packet header of the flow data packet according to the information of the target server, and sending the updated flow data packet to the switch, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a VxLAN (virtual extensible local area network) message and forwarding the VxLAN message to the target server;

the connection table stores the corresponding relation between the quintuple information and the server, and is created by a software layer of a load balancing network and issued to the integrated chip.

2. The method of claim 1, further comprising:

3. The method according to claim 1, wherein the at least one ethernet interface for receiving the traffic data packets is at least one, and each ethernet interface configures the HBM file corresponding to a set of object relational mapping frameworks; the connection table is stored in each HBM file in the form of a hash table.

4. The method of claim 3, wherein said searching a connection table according to the five-tuple information comprises:

calculating a hash value according to the quintuple information;

and accessing the information of the server stored in the corresponding address in the connection table according to the hash value.

5. The method according to claim 1, wherein the information of the destination server corresponding to the quintuple information comprises: a first field for indicating a destination server address, and a second field for indicating a destination port.

6. The method of claim 5, wherein the updating the header of the traffic packet according to the information of the destination server comprises:

inserting the first field and the second field into a metadata packet header, where the metadata packet header is located between an ethernet packet header and an Internet Protocol (IP) packet header of the traffic data packet.

7. A data packet forwarding method is applied to a switch, and is characterized by comprising the following steps:

forwarding a flow data packet of a client to an integrated chip;

encapsulating the updated flow data packet into a VxLAN message according to the updated packet header, and forwarding the VxLAN message to the target server;

extracting quintuple information from the flow data packet by the integrated chip; searching a connection table according to the quintuple information; if the information of the target server corresponding to the quintuple information is found in the connection table, updating a packet header of the flow data packet according to the information of the target server, and sending the updated flow data packet to the switch, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a VxLAN (virtual extensible local area network) message and forwarding the VxLAN message to the target server; the connection table stores the corresponding relation between the quintuple information and the server, and is created by a software layer of a load balancing network and issued to the integrated chip.

8. The method of claim 7, wherein the updated header comprises an ethernet header, a metadata header, and an IP header;

9. The method according to claim 8, wherein encapsulating the updated traffic data packet into a VxLAN packet according to the updated packet header and forwarding the VxLAN packet to the destination server comprises:

determining a destination port according to the second field;

10. A packet processing apparatus, comprising:

the extracting module is used for receiving the flow data packet forwarded by the exchanger and extracting quintuple information from the flow data packet;

a packet updating module, configured to update a packet header of the traffic packet according to information of the destination server if information of the destination server corresponding to the quintuple information is found in the connection table, and send the updated traffic packet to the switch, where the updated packet header is used to instruct the switch to encapsulate the updated traffic packet into a VxLAN packet and forward the VxLAN packet to the destination server;

the connection table stores the corresponding relation between the quintuple information and the server, and is created by the software layer of the load balancing network and issued to the integrated chip.

11. A packet forwarding apparatus, comprising:

the message forwarding module is used for encapsulating the updated flow data packet into a VxLAN message according to the updated packet header and forwarding the VxLAN message to the target server;

the integrated chip extracts quintuple information from the flow data packet; searching a connection table according to the quintuple information; if the information of the target server corresponding to the quintuple information is found in the connection table, updating a packet header of the flow data packet according to the information of the target server, and sending the updated flow data packet to a switch, wherein the updated packet header is used for indicating the switch to encapsulate the updated flow data packet into a VxLAN message and forwarding the VxLAN message to the target server; the connection table stores the corresponding relationship between the quintuple information and the server, and the corresponding relationship is created by a software layer of a load balancing network and is issued to the integrated chip.

12. An integrated chip, comprising:

one or more processors;

storage means for storing one or more programs;

when executed by the one or more processors, cause the one or more processors to implement a data packet processing method as claimed in any one of claims 1-6.

13. A switch, comprising:

one or more processors;

storage means for storing one or more programs;

when executed by the one or more processors, cause the one or more processors to implement a method of forwarding data packets as claimed in any of claims 7-9.

14. A packet forwarding system comprising a client, a switch according to claim 13, an integrated chip according to claim 12, and at least one server; the switch is respectively connected with the client, the integrated chip and each server;

the integrated chip is used for extracting quintuple information from the flow data packet; searching a connection table according to the quintuple information; if the information of the destination server corresponding to the quintuple information is found in the connection table, updating a packet header of the traffic data packet according to the information of the destination server, and sending the updated traffic data packet to the switch;

15. The system of claim 14, further comprising: a central processing unit;

the integrated chip is further configured to send the traffic data packet to the central processing unit if the information of the destination server corresponding to the quintuple information is not found in the connection table;

16. The system according to claim 14, wherein said updating the header of the traffic packet according to the information of the destination server comprises:

17. The system according to claim 16, wherein said encapsulating the updated traffic packet into a VxLAN packet according to the updated packet header and forwarding the VxLAN packet to the destination server comprises:

determining a destination port according to the second field;