CN113131726B - Common mode voltage rejection PWM strategy with minimal switching losses - Google Patents

Abstract

The invention discloses a common mode voltage suppression PWM strategy with minimum switching loss, which includes using a PWM modulator on a three-phase voltage source inverter to generate drive signals Sa, Sb and Sc of a three-phase two-level inverter. The common mode voltage suppression PWM strategy of the present invention realizes the minimum switching loss within the full power factor range, improves the system efficiency, and can effectively suppress the common mode voltage.

Description

Common Mode Voltage Rejection PWM Strategy with Minimal Switching Losses

technical field

The invention belongs to the technical field of power electronic control, and in particular relates to a common mode voltage suppression PWM strategy with minimum switching loss.

Background technique

With the wide application of new wide-bandgap semiconductors (such as SiC, GAN, etc.) in frequency converters, some negative effects also follow. Especially the high frequency common mode voltage will generate bearing current on the rotating shaft of the motor, which will accelerate the aging of the motor and reduce its service life. Wide-bandgap semiconductor devices also lead to more severe common-mode currents due to their faster switching action. The common mode current will flow into the ground through the electrostatic coupling between the stator winding and the casing, and return to the grid through the ground conductor. This will not only cause the protection device to malfunction, but also generate large common-mode electromagnetic interference, affecting the safety of electricity use.

SUMMARY OF THE INVENTION

其中v_a ^*,v_b ^*和v_c ^*是三相电压源逆变器中控制器输出的参考电压，v₀是零序电压分量；v₀的表达式为：

i∈{a,b,c}。In order to solve the above-mentioned technical problems, the technical solution adopted in the present invention is: a common-mode voltage suppression PWM strategy with minimum switching loss, including using a PWM modulator on a three-phase voltage source inverter to generate a three-phase two-level inverter. The expressions of the drive signals Sa, Sb and Sc, and the modulated waves _va ^** , _vb ^** and _vc ^** of the drive signals Sa, Sb and Sc are:

Where v _a ^* , v _b ^* and v _c ^* are the reference voltages output by the controller in the three-phase voltage source inverter, v ₀ is the zero-sequence voltage component; the expression of v ₀ is:

i∈{a,b,c}.

As the optimization of above-mentioned technical scheme, the generation step of described v ₀ is:

(1) Obtain the reference voltages v _a ^* , v _b ^* and v _c ^* and the current sampling values i _a , ib , and ic ; (2) Calculate _{∣v m} ∣ ^* =min( _{∣v a} ^* ∣,∣v _b ^* ∣,∣v _c ^* ∣) and ∣i _n ∣ ^* =min(∣i _a ∣,∣i _b ∣,∣i _c ∣),m,n∈{a,b,c};

(2) Judge whether m is equal to n, when m and n are equal, get u _i ^* = u _n ^* , when m and n are not equal, judge whether ∣i _p ∣ is greater than ∣i _q ∣, where p, q∈a , b, c and p, q≠n, when ∣i _p ∣>∣i _q ∣, get u _i ^* =u _p ^* , when ∣i _p ∣ is not greater than ∣i _q ∣, get u _i ^* = u _q ^* ;

(3) According to the u _i ^* obtained in step (2), use the formula: u ₀ =sign(u _i ^* )·U _dc /2-u _i ^* to synthesize the v ₀ zero-sequence voltage component.

As a preferred option of the above technical solution, after the zero-sequence voltage components of v ₀ are synthesized, the PWM modulator is selectively set.

As a preferred option of the above technical solution, the PWM modulator includes a first ePWM generation mechanism and a second ePWM generation mechanism, the phase corresponding to v _n is generated by the first ePWM generation mechanism, n∈{a, b, c }, the remaining phases are generated using the second ePWM generation mechanism.

The beneficial effects of the present invention are: the common mode voltage suppression PWM strategy of the present invention realizes the minimum switching loss within the full power factor range, improves the system efficiency, and can effectively suppress the common mode voltage.

Description of drawings

Figure 1 is a schematic diagram of the algorithm synthesis of the common mode voltage suppression PWM strategy;

Fig. 2 is a flow chart of zero-sequence voltage component synthesis;

Fig. 3 is the schematic diagram of ePWM module setting in the controller;

Figure 4 is a schematic diagram of the comparison of the effective value of the common mode voltage;

Figure 5 is a schematic diagram of the comparison of the loss characteristics (SLF) of different PWM methods;

Figure 6 is a topology and control block diagram of a three-phase voltage source inverter.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

In the description of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

其中v_a ^*,v_b ^*和v_c ^*是三相电压源逆变器中控制器输出的参考电压，v₀是零序电压分量；v₀的表达式为：

i∈{a,b,c}。所述v₀的生成步骤是：Common-mode voltage rejection PWM strategy with minimal switching losses, including the use of a PWM modulator on a three-phase voltage source inverter to generate the drive signals Sa, Sb and Sc of the three-phase two-level inverter, the drive signals Sa, Sb and The expressions of modulating waves v _a ^** , v _b ^** , and v _c ^** of Sc are:

Where v _a ^* , v _b ^* and v _c ^* are the reference voltages output by the controller in the three-phase voltage source inverter, v ₀ is the zero-sequence voltage component; the expression of v ₀ is:

i∈{a,b,c}. The steps for generating _v0 are:

(1) Obtain the reference voltages v _a ^* , v _b ^* and v _c ^* and the current sampling values i _a , ib , and ic ; (2) Calculate _{∣v m} ∣ ^* =min( _{∣v a} ^* ∣,∣v _b ^* ∣,∣v _c ^* ∣) and ∣i _n ∣ ^* =min(∣i _a ∣,∣i _b ∣,∣i _c ∣),m,n∈{a,b,c};

(2) Judge whether m is equal to n, when m and n are equal, get u _i ^* = u _n ^* , when m and n are not equal, judge whether ∣i _p ∣ is greater than ∣i _q ∣, where p, q∈a , b, c and p, q≠n, when ∣i _p ∣>∣i _q ∣, get u _i ^* =u _p ^* , when ∣i _p ∣ is not greater than ∣i _q ∣, get u _i ^* = u _q ^* ;

(3) According to the u _i ^* obtained in step (2), use the formula: u ₀ =sign(u _i ^* )·U _dc /2-u _i ^* to synthesize the v ₀ zero-sequence voltage component.

Further, after the zero-sequence voltage components of v ₀ are synthesized, the PWM modulator is selectively set. The PWM modulator includes a first ePWM generation mechanism and a second ePWM generation mechanism, the phase corresponding to v _n is generated by the first ePWM generation mechanism, n∈{a, b, c}, and the remaining phases are generated by the second ePWM generation mechanism. ePWM generation mechanism generated. For example, V _n =V _a , then the a phase is generated by the first ePWM generation mechanism, and the b and c phases are generated by the second ePWM generation mechanism.

其中v_a ^*,v_b ^*和v_c ^*是控制器输出的参考电压，v₀是生成的零序电压分量。零序电压分量v₀的表达式为：

i∈{a,b,c}。零序电压分量v₀通过图2所示流程图获得。在完成零序电压分量合成后，还需要对所提算法的载波进行操作，其中v_n所对应的相，在所使用的控制芯片中，使用图3(b)所示的第一ePWM生成机制，其他相采用如图3(a)所示的第二ePWM生成机制。Specifically, it is implemented according to the process shown in FIG. 6 . The present invention implements the minimum common mode voltage algorithm through the carrier PWM method, and generates the drive signals Sa, Sb and Sc of the three-phase two-level inverter, as shown in FIG. 1 . The expressions of its modulating waves v _a ^** , v _b ^** and v _c ^** are:

where v _a ^* , v _b ^* and v _c ^* are the reference voltages output by the controller, and v ₀ is the resulting zero-sequence voltage component. The expression of the zero-sequence voltage component v ₀ is:

i∈{a,b,c}. The zero-sequence voltage component v ₀ is obtained through the flow chart shown in FIG. 2 . After the zero-sequence voltage component synthesis is completed, it is also necessary to operate the carrier of the proposed algorithm, where the phase corresponding to v _n uses the first ePWM generation mechanism shown in Figure 3(b) in the used control chip. , and the other phases adopt the second ePWM generation mechanism as shown in Figure 3(a).

其中，

表示为功率因数角。可以发现该策略比其他任何调制方法所获得的SLF结果都要小，如图5所示。By calculating the effective value of the common mode voltage, it can be found that the common mode voltage value of the PWM method proposed in the present invention is much smaller than that of the commonly used space vector modulation method, as shown in FIG. 4 . According to the calculation method by the switching loss characteristic formula (switching losses function, SLF) proposed in the document [Simple Analytical and Graphical Methods for Carrier-Based PWM-VSI Drives], it can be found that the SLF of the PWM method proposed by the present invention satisfies the following formula:

in,

Expressed as power factor angle. It can be found that this strategy achieves smaller SLF results than any other modulation method, as shown in Figure 5.

It is worth mentioning that the technical features of the three-phase voltage source inverter and PWM modulator involved in the patent application of the present invention should be regarded as the prior art, and the specific structure, working principle and possible control methods of these technical features . The space arrangement mode can be selected by conventional choices in the field, and should not be regarded as the invention point of the patent of the present invention, and the patent of the present invention will not be further detailed.

The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make many modifications and changes according to the concept of the present invention without creative work. The technical solutions that the inventive concept can obtain through logical analysis, reasoning or limited experiments on the basis of the prior art shall all fall within the protection scope determined by the claims.

Claims (4)

1. The common-mode voltage suppression PWM strategy with the minimum switching loss is characterized by comprising the steps of using a PWM modulator on a three-phase voltage source inverter to generate driving signals Sa, Sb and Sc of a three-phase two-level frequency converter and a modulation wave v of the driving signals Sa, Sb and Sc _a ^** 、v _b ^** 、v _c ^** The expression of (a) is:

wherein v is _a ^* ,v _b ^* And v _c ^* Is a reference voltage, v, output by a controller in a three-phase voltage source inverter ₀ Is the zero sequence voltage component; v. of ₀ The expression of (a) is:

v is ₀ The generation steps are as follows:

(1) obtaining a reference voltage v _a ^* ,v _b ^* And v _c ^* And current sample value i _a 、i _b 、i _c ；

(2) Calculation | v _m ∣ ^* ＝min(∣v _a ^* ∣,∣v _b ^* ∣,∣v _c ^* | i) and | i _n ∣ ^* ＝min(∣i _a ∣,∣i _b ∣,∣i _c ∣),m,n∈{a、b、c}；

(3) Judging whether m is equal to n or not, and obtaining v when m is equal to n _i ^* ＝v _n ^* And when m is not equal to n, judging | i _p If | i is greater than | i _q | wherein p, q ∈ a, b, c and p, q ≠ n, when | i _p ∣>∣i _q | get v _i ^* ＝v _p ^* When | i _p | is not greater than | i _q | get v _i ^* ＝v _q ^* ；

(4) According to v obtained in step (3) _i ^* Using the formula:

synthesis to obtain v ₀ A zero sequence voltage component.

2. The common-mode voltage rejection PWM strategy with minimal switching loss as in claim 1, wherein said v ₀ After the zero sequence voltage components are synthesized, PWM is adjustedThe controller makes the selective setting.

3. The common mode voltage rejection (PWM) strategy with minimal switching loss of claim 2, wherein the PWM modulator setup includes a first ePWM generation mechanism and a second ePWM generation mechanism, v _n And the corresponding phases are generated by adopting a first ePWM generation mechanism, n belongs to { a, b and c }, and the other phases are generated by adopting a second ePWM generation mechanism.

4. The common-mode voltage rejection (PWM) strategy with minimal switching losses of claim 3, wherein the first ePWM generation mechanism comprises: comparing the comparison value with the count value of the ePWM, outputting a high level when the comparison value is greater than the count value when the count value rises, and outputting the high level when the comparison value is less than the count value when the count value falls; the second ePWM generation mechanism includes: the comparison value is compared with the count value of the ePWM, and when the count value rises, a high level is output when the comparison value is smaller than the count value, and when the count value falls, a high level is output when the comparison value is larger than the count value.

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