CN113131726B - Common mode voltage rejection PWM strategy with minimal switching losses - Google Patents

Common mode voltage rejection PWM strategy with minimal switching losses Download PDF

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CN113131726B
CN113131726B CN202110414751.8A CN202110414751A CN113131726B CN 113131726 B CN113131726 B CN 113131726B CN 202110414751 A CN202110414751 A CN 202110414751A CN 113131726 B CN113131726 B CN 113131726B
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epwm
count value
pwm
mode voltage
generation mechanism
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CN113131726A (en
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梁光耀
徐军忠
刘广财
季必胜
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Tianjin Qinxuan Information Technology Co ltd
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Jiaxing Fuer Electronic Technology Co ltd
Shanghai Baozhun Power Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention discloses a common-mode voltage suppression PWM strategy with minimum switching loss, which comprises the steps of using a PWM modulator on a three-phase voltage source inverter to generate driving signals Sa, Sb and Sc of a three-phase two-level frequency converter. The common mode voltage suppression PWM strategy of the invention realizes minimum switching loss in a full power factor range, improves the system efficiency and can effectively suppress the common mode voltage.

Description

Common mode voltage rejection PWM strategy with minimal switching losses
Technical Field
The invention belongs to the technical field of power electronic control, and particularly relates to a common-mode voltage suppression PWM strategy with minimum switching loss.
Background
With the wide application of new wide bandgap semiconductors (e.g., SiC, GAN, etc.) in frequency converters, some negative effects come along. Especially, the high-frequency common mode voltage can generate bearing current on a rotating shaft of the motor, so that the aging of the motor is accelerated, and the service life of the motor is shortened. Wide bandgap semiconductor devices also result in more severe common mode currents due to faster switching. This common mode current will flow into earth through the electrostatic coupling between the stator windings and the machine housing and return to the grid via the ground conductor. This not only can cause protection device malfunction, but also can produce great common mode electromagnetic interference, influences the safety of using electricity.
Disclosure of Invention
In order to solve the technical problems, the invention adopts the technical scheme that: the common-mode voltage suppression PWM strategy with the minimum switching loss comprises the steps of using a PWM modulator on a three-phase voltage source inverter to generate driving signals Sa, Sb and Sc of a three-phase two-level frequency converter and a modulation wave v of the driving signals Sa, Sb and Sc a ** 、v b ** 、v c ** The expression of (a) is:
Figure BDA0003025383250000011
wherein v is a * ,v b * And v c * Is a reference voltage, v, output by a controller in a three-phase voltage source inverter 0 Is a zero sequence voltage componentAn amount; v. of 0 The expression of (a) is:
Figure BDA0003025383250000021
i∈{a,b,c}。
preferably, said v represents 0 The generation steps are as follows:
(1) obtaining a reference voltage v a * ,v b * And v c * And current sample value i a 、i b 、i c (ii) a (2) Calculation | v m ∣ * ＝min(∣v a * ∣,∣v b * ∣,∣v c * | i) and | i n ∣ * ＝min(∣i a ∣,∣i b ∣,∣i c ∣),m,n∈{a、b、c}；
(2) Judging whether m is equal to n or not, and obtaining u when m is equal to n i * ＝u n * And when m is not equal to n, judging | i p If | i is greater than | i q | wherein p, q ∈ a, b, c and p, q ≠ n, when | i p ∣>∣i q | then obtain u i * ＝u p * When | i p | is not greater than | i q | then obtain u i * ＝u q * ；
(3) According to u obtained in step (2) i * Using the formula: u. of 0 ＝sign(u i * )·U dc /2-u i * Synthesis to obtain v 0 A zero sequence voltage component.
Preferably, said v represents 0 And after the zero sequence voltage components are synthesized, the PWM modulator is selectively set.
Preferably, the PWM modulator includes a first ePWM generating mechanism and a second ePWM generating mechanism, v n And the corresponding phases are generated by adopting a first ePWM generation mechanism, n belongs to { a, b and c }, and the other phases are generated by adopting a second ePWM generation mechanism.
The invention has the beneficial effects that: the common mode voltage suppression PWM strategy of the invention realizes minimum switching loss in a full power factor range, improves the system efficiency and can effectively suppress the common mode voltage.
Drawings
FIG. 1 is a schematic diagram of an algorithm synthesis of a common mode voltage rejection PWM strategy;
FIG. 2 is a flow chart of zero sequence voltage component synthesis;
FIG. 3 is a schematic diagram of ePWM module setup in the controller;
FIG. 4 is a comparison of the effective value of the common mode voltage;
FIG. 5 is a graph comparing loss characteristics (SLF) of different PWM methods;
fig. 6 is a block diagram of a three-phase voltage source converter topology and control.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The common-mode voltage suppression PWM strategy with minimum switching loss comprises the steps of using a PWM modulator on a three-phase voltage source inverter to generate driving signals Sa, Sb and Sc of a three-phase two-level frequency converter and a modulation wave v of the driving signals Sa, Sb and Sc a ** 、v b ** 、v c ** The expression of (a) is:
Figure BDA0003025383250000041
wherein v is a * ,v b * And v c * Is a reference voltage, v, output by a controller in a three-phase voltage source inverter 0 Is the zero sequence voltage component; v. of 0 The expression of (a) is:
Figure BDA0003025383250000042
i belongs to { a, b, c }. V is 0 The generation steps are as follows:
(1) obtaining a reference voltage v a * ,v b * And v c * And current sample value i a 、i b 、i c (ii) a (2) Calculation | v m ∣ * ＝min(∣v a * ∣,∣v b * ∣,∣v c * | i) and | i n ∣ * ＝min(∣i a ∣,∣i b ∣,∣i c ∣),m,n∈{a、b、c}；
(2) Judging whether m is equal to n or not, and obtaining u when m is equal to n i * ＝u n * And when m is not equal to n, judging | i p If | i is greater than | i q | wherein p, q ∈ a, b, c and p, q ≠ n, when | i p ∣>∣i q | then obtain u i * ＝u p * When | i p | is not greater than | i q | then obtain u i * ＝u q * ；
(3) According to u obtained in step (2) i * Using the formula: u. of 0 ＝sign(u i * )·U dc /2-u i * Synthesis to obtain v 0 A zero sequence voltage component.
Further, said v 0 And after the zero sequence voltage components are synthesized, the PWM modulator is selectively set. The PWM modulator comprises a first ePWM generating mechanism and a second ePWM generating mechanism, v n And the corresponding phases are generated by adopting a first ePWM generation mechanism, n belongs to { a, b and c }, and the other phases are generated by adopting a second ePWM generation mechanism. For example, V n ＝V a Then phase a is generated using a first ePWM generation mechanism and phase b, c is generated using a second ePWM generation mechanism.
Specifically, it is implemented according to the process shown in fig. 6. The invention realizes the minimum common mode voltage algorithm by a carrier PWM method to generate driving signals Sa, Sb and Sc of a three-phase two-level frequency converter, as shown in figure 1. Its modulated wave v a ** ,v b ** And v c ** The expression of (a) is:
Figure BDA0003025383250000051
wherein v is a * ,v b * And v c * Is a reference voltage, v, output by the controller 0 Is the generated zero sequence voltage component. Zero sequence voltage component v 0 The expression of (a) is:
Figure BDA0003025383250000052
i belongs to { a, b, c }. Zero sequence voltage component v 0 Obtained by means of the flow chart shown in figure 2. After the zero sequence voltage component synthesis is completed, the carrier wave of the proposed algorithm needs to be operated, wherein v n The corresponding phases use the first ePWM generation mechanism shown in fig. 3(b) in the control chip used, and the other phases use the second ePWM generation mechanism shown in fig. 3 (a).
By calculating the effective value of the common mode voltage, the common mode of the PWM method provided by the invention can be foundThe voltage value is much smaller than that of the conventional space vector modulation method, as shown in fig. 4. According to the calculation method of switching loss characteristics (SLF) proposed in the document [ Simple Analytical and Graphical Methods for Carrier-Based PWM-VSI drivers ], it can be found that the SLF of the PWM method proposed by the present invention satisfies the following formula:
Figure BDA0003025383250000053
wherein,
Figure BDA0003025383250000054
expressed as power factor angle. It can be seen that this strategy achieves smaller SLF results than any other modulation method, as shown in fig. 5.
It should be noted that the technical features of the three-phase voltage source inverter, the PWM modulator, and the like, which are referred to in the present patent application, should be regarded as the prior art, and the specific structure, the operation principle, the control manner and the spatial arrangement manner that may be referred to in the present patent application may be implemented by conventional selection in the art, and should not be regarded as the invention point of the present patent application, and the present patent application is not further specifically described in detail.
Having described preferred embodiments of the present invention in detail, it is to be understood that modifications and variations may be resorted to without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (4)

1. The common-mode voltage suppression PWM strategy with the minimum switching loss is characterized by comprising the steps of using a PWM modulator on a three-phase voltage source inverter to generate driving signals Sa, Sb and Sc of a three-phase two-level frequency converter and a modulation wave v of the driving signals Sa, Sb and Sc a ** 、v b ** 、v c ** The expression of (a) is:
Figure FDA0003664721180000011
wherein v is a * ,v b * And v c * Is a reference voltage, v, output by a controller in a three-phase voltage source inverter 0 Is the zero sequence voltage component; v. of 0 The expression of (a) is:
Figure FDA0003664721180000012
v is 0 The generation steps are as follows:
(1) obtaining a reference voltage v a * ,v b * And v c * And current sample value i a 、i b 、i c ；
(2) Calculation | v m ∣ * ＝min(∣v a * ∣,∣v b * ∣,∣v c * | i) and | i n ∣ * ＝min(∣i a ∣,∣i b ∣,∣i c ∣),m,n∈{a、b、c}；
(3) Judging whether m is equal to n or not, and obtaining v when m is equal to n i * ＝v n * And when m is not equal to n, judging | i p If | i is greater than | i q | wherein p, q ∈ a, b, c and p, q ≠ n, when | i p ∣>∣i q | get v i * ＝v p * When | i p | is not greater than | i q | get v i * ＝v q * ；
(4) According to v obtained in step (3) i * Using the formula:
Figure FDA0003664721180000013
synthesis to obtain v 0 A zero sequence voltage component.
2. The common-mode voltage rejection PWM strategy with minimal switching loss as in claim 1, wherein said v 0 After the zero sequence voltage components are synthesized, PWM is adjustedThe controller makes the selective setting.
3. The common mode voltage rejection (PWM) strategy with minimal switching loss of claim 2, wherein the PWM modulator setup includes a first ePWM generation mechanism and a second ePWM generation mechanism, v n And the corresponding phases are generated by adopting a first ePWM generation mechanism, n belongs to { a, b and c }, and the other phases are generated by adopting a second ePWM generation mechanism.
4. The common-mode voltage rejection (PWM) strategy with minimal switching losses of claim 3, wherein the first ePWM generation mechanism comprises: comparing the comparison value with the count value of the ePWM, outputting a high level when the comparison value is greater than the count value when the count value rises, and outputting the high level when the comparison value is less than the count value when the count value falls; the second ePWM generation mechanism includes: the comparison value is compared with the count value of the ePWM, and when the count value rises, a high level is output when the comparison value is smaller than the count value, and when the count value falls, a high level is output when the comparison value is larger than the count value.
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