CN113130494A

CN113130494A - Memory device and method of manufacturing the same

Info

Publication number: CN113130494A
Application number: CN202010702786.7A
Authority: CN
Inventors: 崔康植
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2019-12-30
Filing date: 2020-07-21
Publication date: 2021-07-16
Also published as: TW202125771A; US11700725B2; US20210202488A1; KR20210085417A; US11329046B2; US20220238527A1; US20230309290A1

Abstract

The memory device includes: a substrate; an active layer spaced apart from and laterally oriented to the substrate; word lines laterally oriented parallel to the active layer along one side of the active layer; an active body vertically oriented by penetrating the active layer; a bit line vertically oriented to be spaced apart from one side of the active body by penetrating the active layer; and a capacitor vertically oriented to be spaced apart from the other side of the active body by penetrating the active layer.

Description

Memory device and method of manufacturing the same

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2019-0178427, filed on 30.12.2019, the entire contents of which are incorporated herein by reference.

Technical Field

Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same.

Background

Recently, the size of memory cells has continued to decrease in order to increase the net die of memory devices.

As the memory cell size is miniaturized, the parasitic capacitance Cb decreases and the capacitance increases. However, it is difficult to increase the net die due to structural limitations of the memory cell.

Disclosure of Invention

Embodiments of the present invention relate to a highly integrated memory cell, a memory device including the integrated memory cell, and a method of manufacturing the memory device.

According to one embodiment of the present invention, a memory device includes: a substrate; an active layer spaced apart from and laterally oriented to the substrate; word lines laterally oriented parallel to the active layer along one side of the active layer; an active body (active body) vertically oriented by way of penetrating the active layer; a bit line vertically oriented by penetrating the active layer to be spaced apart from one side of the active body; and a capacitor vertically oriented by penetrating the active layer to be spaced apart from the other side of the active body.

According to another embodiment of the present invention, a storage device includes storage units arranged in a vertical direction, wherein each of the storage units includes: an active layer comprising a first source/drain region, a second source/drain region, and a channel body (channel body) oriented laterally between the first source/drain region and the second source/drain region; word lines laterally oriented parallel to one side of the active layer; an active body extending through the channel body; a bit line vertically oriented through the active layer coupled with the first source/drain region; and a capacitor vertically oriented through the active layer to couple with the second source/drain region.

According to still another embodiment of the present invention, a method for manufacturing a memory device includes: forming a plurality of active layers arranged in a vertical direction with respect to a substrate; forming a vertically oriented active body that interconnects the active layers to each other throughout the active layers; forming a vertically oriented bit line spaced apart from one side of the active body and penetrating the active layer; forming a vertically oriented capacitor spaced apart from the other side of the active body and penetrating the active layer; and forming a plurality of word lines oriented laterally adjacent to one side of each of the active layers.

These and other features and advantages of the present invention will become apparent to those skilled in the art to which the present invention pertains from the following detailed description and the accompanying drawings.

Drawings

Fig. 1A is a perspective view schematically showing the structure of a memory device according to an embodiment of the present invention.

FIG. 1B is a plan view of the memory device taken along line A-A' of FIG. 1.

FIG. 1C is a cross-sectional view of the memory device taken along line B-B' of FIG. 1B.

Fig. 2A and 2B are sectional views illustrating a memory device according to another embodiment of the present invention.

Fig. 3A to 26B are cross-sectional views illustrating a method of manufacturing a memory device according to an embodiment of the present invention.

Fig. 27A and 27B show a stepped word line structure.

Fig. 28 to 30 illustrate a method for manufacturing a memory device according to another embodiment of the present invention.

Fig. 31 to 33 illustrate memory devices according to other embodiments of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers to not only a case where the first layer is directly formed on the second layer or the substrate but also a case where a third layer is present between the first layer and the second layer or the substrate.

According to an embodiment of the present invention, a memory device may include: at least one laterally extending active layer (also referred to as a lateral active layer); at least one word line WL; a vertical bit line BL penetrating the at least one active layer; and a vertical capacitor also extending through the at least one active layer. The at least one single word line WL may be at the same distance (level) from the substrate as the at least one lateral active layer.

Fig. 1A is a perspective view schematically showing the structure of a memory device 100M according to an embodiment of the present invention. Fig. 1B is a plan view of the memory device 100M taken along line a-a 'of fig. 1A, and fig. 1C is a cross-sectional view of the memory device 100M taken along line B-B' of fig. 1B.

Referring to fig. 1A to 1C, the memory device 100M may include: a substrate SS; an active layer ACT oriented laterally and spaced apart from the substrate SS; word lines WL laterally oriented parallel to the active layer ACT along one side of the active layer ACT; an active body ACB vertically oriented and penetrating the active layer ACT; a bit line BL vertically oriented and penetrating the active layer ACT to be spaced apart from one side of the active body ACB; and a capacitor CAP vertically oriented and penetrating the active layer ACT to be spaced apart from the other side of the active body ACB.

The substrate SS may provide a plane extending in the first direction D1 and the third direction D3. The memory cell array MCA may be positioned vertically above the substrate SS in the second direction D2. The second direction D2 may be perpendicular to the first direction D1 and the third direction D3. The second direction D2 may be referred to simply as a vertical direction or a vertical orientation. The memory cell array MCA may include a plurality of memory cells MC vertically arranged in the second direction D2. The memory cell array MCA may be located over the substrate SS. The memory cell MC may be located over the substrate SS. For example, the memory cell array MCA may be or may include a Dynamic Random Access Memory (DRAM) memory cell array.

Each memory cell MC may include an active layer ACT, a word line WL, a bit line BL, and a capacitor CAP. The plurality of active layers ACT may be vertically arranged in the second direction D2. The active layers ACT may vertically overlap in the second direction D2. Each active layer ACT may have a plate shape having a cross section with a plurality of fingers. In other words, each active layer ACT may have a first elongated portion extending laterally in the first direction D1 and a plurality of fingers extending from the elongated portion in the third direction D3. The fingers may be spaced apart from each other at regular intervals. The fingers may have the same shape and size, however, the present invention is not limited thereto. The first finger of each active layer ACT may be a portion of the active layer ACT penetrated by the active body ACB. The second finger of each active layer ACT may be a portion of the active layer ACT penetrated by the bit line BL, and the third finger of each active layer ACT may be a portion of the active layer ACT penetrated by the capacitor CAP. The active body ACB, the bit line BL, and the capacitor CAP may pass through the respective first, second, and third fingers along the center such that each finger leaves an equal portion on either of their respective sides in the first direction D1 and the third direction D3.

Each active layer ACT may include a first source/drain region FSD, a second source/drain region SSD, and a channel body CHB arranged between the first source/drain region FSD and the second source/drain region SSD in the first direction D1. The first source/drain region FSD, the second source/drain region SSD, and the channel body CHB may be located at the same distance.

The laterally oriented word lines WL may be positioned parallel to one side of each active layer ACT. The active body ACB may penetrate the plurality of active layers ACT arranged in the second direction D2. The active body ACB may be vertically oriented in the second direction D2. The active host ACB may be referred to as an "active pillar". The active body ACB may have a rectangular cross-section when viewed from above. The active body ACB may pass through the channel body CHB of each active layer while extending in the second direction D2. The channel body CHB of each active layer ACT may surround the active body ACB passing therethrough. Accordingly, each channel body CHB may be located at the same distance as the corresponding active layer ACT. The plurality of channel bodies CHB may vertically overlap in the second direction D2. The word lines WL may vertically overlap in the second direction D2. For example, as shown in the embodiment of fig. 1A, the ends of the word lines WL may form a stepped structure whose length in the first direction decreases stepwise from a bottom word line next to the substrate SS toward a top word line in the second direction.

The bit line BL may be vertically oriented in the second direction D2, and may penetrate each active layer ACT. The bit line BL may be coupled to the first source/drain region FSD. The bit line BL may also have a rectangular cross section when viewed from above. The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node (plate node) PN. The storage node SN may be formed in each active layer ACT to be coupled to the corresponding second source/drain region SSD. The dielectric layer DE and the plate node PN may extend in the second direction D2 and penetrate the active layer ACT.

The memory device 100M may further include a plurality of bit line contact nodes BLC (shown in fig. 1C) formed in each active layer ACT. Each contact node BLC is coupled to the first source/drain region FSD of the corresponding active layer ACT and the bit line BL. The memory device 100M may further include: a contact pad layer CL vertically oriented (i.e., extending in the second direction D2) so as to penetrate the bit line contact node BLC in the second direction D2 while surrounding sidewalls of the bit line BL. The bit line contact node BLC may also surround the bottom of the bit line BL. The bit line contact node BLC may not surround the top of the bit line BL.

The bit lines BL, the active body ACB, and the capacitor CAP may extend vertically upward from the substrate SS. Each of the plurality of active layers ACT may be located at the same distance from one word line WL. The active layer ACT may be parallel to the plane of the substrate SS.

As shown in fig. 1B, a gate dielectric layer GD may be formed between one side of the channel body CHB and the word line WL. Each word line WL having a generally elongated shape extending in the first direction D1 may further include a protrusion WLP extending laterally in the third direction D3 to be in direct contact with the gate dielectric layer GD. The portion of each word line WL extending in the first direction D1 may be referred to herein as a line portion WLL of the word line WL. The line portion WLL of each word line WL may be spaced apart from the first and second source/drain regions FSD and SSD of the corresponding active layer ACT.

The plate node PN and the dielectric layer DE may be each oriented perpendicular to the substrate SS in the second direction D2, and the dielectric layer DE may surround sidewalls of the plate node PN. The dielectric layer DE may also surround the bottom of the plate node PN. The plurality of storage nodes SN may be arranged perpendicular to the substrate SS in the second direction D2. The storage nodes SN may be formed in the respective active layers ACT and shaped to surround the dielectric layer DE and the plate node PN. The storage node SN may be located at the same distance from the word line WL in the second direction D3. The storage node SN may contact the capacitor contact node SNC. The capacitor contact node SNC may contact the second source/drain region SSD. The capacitor contact node SNC may surround the storage node SN. The storage node SN and the capacitor contact node SNC may be located at the same distance. The storage node SN may have a rectangular ring shape in plan view (see fig. 1B).

Fig. 2A and 2B are sectional views illustrating a memory device 100 according to another embodiment of the present invention.

Referring to fig. 2A and 2B, the memory device 100 may include a peripheral circuit 110, a lower structure 120, and a memory cell array 130M, the lower structure 120 and the memory cell array 130M being sequentially formed over the peripheral circuit 110.

The peripheral circuitry 110 may include a plurality of control circuits. At least one control circuit in peripheral circuitry 110 may include N-channel transistors, P-channel transistors, CMOS circuitry, or a combination thereof. At least one control circuit in the peripheral circuits 110 may include an address decoder circuit, a read circuit, a write circuit, and the like. The at least one control circuit in the peripheral circuit 110 may include a planar channel transistor, a recessed channel transistor, a buried gate type transistor, a fin type channel transistor (FinFET), and the like.

The memory cell array 130M may include a DRAM memory cell array, and the peripheral circuit 110 may include a sense amplifier SA. The sense amplifier SA may be coupled to the multi-level metal wiring MLM.

The lower structure 120 may include an etch stop layer 121 and a lower interlayer dielectric ILD 122. The etch stop layer 121 may include a material having an etch selectivity in a series of etching processes for forming the subsequent memory cell array 130M. For example, the etch stop layer 121 may include a polysilicon layer. The etch stop layer 121 may be formed by depositing a polysilicon layer and etching the polysilicon layer. The etch stop layer 121 may be formed in a shape having a plurality of etch stop layer islands spaced apart from each other over the lower structure 120. The protective layer 123 may be formed on the surface of the etch stop layer 121.

The lower structure 120 may provide a plane extending in the first direction D1 and the third direction D3, and the memory cell array 130M may be positioned vertically above the lower structure 120 in the second direction D2. The second direction D2 may be perpendicular to the first direction D1 and the third direction D3. The memory cell array 130M may include a plurality of memory cells MC vertically arranged in the second direction D2. The first dielectric material 131 may be formed between the memory cells MC to be vertically arranged in the second direction D2. The first dielectric material 131 and the memory cells MC may be vertically alternately formed in the second direction D2. The second dielectric material 132 surrounding the memory cell MC may be formed between the first dielectric materials 131 in the vertical direction. In one embodiment, the first dielectric material 131 may, for example, comprise silicon oxide and the second dielectric material 132 may, for example, comprise silicon nitride.

Each memory cell MC may include an active layer 151, a word line 173, a bit line 184, and a capacitor 195. These active layers 151 may be vertically arranged in the second direction D2. Each active layer 151 may include a first source/drain region 163, a second source/drain region 164, and a channel body 157, the channel body 157 being laterally oriented in a direction D1 between the first source/drain region 163 and the second source/drain region 164. The first source/drain region 163, the second source/drain region 164, and the channel body 157 may be located at the same distance. The word lines 173 may be positioned to be laterally oriented parallel to one side of each active layer 151. The active body 156 may be formed to penetrate the active layer 151. The active body 156 may extend through the channel body 157 in the second direction D2. The bit line 184 may be vertically oriented in the second direction D2, and may penetrate the active layer 151 to be coupled to the first source/drain region 163. The capacitor 195 may include a storage node 192, a dielectric layer 193, and a plate node 194. The storage node 192 may be formed in the active layer 151 to be coupled to the second source/drain region 164. The dielectric layer 193 and the plate node 194 may penetrate the active layer 151.

The memory device 100M may further include a bit line contact node 183 formed in the active layer 151 and coupled to the first source/drain region 163 and the bit line 184. The memory device 100 may further include a contact pad layer 182 vertically oriented in the second direction D2 to penetrate the bit line contact node 183 while surrounding sidewalls of the bit line 184.

The side of the active layer 151 may be covered by the protective layer 134. A portion of the protection layer 134 may be cut, and one side of the active layer 151 may be partially exposed by the cut protection layer 134. Here, the exposed side may be a portion of the first source/drain region 163, the second source/drain region 164, and the channel body 157.

Gate dielectric layer 172 may be formed between one side of channel body 157 and word line 173. An isolation dielectric layer 165 may be formed between the first and second source/

drain regions

163 and 164 and the word line 173. The word lines 173 may contact a slit (slit) dielectric layer 174. As will be described later, the plurality of word lines 173 may be isolated from each other by the slit dielectric layer 174.

The board node 194 and the dielectric layer 193 may be vertically oriented with respect to the lower structure 120 in the second direction D2, and the dielectric layer 193 may surround sidewalls of the board node 194. The plurality of storage nodes 192 may be vertically arranged with respect to the lower structure 120 in the second direction D2. The storage node 192 may be formed in the active layer 151. The storage node 192 may be formed to surround the dielectric layer 193 and the plate node 194. The storage node 192 and the word line 173 may be located at the same distance from the peripheral circuit 110 along the second direction D2. The storage node 192 may contact the capacitor contact node 192C. The capacitor contact node 192C may contact the second source/drain region 164. The capacitor contact node 192C may surround the storage node 192. The storage node 192 and the capacitor contact node 192C may be located at the same distance. The storage node 192 may have a transverse ring shape.

The bit line contact node 183 may be coupled to the first source/drain region 163, and the storage node 192 may be coupled to the second source/drain region 164. The bit line contact node 183, the storage node 192, and the channel body 157 may be laterally arranged in the first direction D1.

Each active layer 151 may be laterally oriented in the first direction D1. Word lines 173 may be oriented laterally in a first direction D1. The active layers 151 may be vertically stacked in the second direction D2. The word lines 173 may be vertically stacked in the second direction D2. The active layer 151 and the word line 173 may be parallel to each other. The active layer 151 and the word line 173 may be located at the same lateral distance. The end of the word line 173 may have a step shape in the second direction D2. In other words, the word lines 173 stacked in the second direction D2 may have different lengths. The bit line 184 and the capacitor 195 may be vertically oriented in a second direction D2. The bit line contact node 183 may extend in the third direction D3 from the first source/drain region 163. The storage node 192 may extend in the third direction D3 from the second source/drain region 164.

Fig. 3A to 26B are cross-sectional views illustrating a method of manufacturing a memory device according to an embodiment of the present invention. Fig. 3A to 26A are plan views, and fig. 3B to 26B are sectional views.

Fig. 3B is a sectional view taken along line a-a' of fig. 3A.

Referring to fig. 3A and 3B, the lower structure 120 and the upper structure 130 may be sequentially formed over the peripheral circuit 110.

The peripheral circuit 110 may be made of a material suitable for semiconductor processing. The peripheral circuitry 110 may include at least one of a conductive material, a dielectric material, and a semiconductor material. Various materials may be formed in the peripheral circuit 110. The peripheral circuit 110 may include a semiconductor substrate, and the semiconductor substrate may be formed of a material including silicon. For example, the peripheral circuitry 110 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon doped silicon, combinations thereof, or multilayers thereof. Peripheral circuitry 110 may include other semiconductor materials, such as germanium. The peripheral circuitry 110 may include a group III/V semiconductor substrate, such as a compound semiconductor substrate, e.g., GaAs. The peripheral circuitry 110 may include a silicon-on-insulator (SOI) substrate.

According to another embodiment of the present invention, the peripheral circuit 110 may include a semiconductor substrate and a plurality of integrated circuits formed on the semiconductor substrate. For example, the peripheral circuitry 110 may include a plurality of control circuits. The control circuitry of the peripheral circuitry 110 may include at least one of: n-channel transistors, P-channel transistors, CMOS circuits, address decoder circuits, read circuits, write circuits, planar channel transistors, recessed channel transistors, buried gate transistors, fin channel transistors (finfets), and the like. In one embodiment, the at least one control circuit in the peripheral circuits 110 may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof, the at least one control circuit in the peripheral circuits 110 may include an address decoder circuit, a read circuit, a write circuit, and the like, and the at least one control circuit in the peripheral circuits 110 may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like.

Although not shown, the peripheral circuit 110 may include a sense amplifier SA, and the sense amplifier SA may be coupled to a multi-level metal wiring (MLM).

The lower structure 120 may include an etch stop layer 121 and a lower interlayer dielectric layer 122. The etch stop layer 121 may include a material having an etch selectivity during a subsequent etching process of the upper structure 130. For example, the etch stop layer 121 may include a polysilicon layer. The etch stop layer 121 may be formed by depositing a polysilicon layer and etching the polysilicon layer to form a plurality of etch stop layer islands (i.e., spaced apart regions) formed spaced apart from each other over the peripheral circuit 110.

After forming the etch stop layer 121 having a plurality of islands over the peripheral circuit 110, a lower interlayer dielectric layer 122 may be formed to fill spaces between the islands of the etch stop layer 121. The lower interlayer dielectric layer 122 may be formed by depositing a dielectric material on the peripheral circuit 110 including the etch stop layer 121 and then performing planarization.

The lower interlayer dielectric layer 122 may include, for example, an oxide.

The upper structure 130 may include a first material layer 131 and a second material layer 132. The upper structure 130 may include a plurality of first material layers 131 and a plurality of second material layers 132. The upper structure 130 may be an alternating stack in which a first material layer 131 is alternately stacked with a second material layer 132. The first material layer 131 and the second material layer 132 may be different materials. The first material layer 131 and the second material layer 132 may have different etching selectivity.

In one embodiment, the first material layer 131 may include silicon oxide, and the second material layer 132 may include silicon nitride. The stack of the first material layer 131 and the second material layer 132 may be referred to as an "oxide-nitride (ON) stack", and the upper structure 130 may include at least one ON stack. The number of ON stacks may be set to correspond to the number of memory cells.

The first material layer 131 may be located at the lowermost and uppermost portions of the upper structure 130, respectively. The lowermost first material layer 131 and the uppermost first material layer 131 may be thicker than the remaining first material layers 131. The first material layer 131 and the second material layer 132 may have the same thickness except for the lowermost first material layer 131 and the uppermost first material layer 131.

Hereinafter, in a plan view, reference numerals of the lower structure 120 between the peripheral circuit 110 and the upper structure 130 will be omitted.

Fig. 4B is a sectional view taken along line a-a' of fig. 4A. Referring to fig. 4A and 4B, a portion (i.e., a first region) of the upper structure 130 may be etched using a first mask M1. The etching process of the first region of the upper structure 130 may be performed until it ends at the etch stop layer 121. As a result, a plurality of cell openings 140 may be formed through the upper structure 130. The first region of the upper structure 130 may be dry etched to form the cell opening 140.

The first mask M1 may be an etch stop layer during the process of etching the upper structure 130. The first mask M1 may include a photoresist pattern. According to another embodiment of the invention, the first mask M1 may comprise a hard mask material. The first mask M1 may include amorphous carbon or polysilicon.

To prevent the cell opening 140 from being left unopened, the process of etching the cell opening 140 may include over-etching. As a result, the bottom of the cell opening 140 may partially extend into the island of the etch stop layer 121. In other words, a concave surface may be formed on the surface of each island of the etch stop layer 121.

The cell opening 140 is a vertical opening that is vertically oriented from the lower structure 120 and may extend vertically to the upper surface of the etch stop layer 121 and through the upper structure 130. The sidewalls of the cell opening 140 may have a vertical profile. The cell opening 140 may refer to an area: in which a portion of a plurality of memory cells is to be formed.

From a top view perspective, the cell opening 140 may include a plurality of fingers. The cell openings 140 may be finger-shaped openings. For example, the cell opening 140 may include a first finger 141, a second finger 142, and a third finger 143. Hereinafter, the first finger 141 may be referred to as a first cell opening 141, the second finger 142 may be referred to as a second cell opening 142, and the third finger 143 may be referred to as a third cell opening 143.

As shown in fig. 4A, the first, second, and

third cell openings

141, 142, and 143 may be coupled to each other. The first cell opening 141 may provide a space in which an active body is to be formed, the second cell opening 142 may provide a space in which a bit line is to be formed, and the third cell opening 143 may define a space in which a capacitor is to be formed. The first cell opening 141 may be referred to as an "active body opening", and the second cell opening 142 may be referred to as a "bit line opening". The third cell opening 143 may be referred to as a "capacitor opening".

From a top view perspective, the first unit opening 141 may be located at the center, the second unit opening 142 may be located at one side (or left side) of the first unit opening 141, and the third unit opening 143 may be located at the other side (or right side) of the first unit opening 141. The opening area of the third unit opening 143 may be larger than the first unit opening 141 and the second unit opening 142. Since the third cell opening 143 is made larger, the size of a capacitor to be formed later can be increased. As a result, the capacitance can be sufficiently ensured.

As described above, the cross-section of the cell opening 140 may have a multi-finger shape. The first, second, and

third cell openings

141, 142, and 143 may be arranged side by side in the shape of a multi-finger. From a top view, the cell opening 140 may have an elongated portion extending in the first direction D1 from which three

fingers

141, 142, and 143 protrude laterally in the third direction D3.

The second material layer 132 may be replaced with the active layer 151 through the following series of processes. A portion of the active layer 151 may be replaced with a channel body 157, a bit line contact node 183, and a storage node 192.

Fig. 5B is a sectional view taken along line a-a' of fig. 5A. Referring to fig. 5A and 5B, the protective layer 123 may be formed by oxidizing the recess surface of the etch stop layer 121. The protective layer 123 may be formed by exposing the recessed surface of the etch stop layer 121 to a thermal oxidation process. For example, when the etch stop layer 121 includes polysilicon, the protective layer 123 may be formed of silicon oxide. The protective layer 123 may protect the etch stop layer 121 in a subsequent process. Also, the protective layer 123 may electrically insulate the subsequent bit line and capacitor from the etch stop layer 121.

The protective layer 123 may not fill the bottom of the cell opening 140, i.e., the recessed surface of the etch stop layer 121. The protective layer 123 may be conformally formed on the recessed surface of the etch stop layer 121.

Fig. 6B is a sectional view taken along line a-a' of fig. 6A. Referring to fig. 6A and 6B, a portion of the upper structure 130 may be selectively recessed through the cell opening 140. For example, second material layer 132 of upper structure 130 may be selectively recessed laterally. A plurality of lateral recesses 133 may be formed in the upper structure 130 by laterally recessing (e.g., etching) the second material layer 132. The lateral recess 133 may be formed between the vertically stacked first material layers 131. The lateral recessing of second material layer 132 may be performed by wet etching or dry etching. For example, when the second material layer 132 includes silicon nitride, the lateral recess 133 may be formed by wet etching of silicon nitride.

The lateral recess 133 may laterally extend into the upper structure 130 from the side of the first to

third unit openings

141, 142 and 143. As a result, the lateral recesses 133 may extend from the sides of the first, second, and

third cell openings

141, 142, and 143, respectively.

Fig. 7B is a sectional view taken along line a-a' of fig. 7A. Referring to fig. 7A and 7B, the side of the second material layer 132 may be selectively oxidized. As a result, the sidewalls of the lateral recess 133 may be covered by selective oxides 134. For example, when the second material layer 132 includes silicon nitride, the selective oxide 134 may include silicon oxynitride.

Subsequently, an active material 150 may be deposited. The active material 150 may fill the lateral recess 133. The active material 150 may cover sidewalls of the first to

third cell openings

141, 142 and 143, and may not fill the first to

third cell openings

141, 142 and 143. In other words, the active material 150 may conformally cover sidewalls of the first to

third cell openings

141, 142 and 143 while filling the lateral recess 133. Each selective oxide 134 may be located between the active material 150 and the second material layer 132. The active material 150 may include a semiconductor material. The active material 150 may include polysilicon. The active material 150 may include P-type polysilicon or undoped polysilicon. The thickness of the active material 150 may be adjusted to fill the lateral recess 133 without a gap.

Fig. 8B is a sectional view taken along line a-a' of fig. 8A. Referring to fig. 8A and 8B, an active isolation process may be performed. For example, the active material 150 may be selectively etched to form active layers 151 in the lateral recesses 133, respectively. The active layers 151 respectively formed in the lateral recesses 133 may be isolated from each other in the vertical direction. Sidewalls of the active layers 151 may be respectively covered with the selective oxide 134. The selective oxide 134 may be respectively located between the active layer 151 and the second material layer 132.

The active layer 151 may have a closed ring shape from a top view point. Accordingly, the first cell opening 141, the second cell opening 142, and the third cell opening 143 may be formed to penetrate the vertically stacked active layer 151. The active layer 151 may include a plurality of fingers. Each finger may be penetrated by the first through third cell openings 141 through 143 therein.

Fig. 9B is a sectional view taken along line a-a' of fig. 9A. Referring to fig. 9A and 9B, a sacrificial liner layer 152 may be formed to protect the active layer 151. The sacrificial liner layer 152 may include a dielectric material. For example, the sacrificial liner layer 152 may be formed of silicon nitride or silicon oxide.

A sacrificial material 153 may be formed on the sacrificial liner layer 152. The sacrificial material 153 may fill the first to

third cell openings

141, 142 and 143 on the sacrificial liner layer 152. Sacrificial material 153 may comprise a metal-based material. The sacrificial material 153 may include metal and metal nitride. Sacrificial material 153 may include tungsten. The sacrificial material 153 may be planarized to remain only inside the first to

third cell openings

141, 142 and 143.

An upper interlayer dielectric layer (ILD)154 may be formed over the sacrificial material 153. The upper interlayer dielectric layer 154 may include silicon oxide.

As described above, a plurality of active layers 151 may be formed in the upper structure 130. The active layer 151 and the first material layer 131 may be alternately stacked in a vertical direction. The sides of the active layer 151 may be surrounded by the second material layers 132, respectively. The upper structure 130 may be referred to as a mold structure (mold structure), and the mold structure may include: and an alternate lamination in which the active layer 151 and the first material layer 131 are alternately laminated in a vertical direction.

Fig. 10B is a sectional view taken along line a-a' of fig. 10A. Referring to fig. 10A and 10B, the first cell opening 141 may be exposed again. To this end, the sacrificial liner layer 152 and the sacrificial material 153 filling the first cell opening 141 may be selectively removed. For example, by using the second mask M2, a portion of the upper interlayer dielectric layer 154 may be etched to expose a portion corresponding to the first cell opening 141, and then the sacrificial liner layer 152 and the sacrificial material 153 filling the first cell opening 141 may be etched.

As described above, the exposed first cell opening 141 may be simply referred to as an "active body opening 155". A portion of each active layer 151 may be exposed through the active body opening 155.

The active body opening 155 can be oriented vertically with respect to the substructure 120.

Fig. 11B is a sectional view taken along line a-a' of fig. 11A. Referring to fig. 11A and 11B, after removing the second mask M2, the active body openings 155 may be filled with active bodies 156. The active body 156 may comprise P-type polysilicon. The active body 156 may be formed by depositing P-type polysilicon to fill the active body opening 155 and performing planarization. During the planarization of the P-type polysilicon, a portion of the sacrificial material 153 and the sacrificial liner layer 152 may be planarized.

The active body 156 may interconnect the active layers 151 positioned in the vertical direction. A body bias may be applied to the active body 156. The active body 156 may be cylindrical. The active body 156 may penetrate the active layers 151 stacked in the vertical direction.

Fig. 12B is a sectional view taken along line a-a' of fig. 12A. Referring to fig. 12A and 12B, when the active layer 151 includes undoped polysilicon, a heat treatment process may be subsequently performed to diffuse P-type impurities from the active body 156. Accordingly, a portion of the active layer 151 contacting the active body 156 may be doped with P-type impurities. The portion of the active layer 151 doped with the P-type impurity may be the channel body 157. The channel bodies 157 may be stacked in a vertical direction. At one level (level), the channel body 157 and the active layer 151 may be located at the same distance.

From a top view perspective, the channel body 157 may have a rounded shape around the active body 156. The active body 156 may be formed to penetrate the channel body 157 stacked in the vertical direction.

Fig. 13B is a sectional view taken along the line C-C 'of fig. 13A, and fig. 13C is a sectional view taken along the line D-D' of fig. 13A.

Referring to fig. 13A to 13C, an isolation opening 161 may be formed at a position spaced apart from the active layer 151. For example, after forming a third mask (not shown) over the upper structure 130, a second region of the upper structure 130 (here, which is a portion where the first to

third cell openings

141, 142, and 143 are not formed) may be etched using the third mask. As a result, when the upper interlayer dielectric layer 154, the plurality of first material layers 131, and the plurality of second material layers 132 are etched, a pair of isolation openings 161 isolated from each other may be formed. When the isolation opening 161 is formed to be laterally spaced apart from the active layer 151, the second material layer 132 may be selectively recessed from a sidewall of the isolation opening 161, thereby exposing one side of the active layer 151. According to another embodiment of the present invention, the etching process for forming the isolation opening 161 may be performed by: so that the sidewall of the isolation opening 161 exposes one side of the active layer 151. The isolation opening 161 may be vertically oriented in the stacking direction of the memory cells.

Subsequently, an impurity doping process 162 may be performed. Impurities may be doped onto the exposed portion of the active layer 151 through the isolation opening 161. As a result, the first source/drain region 163 and the second source/drain region 164 may be formed. The impurity doping process 162 may include an N-type impurity doping process. First source/drain region 163 and second source/drain region 164 may be N-type source/drain regions.

The first source/drain region 163 may be a portion to be subsequently coupled to a bit line, and the second source/drain region 164 may be a portion to be subsequently coupled to a capacitor.

The impurity doping process 162 may be performed by tilt ion implantation (tilt implantation). According to another embodiment of the present invention, the impurity doping process 162 may be performed by a plasma doping process.

The first source/drain region 163 and the second source/drain region 164 may be laterally spaced apart from one another by a channel body 157 therebetween. Accordingly, a lateral channel may be defined in the channel body 157 between the first source/drain region 163 and the second source/drain region 164.

Fig. 14B is a sectional view taken along line C-C 'of fig. 14A, and fig. 14C is a sectional view taken along line D-D' of fig. 14A.

Referring to fig. 14A through 14C, the isolation opening 161 may be filled with an isolation dielectric layer 165. The isolation dielectric layer 165 may include silicon oxide. The isolation dielectric layer 165 may be vertically oriented with respect to the lower structure 120. The isolation dielectric layer 165 may be referred to as a bonding isolation layer. The isolation dielectric layer 165 may face the first source/drain region 163 and the second source/drain region 164. The isolation dielectric layer 165 may be vertically oriented in the stacking direction of the memory cells.

Fig. 15B is a sectional view taken along line C-C 'of fig. 15A, and fig. 15C is a sectional view taken along line D-D' of fig. 15A. Fig. 15D is a sectional view taken along line B-B' of fig. 15A. Referring to fig. 15A to 15D, a slit 166 may be formed. The slit 166 may be formed around the isolation dielectric layer 165. The isolation dielectric layer 165 may be located between the active layer 151 and the slits 166. The slits 166 may be laterally spaced from the active layer 151.

The slit 166 may be formed by etching a third region of the upper structure 130. For example, the slits 166 may be formed in the third region of the upper structure 130 by etching the alternating stack of the upper interlayer dielectric layer 154, the first material layer 131, and the second material layer 132. The bottom of the slot 166 may be located on the top surface of the lower structure 120.

Fig. 16B is a sectional view taken along line C-C ' of fig. 16A, fig. 16C is a sectional view taken along line D-D ' of fig. 16A, and fig. 16D is a sectional view taken along line B-B ' of fig. 16A.

Referring to fig. 16A to 16D, the second material layer 132 may be selectively peeled off through the slits 166. As a result, the second material layer 132 may be selectively removed between the lateral isolation dielectric layers 165 located in the lateral direction. Also, the second material layer 132 may be selectively removed between the slits 166 and the isolation dielectric layer 165.

As described above, the lateral gate recess 171 may be formed between the first material layers 131 stacked in the vertical direction in a self-aligned manner through the selective removal process of the second material layer 132.

Lateral gate recess 171 may expose a portion of protective layer 134. After stripping the second material layer 132, a portion of the protection layer 134 may be removed to expose the channel body 157.

Fig. 17B is a sectional view taken along line C-C 'of fig. 17A, and fig. 17C is a sectional view taken along line D-D' of fig. 17A. Fig. 17D is a sectional view taken along line B-B' of fig. 17A.

Referring to fig. 17A through 17D, a gate dielectric layer 172 may be formed. Gate dielectric layer 172 may be formed by selectively oxidizing the surface of channel body 157 exposed by lateral gate recess 171.

Word lines 173 may be formed over gate dielectric layer 172 to fill lateral gate recesses 171. The word lines 173 may be formed of a metal-based material. The word line 173 may be formed by stacking titanium nitride and tungsten. For example, after forming titanium nitride conformally on the lateral gate recesses 171, the lateral gate recesses 171 may be filled with tungsten gaps. Subsequently, the titanium nitride and the tungsten may be etched back to form the word lines 173 isolated in the vertical direction. This may be referred to as a word line isolation process, and the edges of word lines 173 may be located inside lateral gate recesses 171. That is, the edge of the word line 173 may be formed with an undercut between the first material layers 131. According to another embodiment of the present invention, the word lines 173 may include polysilicon doped with impurities.

As described above, the plurality of word lines 173 may be stacked in the vertical direction. The first material layer 131 may be located between the word lines 173 stacked in the vertical direction. The plurality of first material layers 131 and the plurality of word lines 173 may be alternately stacked in a direction perpendicular to the lower structure 120. The word line 173 and the active layer 151 may be located at the same distance.

Fig. 18B is a sectional view taken along line C-C 'of fig. 18A, and fig. 18C is a sectional view taken along line D-D' of fig. 18A. Fig. 18D is a sectional view taken along line B-B' of fig. 18A.

Referring to fig. 18A through 18D, after forming the word lines 173, the slits 166 may be filled with a slit dielectric layer 174. For example, the slit dielectric layer 174 may include an oxide, such as silicon oxide.

Fig. 19B is a sectional view taken along line a-a' of fig. 19A. Referring to fig. 19A and 19B, a top interlayer dielectric layer 180 may be formed over the slit dielectric layer 174 and the upper structure 130. For example, the top interlayer dielectric layer 180 may include silicon oxide.

Subsequently, the sacrificial material 153 and the sacrificial protective layer 152 filling the second cell opening 142 may be removed to form the bit line opening 181. For example, after etching the top interlayer dielectric layer 180 of a portion corresponding to the second cell opening 142, the sacrificial material 153 and the sacrificial protective layer 152 filling the second cell opening 142 may be etched.

The protective layer 123 may be exposed on the bottom of the bit line opening 181. The bit line openings 181 may be vertically oriented with respect to the lower structure 120. The bit line opening 181 may have a shape vertically penetrating the active layer 151.

Fig. 20B is a sectional view taken along line a-a' of fig. 20A. Referring to fig. 20A and 20B, a first contact pad layer 182 may be formed to cover the bit line opening 181. The first contact liner layer 182 may contain impurities. For example, the first contact liner layer 182 may include N-type polysilicon.

Fig. 21B is a sectional view taken along line a-a' of fig. 21A. Referring to fig. 21A and 21B, a heat treatment may be performed to diffuse the N-type impurity from the first contact pad layer 182. As a result, the portion of the active layer 151 in contact with the first contact pad layer 182 may be doped with N-type impurities. The first contact pad layer 182 and the portion of the active layer 151 doped with N-type impurities may form a bit line contact node 183. From a top view perspective, the bit line contact node 183 may be formed to penetrate the upper structure 130 and may laterally extend to be located between the first material layers 131 while covering sidewalls of the bit line opening 181. Thus, a portion of the bit line contact node 183 may be a portion of the active layer 151 doped with N-type impurities.

According to another embodiment of the present invention, the first contact pad layer 182 may be removed after the thermal treatment. As such, the bit line contact node 183 may not cover sidewalls of the bit line opening 181, and may be located only between the first material layers 131. The bit line contact node 183 may be located at the same distance as the active layer 151 and may also be located at the same distance as the word line 173.

Fig. 22B is a sectional view taken along line a-a' of fig. 22A. Referring to fig. 22A and 22B, a bit line 184 may be formed on the bit line contact node 183 to fill the bit line opening 181. The bit lines 184 may be formed by forming a bit line conductive material to fill the bit line openings 181 and then performing planarization. The bit line 184 may include a metal-based material. The bit line 184 may comprise a stack of metal nitride and metal. For example, the bit line 184 may be formed by stacking titanium nitride and tungsten. According to another embodiment of the present invention, an ohmic contact layer (not shown) may be further formed between the bit line 184 and the bit line contact node 183. For example, the ohmic contact layer may include a metal silicide.

As described above, the bit lines 184 may be oriented vertically with respect to the lower structure 120. From a top view perspective, the bit line 184 may have a shape that intersects the bit line contact node 183. The bit line contact node 183 may have a shape surrounding the bit line 184.

Fig. 23B is a sectional view taken along line a-a' of fig. 23A. Referring to fig. 23A and 23B, the sacrificial material 153 and the sacrificial protective layer 152 filling the third cell opening 143 may be removed to form a capacitor opening 190. For example, after etching the top interlayer dielectric layer 180 and the upper interlayer dielectric layer 154 of a portion corresponding to the third cell opening 143, the sacrificial material 153 and the sacrificial protective layer 152 filling the second cell opening 143 may be etched. Although not shown, an additional hard mask layer may be further formed over the top interlayer dielectric layer 180, and the sacrificial material 153 and the sacrificial protective layer 152 may be removed by using the additional hard mask layer.

The protective layer 123 may be exposed on the bottom surface of the capacitor opening 190. The capacitor openings 190 may be oriented vertically with respect to the substructure 120. The capacitor opening 190 may be formed to vertically penetrate the active layer 151.

Fig. 24B is a sectional view taken along line a-a' of fig. 24A. Referring to fig. 24A and 24B, a second contact pad layer 191 may be formed to cover the capacitor opening 190. The second contact pad layer 191 may contain impurities. For example, the second contact pad layer 191 may include N-type polysilicon.

Fig. 25B is a sectional view taken along line a-a' of fig. 25A. Referring to fig. 25A and 25B, a heat treatment may be performed to diffuse the N-type impurity from the second contact pad layer 191. As a result, N-type impurities may be doped in a portion of the active layer 151 contacting the second contact pad layer 191. A portion of the active layer 151 doped with N-type impurities may be a storage node 192 of a capacitor. From a top view perspective, the storage node 192 may laterally extend to be located between the first material layers 131 while covering sidewalls of the capacitor opening 190. Thus, the storage node 192 may be part of: in which a portion of the active layer 151 is doped with N-type impurities. The storage nodes 192 may be stacked in a vertical direction with the first material layer 131 interposed therebetween. The storage nodes 192 may be alternately stacked with the first material layers 131.

Fig. 26B is a sectional view taken along line a-a' of fig. 26A. Referring to fig. 26A and 26B, after removing the second contact pad layer 191, a dielectric layer 193 and a plate node 194 may be formed on the storage node 192 to fill the capacitor opening 190.

The dielectric layer 193 may conformally cover the capacitor opening 190, and the plate node 194 may completely fill the capacitor opening 190 above the dielectric layer 193.

The dielectric layer 193 and the plate node 194 may be formed by: a dielectric material and a plate node layer are deposited over the capacitor opening 190 and then planarized to remain in the capacitor opening 190.

Dielectric layer 193 can include a single layer of material, multiple layers of material, laminated material, hybrid material, or combinations thereof. Dielectric layer 193 can comprise a high-k material. Dielectric layer 193 can have a specific silicon oxide (SiO)₂) High dielectric constant. The silicon oxide may have a dielectric constant of about 3.9, and the dielectric layer 193 may include a material having a dielectric constant of about 4 or more. The high-k material may have a dielectric constant of about 20 or greater. The high-k material may include hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Alumina (Al)₂O₃) Or of themAnd (4) combining. The dielectric layer 193 may be formed by Atomic Layer Deposition (ALD).

Dielectric layer 193 may be formed of a zirconium-based oxide. The dielectric layer 193 may have a thickness including zirconium oxide (ZrO)₂) The laminated structure of (1). Comprising zirconium oxide (ZrO)₂) May include ZA (ZrO)₂/Al₂O₃) Or ZAZ (ZrO)₂/Al₂O₃/ZrO₂). ZA may have alumina (Al) therein₂O₃) Laminated on zirconia (ZrO)₂) The above structure. ZAZ may have zirconium oxide (ZrO) therein₂) Alumina (Al)₂O₃) And zirconium oxide (ZrO)₂) A sequentially stacked structure. ZrO (ZrO)₂ZA and ZAZ may be referred to as zirconia-based layers. According to another embodiment of the present invention, the dielectric layer 193 may be formed of a hafnium-based oxide. Dielectric layer 193 may have a thickness including hafnium oxide (HfO)₂) The laminated structure of (1). Including hafnium oxide (HfO)₂) May comprise HA (HfO)₂/Al₂O₃) Or HAH (HfO)₂/Al₂O₃/HfO₂). HA may have alumina (Al) therein₂O₃) Laminated on hafnium oxide (HfO)₂) The above structure.

The HAH may have hafnium oxide (HfO) therein₂) Alumina (Al)₂O₃) And hafnium oxide (HfO)₂) A sequentially stacked structure. HfO₂HA and HAH may be referred to as hafnium oxide based layers. Of ZA, ZAZ, HA and HAH, alumina (Al)₂O₃) May have a specific zirconia (ZrO)₂) And hafnium oxide (HfO)₂) A large band gap. Alumina (Al)₂O₃) May be lower than that of zirconium oxide (ZrO)₂) And hafnium oxide (HfO)₂). Accordingly, dielectric layer 193 can include a stack of a high-k material and a high-bandgap material having a bandgap energy greater than that of the high-k material. Except for alumina (Al)₂O₃) In addition, dielectric layer 193 can include silicon oxide (SiO)₂) As another high bandgap material. The dielectric layer 193 may include a high bandgap material so that leakage current may be suppressed. The high band gap material canTo be very thin. The high bandgap material may be thinner than the high k material.

According to another embodiment of the present invention, the dielectric layer 193 may include a laminated structure (plated structure) in which a high-k material and a high band gap material are alternately laminated. For example ZAZAZA (ZrO)₂/Al₂O₃/ZrO₂/Al₂O₃)、ZAZAZ(ZrO₂/Al₂O₃/ZrO₂/Al₂O₃/ZrO₂)、HAHA(HfO₂/Al₂O₃/HfO₂/Al₂O₃) Or HAHAH (HfO)₂/Al₂O₃/HfO₂/Al₂O₃). In the above laminated structure, alumina (Al)₂O₃) Can be very thin.

According to another embodiment of the present invention, the dielectric layer 193 may include hafnium oxide having a tetragonal phase or zirconium oxide having a tetragonal phase.

According to another embodiment of the present invention, the dielectric layer 193 may have a stacked-layer structure including hafnium oxide having a tetragonal phase and zirconium oxide having a tetragonal phase.

The board node 194 may comprise a metal-based material. Plate node 194 may comprise a metal nitride. Plate node 194 may comprise a metal, metal nitride, metal carbide, conductive metal nitride, conductive metal oxide, or combinations thereof. The plate node 194 may be formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO)₂) Iridium oxide (IrO)₂) Or a combination thereof.

As a result of the above-described series of processes, the capacitor 195 may be formed, and the capacitor 195 may include the storage node 192, the dielectric layer 193, and the plate node 194. The dielectric layer 193 and the board node 194 may be vertically oriented with respect to the lower structure 120, and each storage node 192 may surround the dielectric layer 193 and the board node 194. The storage node 192 may have a transverse ring shape.

Fig. 27A and 27B illustrate a method for forming a stepped word line structure. The stepped word line structure may be stepped on two opposite ends of the word line.

Referring to fig. 27A, a stepped structure ST may be formed by selectively etching the first material layer 131 and the second material layer 132 of the upper structure 130. A process for forming the stepped structure ST may be referred to as a thinning process. The stepped structure ST may be formed simultaneously with the isolation opening 161 shown in fig. 13A to 13C.

Referring to fig. 16A to 16D, the second material layer 132 may be selectively removed to form a gate recess 171 between the first material layers 131.

Subsequently, as shown in fig. 27B, the gate recess 171 may be filled with the word line 173.

As described above, when the stepped structure ST is formed in the upper structure 130, at least one end of the word line 173 may be formed in the stepped structure ST.

Fig. 28 to 30 illustrate a method for manufacturing a memory device according to another embodiment of the present invention. A method of forming other constituent elements than the capacitor will refer to the method illustrated in fig. 3A to 22B.

First, referring to fig. 23A and 23B, a capacitor opening 190 may be formed.

Subsequently, as shown in fig. 28, the side of the active layer 151 exposed by the capacitor opening 190 may be selectively removed to form a storage node recess 191'. The storage node recesses 191' may be located between the first material layers 131.

Subsequently, the capacitor contact node 192C may be formed in the active layer 151 remaining due to the storage node recess 191'.

For example, referring to fig. 24A to 25B, a second contact pad layer 191 may be formed to cover the capacitor opening 190. The second contact pad layer 191 may contain impurities. The second contact pad layer 191 may include N-type polysilicon. Subsequently, the N-type impurity may be diffused from the second contact pad layer 191 by performing heat treatment. As a result, a portion of the active layer 151 in contact with the second contact pad layer 191 may be doped with N-type impurities. The portion of the active layer 151 doped with the N-type impurity may be the capacitor contact node 192C. From a top view perspective, the capacitor contact node 192C may laterally extend to be located between the first material layers 131 while covering sidewalls of the capacitor opening 190. As such, the capacitor contact node 192C may be the portion that: in which a portion of the active layer 151 is doped with N-type impurities. The capacitor contact nodes 192C may partially fill the storage nodes 191', respectively. According to another embodiment of the present invention, a metal silicide may be further formed on the capacitor contact node 192C. To form the metal silicide, a deposition process and an annealing process of titanium/titanium nitride may be performed, and unreacted titanium/titanium nitride may be removed.

Referring to fig. 29, a storage node 192 'may be formed in the storage node recess 191'. After depositing the conductive material to fill the storage node recesses 191', the conductive material may be selectively etched. For example, the storage nodes 192 'may be formed to be isolated from each other while filling the storage node recesses 191', by etching back the conductive material. The storage node 192' may include a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The storage node 192' may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), and ruthenium oxide (RuO)₂) Iridium oxide (IrO)₂) Or a combination thereof. The storage node 192' may have a transverse ring shape.

Referring to fig. 30, a dielectric layer 193 and a plate node 194 may be formed on the storage node 192' to fill the capacitor opening 190. The dielectric layer 193 and the plate node 194 will be described with reference to fig. 26A and 26B. The dielectric layer 193 may conformally cover the capacitor opening 190, and the plate node 194 may completely fill the capacitor opening 190 above the dielectric layer 193. The dielectric layer 193 and the plate node 194 may be formed by: a dielectric material and a plate node layer are stacked over the capacitor opening 190 and then planarized so that the dielectric material and the plate node layer can remain in the capacitor opening 190. The storage node 192' may surround the dielectric layer 193 and the plate node 194. The capacitor contact node 192C may surround the storage node 192'.

Fig. 31 is a sectional view showing a memory device according to another embodiment of the present invention. The memory device 200 of FIG. 31 may be similar to the memory device 100M of FIG. 1A.

Referring to fig. 31, the memory device 200 may include: a substrate SS; an active layer ACT spaced apart from the substrate SS and oriented laterally in a first direction D1; word lines WL laterally oriented parallel to the active layer ACT along one side of the active layer ACT; an active body ACB vertically oriented in a second direction D2 by penetrating the active layer ACT; a bit line BL vertically oriented in the second direction D2 by penetrating the active layer ACT while being spaced apart from one side of the active body ACB; and a capacitor CAP vertically oriented in the second direction D2 by penetrating the active layer ACT while being spaced apart from the other side of the active body ACB.

In the memory device 200 of fig. 31, the memory cell array MCA may be located under the substrate SS. The substrate SS may include a substrate structure including peripheral circuits, and the peripheral circuits may include at least one control circuit for controlling the memory cell array MCA. The bit lines BL, the active body ACB, and the capacitor CAP may extend vertically downward from the substrate SS. The active layer ACT and the word line WL may be located at the same distance and may be parallel to the plane of the substrate SS.

FIG. 32 illustrates a memory device according to another embodiment of the present invention. The memory device of fig. 32 may be similar to the memory device 100M of fig. 1A.

Referring to fig. 32, adjacent memory cells MCU and MCL may be symmetrical to each other in a third direction D3 with respect to a word line WL therebetween.

FIG. 33 illustrates a memory device according to another embodiment of the present invention. The memory device 400 of fig. 33 may be similar to the memory device 100M of fig. 1A.

Referring to fig. 33, adjacent memory cells MC1, MC2, and MC3 may share one word line WL. The word lines WL may extend in a first direction D1.

According to the embodiments of the present invention, by stacking memory cells in a three-dimensional structure in a vertical direction, it is possible to increase cell density and reduce parasitic capacitance.

According to the embodiments of the present invention, it is also possible to realize a highly integrated memory device in a limited area by laminating memory cells in the vertical direction with respect to the peripheral circuit portion.

Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A memory device, comprising:

a substrate;

an active layer spaced apart from and laterally oriented to the substrate;

word lines laterally oriented parallel to the active layer along one side of the active layer;

an active body vertically oriented by penetrating the active layer;

a bit line vertically oriented by penetrating the active layer to be spaced apart from one side of the active body; and

a capacitor vertically oriented through the active layer to be spaced apart from the other side of the active body.

2. The memory device of claim 1, wherein the active layer and the word line are located at a same distance from the substrate.

3. The memory device of claim 1, wherein the active layer comprises:

a first source/drain region coupled to the bit line;

a second source/drain region coupled to the capacitor; and

a channel body coupled to the active body and oriented laterally between the first and second source/drain regions.

4. The memory device of claim 3, wherein the channel body has a shape that surrounds the active body.

5. The memory device of claim 1, wherein the capacitor comprises:

a storage node laterally oriented parallel to the substrate;

a dielectric layer over the storage node; and

a plate node over the dielectric layer;

wherein the dielectric layer and the plate node are vertically oriented by penetrating the storage node.

6. The memory device of claim 5, wherein the storage node is located at the same distance from the active layer.

7. The memory device of claim 1, further comprising:

a bit line contact node formed in the active layer and surrounding the bit line.

8. The memory device of claim 1, wherein at least one end of the word line has a stepped portion.

9. A memory device, comprising:

storage units, which are arranged in a vertical direction,

wherein each of the memory cells includes:

an active layer comprising a first source/drain region, a second source/drain region, and a channel body laterally oriented between the first source/drain region and the second source/drain region;

word lines laterally oriented parallel to one side of the active layer;

an active body extending through the channel body;

a bit line vertically oriented through the active layer coupled with the first source/drain region; and

a capacitor vertically oriented through the active layer to couple with the second source/drain region.

10. The memory device of claim 9, wherein the word line is parallel to the first source/drain region, the second source/drain region, and the channel body.

11. The memory device of claim 9, further comprising:

a gate dielectric layer formed between one side of the channel body and the word line.

12. The memory device of claim 9, further comprising:

an isolation dielectric layer between the first and second source/drain regions and the word line, wherein the isolation dielectric layer is vertically oriented in a stacking direction of the memory cells.

13. The memory device of claim 9, further comprising:

a bit line contact node formed in the active layer and coupled to the first source/drain region and the bit line, wherein the bit line contact node surrounds the bit line.

14. The memory device of claim 9, wherein at least one end of the word line has a stepped portion.

15. The memory device of claim 9, wherein the capacitor comprises:

a storage node formed in the active layer and coupled to the second source/drain region;

a dielectric layer over the storage node; and

a plate node over the dielectric layer.

16. The memory device of claim 15, wherein the storage node is located at the same distance from the active layer.

17. The memory device of claim 15, wherein the dielectric layer and the plate node are vertically oriented through the active layer.

18. The memory device of claim 9, further comprising:

a dielectric material between the memory cells.

19. The memory device of claim 9, further comprising:

a peripheral circuit located below the memory cell.

20. The memory device of claim 9, further comprising:

peripheral circuitry located above the memory cells.

21. A method for fabricating a memory device, comprising:

forming a plurality of active layers arranged in a vertical direction with respect to a substrate;

forming a vertically oriented active body that interconnects the active layers to each other throughout the active layers;

forming a vertically oriented bit line spaced apart from one side of the active body and penetrating the active layer;

forming a vertically oriented capacitor spaced apart from the other side of the active body and penetrating the active layer; and

a plurality of word lines are formed that are laterally oriented adjacent to one side of each of the active layers.

22. The method of claim 21, wherein the forming a plurality of active layers arranged in a vertical direction with respect to a substrate comprises:

forming an alternating stack wherein the dielectric material is alternately stacked with the sacrificial material;

forming vertically oriented cell openings through the alternating stack;

forming a recess extending laterally from the cell opening by selectively recessing the sacrificial material through the cell opening; and

the active layers are formed, and they fill the recesses, respectively.

23. The method of claim 21, wherein each of the active layers comprises a plurality of fingers.

24. The method of claim 21, wherein the step of forming a vertically oriented active body interconnecting the active layers to each other throughout the active layers comprises:

replacing a portion of the sacrificial material with the active body; and

a vertically oriented active body is formed through the channel body.

25. The method of claim 24, wherein the step of forming a vertically oriented active body interconnecting the active layers to each other throughout the active layers comprises:

forming first cell openings that are vertically oriented by traversing the alternating stack;

forming a recess extending laterally from the first cell opening by selectively recessing the sacrificial material through the first cell opening;

filling the first cell opening from which the sacrificial material has been removed with a silicon material;

forming the active body doped with impurities while filling a first cell opening over the silicon material; and

diffusing the impurity from the active body to form the channel body.

26. The method of claim 21, wherein the step of forming a vertically oriented bit line spaced apart from a side of the active body and penetrating the active layer comprises:

an alternating stack formed over the substrate, wherein dielectric material is stacked alternately with sacrificial material;

replacing a portion of the sacrificial material with a bit line contact node; and

forming a conductive material through the bit line contact node to form the vertically oriented bit line.

27. The method of claim 26, wherein the step of forming a vertically oriented bit line spaced apart from a side of the active body and penetrating the active layer comprises:

forming second cell openings that are vertically oriented by traversing the alternating stack;

forming a recess extending laterally from the cell opening by selectively recessing the sacrificial material through the second cell opening;

filling the second cell opening from which the sacrificial material has been removed with the bit line contact node; and

forming a vertically oriented bit line that fills the second cell opening above the bit line contact node.

28. The method of claim 21, wherein the step of forming a vertically oriented capacitor spaced apart from the other side of the active body and extending through the active layer comprises:

replacing a portion of the sacrificial material with a storage node; and

forming a dielectric layer and a plate node, both vertically oriented to extend through the storage node.

29. The method of claim 28 wherein the step of forming a vertically oriented capacitor spaced from the other side of the active body and extending through the active layer comprises:

forming third cell openings that are vertically oriented by traversing the alternating stack;

forming a recess extending laterally from the third cell opening by selectively recessing the sacrificial material through the third cell opening;

filling the third cell opening from which the sacrificial material has been removed with a capacitor contact node; and

forming a storage node surrounded by the capacitor contact node over the capacitor contact node; and

forming the dielectric layer and the plate node filling the third cell opening over the storage node.

30. The method of claim 21, wherein, in the step of forming a plurality of active layers arranged in a vertical direction with respect to a substrate,

each of the active layers includes a first cell opening, a second cell opening, and a third cell opening, an

The first, second, and third cell openings are vertically oriented with respect to one another.

31. The method of claim 30, wherein the first cell opening is filled with the vertically oriented active body, and

filling the second cell opening with the vertically oriented bit line,

filling the third cell with the vertically oriented capacitor.

32. The method of claim 21, further comprising:

forming a first source/drain region in each of the active layers;

forming a second source/drain region in each of the active layers, laterally spaced from the first source/drain region; and

forming a channel body oriented laterally between the first and second source/drain regions.

33. The method of claim 32, wherein the steps of forming the first source/drain region and forming the second source/drain region comprise:

forming an opening exposing one side of each of the active layers; and

doping impurities on one side of each of the active layers through the openings.

34. The method of claim 32, wherein the step of forming a channel body oriented laterally between the first and second source/drain regions comprises:

forming openings that are vertically oriented by penetrating each of the active layers;

forming an active body doped with impurities, which fills the opening; and

diffusing the impurity from the impurity-doped active body to form the channel body.

35. The method of claim 21, wherein the step of forming a plurality of word lines oriented laterally adjacent to one side of each of the active layers comprises:

forming an opening vertically oriented parallel to one side of the active layer;

forming a gate recess extending laterally from the opening; and

filling the gate recess with a conductive material to form the word line.