CN113129985B - Physical unclonable unit and reading circuit - Google Patents
Physical unclonable unit and reading circuit Download PDFInfo
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- CN113129985B CN113129985B CN202110335319.XA CN202110335319A CN113129985B CN 113129985 B CN113129985 B CN 113129985B CN 202110335319 A CN202110335319 A CN 202110335319A CN 113129985 B CN113129985 B CN 113129985B
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- transistor antifuse
- transistor
- antifuse
- word line
- bit line
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- 238000010586 diagram Methods 0.000 description 6
- 230000005855 radiation Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000010076 replication Effects 0.000 description 2
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
The invention provides a physical unclonable unit and a reading circuit, wherein the physical unclonable unit comprises: the first transistor antifuse is connected with the first word line, the first bit line and the second transistor antifuse respectively, and the second transistor antifuse is also connected with the second word line and the second bit line respectively. The physical unclonable unit provided by the invention is not easy to cause device failure or data overturn in an irradiation environment, so that the safety of stored data is ensured.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a physical unclonable unit and a reading circuit.
Background
With the development of aerospace industry, communication safety among various satellites, spacecrafts and earth stations also needs to be concerned. The physical unclonable PUF (Physical Unclonable Functions) technology is to extract chip features to generate signature data with unique marks by utilizing the uncontrollable manufacturing process difference of an integrated circuit. The special lightweight and tamper-proof properties have great advantages in the hardware security fields of chip authentication, random number generator, key generation and the like, and the conventional PUF technology is based on SRAM and trigger structures. However, the radiation of the Galaxy rays and the radiation band in the space can change data of the SRAM and the trigger, and influence the safety protection capability of the system.
There is therefore a need for a PUF structure that is radiation-resistant and still works properly in an irradiation environment.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a physical unclonable unit and a reading circuit, which aim to solve the problem that the conventional PUF structure is easily influenced by cosmic rays and radiation.
In order to solve the technical problems, the invention adopts the following technical scheme:
In a first aspect, there is provided a physically unclonable unit comprising: the memory device comprises a first word line, a second word line, a first bit line, a second bit line, and a first transistor antifuse and a second transistor antifuse which are arranged in a mirror image mode, wherein the first transistor antifuse is respectively connected with the first word line, the first bit line and the second transistor antifuse, the second transistor antifuse is also respectively connected with the second word line and the second bit line, programming voltages are simultaneously applied to the first transistor antifuse through the first word line and the second transistor antifuse through the second word line, and a voltage difference formed by pulling down the voltages of the first bit line and the second bit line breaks down the first transistor antifuse or the second transistor antifuse so as to store data.
The first transistor antifuse comprises a first gate, a first source and a first drain, the second transistor antifuse comprises a second gate, a second source and a second drain, the first gate is connected with a first word line, the first source is connected with a first bit line, the first drain is connected with a second drain, the second source is connected with a second bit line, and the second gate is connected with a second word line.
The physical unclonable unit further comprises a first thick gate oxide layer and a first thin gate oxide layer which are arranged between the first grid electrode and the first source electrode as well as between the second grid electrode and the second drain electrode, and a second thick gate oxide layer and a second thin gate oxide layer which are arranged between the second grid electrode and the second source electrode as well as between the second grid electrode and the second drain electrode.
In a second aspect, the present invention also provides a read circuit comprising a current comparison circuit, an arbiter, and a physically unclonable cell as described in the first aspect; the first end of the current comparison circuit is connected with a junction between the first transistor antifuse and the second transistor antifuse, and the second end of the current comparison circuit is connected with an arbiter and outputs read data from the arbiter.
The current comparison circuit comprises three parallel current comparators.
The invention has the beneficial effects that:
According to the invention, the first word line and the second word line are used for applying programming voltage and breaking down the first transistor antifuse or the second transistor antifuse to randomly generate data, the first transistor antifuse and the second transistor antifuse have higher single event resistance, the range of changing the resistance values of the first transistor antifuse and the second transistor antifuse can not influence the judgment of stored data even in the environment of higher irradiation dose, and the safety of the data is ensured.
Drawings
The following details the specific construction of the present invention with reference to the accompanying drawings
FIG. 1 is a schematic diagram of a physical unclonable element according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a first transistor antifuse and a second transistor antifuse according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a read circuit according to an embodiment of the invention.
Detailed Description
In order to describe the technical content, the constructional features, the achieved objects and effects of the present invention in detail, the following description is made in connection with the embodiments and the accompanying drawings.
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a physical unclonable unit according to an embodiment of the present invention. As shown in fig. 1, a physically unclonable unit, comprising: the first and second transistor antifuses 100 and 400 are arranged in a mirror image, the first and second transistor antifuses 100 and 400 are respectively connected with the first and second word lines 200 and 500 and the second transistor antifuses 400 and 400 are respectively connected with the second and third word lines 500 and 600, and simultaneously a programming voltage is applied to the first and second transistor antifuses 100 and 400 through the first and second word lines 200 and 500, and a voltage difference is formed by pulling down the voltages of the first and second bit lines 300 and 600, so that the first and second transistor antifuses 100 and 400 are partially broken down for data storage.
The invention has the beneficial effects that:
According to the invention, the first word line 200 and the second word line 500 are used for applying programming voltage and breaking down the first transistor antifuse 100 or the second transistor antifuse 400 to randomly generate data, the first transistor antifuse 100 and the second transistor antifuse 400 have higher single event resistance, the determination of stored data is not affected even in the environment of higher irradiation dose, and the safety of the data is ensured.
Specifically, when the irradiation dose is 300Krad (si) or less, the determination of the stored data "0" or "1" is not affected.
Further, referring to fig. 2, fig. 2 is a schematic structural diagram of a first transistor antifuse and a second transistor antifuse according to an embodiment of the present invention. The first transistor antifuse 100 includes a first gate 110, a first source 120, and a first drain 130, the second transistor antifuse 400 includes a second gate 410, a second source 420, and a second drain 430, the first gate 110 is connected to the first word line 200, the first source 120 is connected to the first bit line 300, the first drain 130 is connected to the second drain 430, the second source 420 is connected to the second bit line 120, and the second gate 410 is connected to the second word line 500.
Optionally, the first drain 130 is connected to the first bit line 300, the first source 120 is connected to the second source 420, and the second drain 430 is connected to the second bit line 600.
Further, the physical unclonable cell further includes a first thick gate oxide 140 and a first thin gate oxide 150 disposed between the first gate 110 and the first source 120, and the first drain 130, and a second thick gate oxide 440 and a second thin gate oxide 450 disposed between the second gate 410 and the second source 420, and the second drain 430.
In this embodiment, the first thick gate oxide 140 is connected to the first source 120, the first thin gate oxide 150 is connected to the first drain 130, the second drain 430 is connected to the second thin gate oxide 450, and the second source 420 is connected to the second thick gate oxide 440.
It should be noted that, in the above embodiment, it is only necessary to ensure that the first transistor antifuse 100 is arranged in mirror image with the second transistor antifuse 400, and the positions of the source and the drain are not limited in the present invention.
The working principle of the invention is as follows:
When the first and second word lines 200 and 500 simultaneously apply the program voltage, the voltages of the first and second bit lines 300 and 600 are pulled down, respectively, a voltage difference is formed between the inside of the first and second transistor antifuses 100 and 400, and the first and second transistor antifuses 100 and 400 start programming at the same time, but due to the difference of the manufacturing process, the time when the first and second thin gate oxide layers 150 and 450 are broken down is different. Assuming that the first thin gate oxide 150 is broken down first, a path is formed between the first gate 110 and the first drain 130, the voltage difference between the second gate 410 and the second drain 430 becomes smaller, and the second thin gate oxide 450 is not broken down; conversely, if the second thin gate oxide 450 is broken down first, the first thin gate oxide 150 is not broken down similarly. For a single physically unclonable cell, by determining that the first thin gate oxide layer 150 or the second thin gate oxide layer 450 is broken down, the data "1" or the data "0" may be stored, which is not limited, only by ensuring that the data stored in the first thin gate oxide layer 150 and the second thin gate oxide layer 450 are different. A key consisting of multi-bit binary data may be randomly generated when there are multiple physically unclonable cells.
Referring to fig. 3, fig. 3 is a schematic diagram of a read circuit according to an embodiment of the invention. In one embodiment, the present invention also provides a reading circuit comprising a current comparing circuit 20, an arbiter 30, and a physically unclonable cell 10 as described in the above embodiments; a first terminal of the current comparison circuit 20 is connected to a junction between the first transistor antifuse 100 and the second transistor antifuse 400, and a second terminal of the current comparison circuit 20 is connected to the arbiter 30 and read data is output from the arbiter 30.
When the stored data is read, a read voltage is applied to the first transistor antifuse 100 through the first word line 200, and if the first thin gate oxide layer 150 is broken down, a large current flows into the current comparing circuit 20, and the current comparing circuit 20 outputs a high level; if the first thin gate oxide 150 is not broken down, the current comparing circuit 20 outputs a low level.
Further, the current comparison circuit 20 includes three parallel current comparators 210.
Further, the read circuit includes a plurality of physically unclonable units 10, each physically unclonable unit 10 further has two identical replication units, when one of the three physically unclonable units 10 and two replication units thereof fails or data flip occurs, the arbiter 30 outputs data stored in the other two units, that is, outputs data stored in most of the three units as a correct result, for example, "1" is stored in one unit, and "0" is stored in the other two units, and outputs "0" as a correct result, thereby ensuring accuracy of stored data.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (2)
1. A read circuit comprising a current comparison circuit, an arbiter, and a plurality of physically unclonable cells;
The physically unclonable unit comprises: the memory device comprises a first word line, a second word line, a first bit line, a second bit line, and a first transistor antifuse and a second transistor antifuse which are arranged in a mirror image mode, wherein a first grid electrode of the first transistor antifuse is connected with the first word line, a first source electrode of the first transistor antifuse is connected with the first bit line, a first drain electrode of the first transistor antifuse is connected with a second drain electrode of the second transistor antifuse, a second grid electrode of the second transistor antifuse is connected with the second word line, a second source electrode of the second transistor antifuse is connected with the second bit line, a programming voltage is applied to the first transistor antifuse through the first word line and the second transistor antifuse through the second word line, a voltage difference is formed by pulling down the voltages of the first bit line and the second bit line, and the first transistor antifuse or the second transistor antifuse is broken down in part so that data can be stored;
The first end of the current comparison circuit is connected with a node between the first transistor antifuse and the second transistor antifuse, the second end of the current comparison circuit is connected with an arbiter, the arbiter is used for outputting data stored in a plurality of physical unclonable units, when the reading circuit reads the data, a reading voltage is applied to the first transistor antifuse through a first word line, and if a first thin gate oxide layer is broken down, the current comparison circuit outputs a high level.
2. The read circuit of claim 1, wherein the current comparison circuit comprises three parallel current comparators.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110335319.XA CN113129985B (en) | 2021-03-29 | 2021-03-29 | Physical unclonable unit and reading circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110335319.XA CN113129985B (en) | 2021-03-29 | 2021-03-29 | Physical unclonable unit and reading circuit |
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| Publication Number | Publication Date |
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| CN113129985A CN113129985A (en) | 2021-07-16 |
| CN113129985B true CN113129985B (en) | 2024-05-03 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9613714B1 (en) * | 2016-01-19 | 2017-04-04 | Ememory Technology Inc. | One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method |
| CN107078162A (en) * | 2015-02-19 | 2017-08-18 | 国际商业机器公司 | Piece semiconductor device with enhanced changeability |
| CN107944301A (en) * | 2016-10-12 | 2018-04-20 | 力旺电子股份有限公司 | Antifuse physics can not duplicate circuit and corresponding control methods |
| CN108701486A (en) * | 2016-01-08 | 2018-10-23 | 美商新思科技有限公司 | It is generated using the PUF values of antifuse memory array |
| EP3506548A1 (en) * | 2017-12-27 | 2019-07-03 | Secure-IC SAS | Quantitative digital sensor |
| CN111201533A (en) * | 2018-08-10 | 2020-05-26 | 深圳市为通博科技有限责任公司 | Physically unclonable function PUF device |
-
2021
- 2021-03-29 CN CN202110335319.XA patent/CN113129985B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107078162A (en) * | 2015-02-19 | 2017-08-18 | 国际商业机器公司 | Piece semiconductor device with enhanced changeability |
| CN108701486A (en) * | 2016-01-08 | 2018-10-23 | 美商新思科技有限公司 | It is generated using the PUF values of antifuse memory array |
| US9613714B1 (en) * | 2016-01-19 | 2017-04-04 | Ememory Technology Inc. | One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method |
| CN107944301A (en) * | 2016-10-12 | 2018-04-20 | 力旺电子股份有限公司 | Antifuse physics can not duplicate circuit and corresponding control methods |
| EP3506548A1 (en) * | 2017-12-27 | 2019-07-03 | Secure-IC SAS | Quantitative digital sensor |
| CN111201533A (en) * | 2018-08-10 | 2020-05-26 | 深圳市为通博科技有限责任公司 | Physically unclonable function PUF device |
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| CN113129985A (en) | 2021-07-16 |
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