CN113129967A - Memristor, Hamming distance calculation method and storage and calculation integrated application - Google Patents
Memristor, Hamming distance calculation method and storage and calculation integrated application Download PDFInfo
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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Abstract
The invention provides a memristor, which comprises a transistor and a resistive random access memory, wherein the drain electrode of the transistor is connected with the bottom electrode of the resistive random access memory; the resistive random access memory includes: the current limiting layer stabilizes the volatility of low resistance by reducing surge current and optimizing heat distribution, so that the Hamming distance calculation accuracy is improved.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a memristor, a Hamming distance calculation method and storage-calculation integrated application.
Background
The Hamming weight is defined as the number of non-zero characters in a binary character string, the Hamming distance is defined as the number of different characters at corresponding positions between two binary character strings with equal length, and the method has wide application in the fields of image identification, information coding and information security encryption. In the information era of increasing data processing demands and increasing processing speed requirements, the conventional von neumann architecture computing system is increasingly subject to the problem of memory wall caused by the speed difference between the memory and the processor, and further improvement of the data processing speed and the bandwidth is limited. And the storage and calculation integrated architecture based on the nonvolatile memory design is beneficial to breaking through the limitation of a memory wall and improving the information processing capability.
The conventional resistive random access memory has the characteristics of high speed, non-volatility, simple device structure, micro-scalability, three-dimensional integration potential, low power consumption and the like, and has a wide prospect in the application aspects of integration of a novel memory and storage and calculation and the like. With the increase of the edge calculation requirement, the small-size, fast and low-power-consumption resistive random access memory device has a greater potential compared with the conventional static random access memory and the flash memory. However, in the past research, the speed and the power consumption performance of the memristor based on the resistive random access memory still need to be greatly improved, and the combination with the practical application needs to be further improved.
The prior art discloses a device for calculating a hamming distance, which may include a plurality of unipolar memristors, a row input and a column input, a first character string and a second character string are respectively used as the row input and the column input, different voltages are used to calculate the hamming distance, and a hamming distance value is read through current accumulation.
Aiming at the technical scheme in the prior art, the defects are as follows:
(1) the unipolar memristor adopted by the invention has poor durability (10 to 10)3Sub-erase and slow operation speed (>100 ns);
(2) for the calculated character string I and the character string II, the amplitude of the applied voltage of the input row and the input column is different, so that the complexity of the design of a peripheral circuit and the performance requirement of a switching device are increased;
(3) the units calculated by the scheme only use the units positioned on the diagonal line of the array, and the devices at the rest positions of the array are in an uninitialized activated state and cannot be used, so that the flexibility and the utilization rate of the array are reduced.
Disclosure of Invention
In view of the above, the present invention is directed to a memristor, a hamming distance calculation method and a memory-integrated application, so as to partially solve at least one of the above technical problems.
In order to achieve the above object, as an aspect of the present invention, a memristor is provided, including a transistor and a resistive random access memory, a drain of the transistor is connected to a bottom electrode of the resistive random access memory; the resistive random access memory includes: the current limiting layer stabilizes the volatility of low resistance by reducing surge current and optimizing heat distribution, so that the Hamming distance calculation accuracy is improved.
The top electrode and the bottom electrode are made of any alloy of one or more metals of TiN, Ti, Pt, Ag, Au, Pd, Ru and W, and the resistance change material layer is made of HfOX、TaOx、TiOx、ZrO2、Al2O3、NiO、ZnO、Ta2O5One of the above; the current confinement layer is made of SiOx、Al2O3、TiOx、TaOx、Ta2O5Is one of the above constitutions.
Wherein the memristor further comprises:
word lines, bit lines, and source lines; the word line is connected with the grid electrode of the transistor and controls the transistor to be switched on and off, and the bit line and the source line are respectively connected with the top electrode of the resistive random access memory and the source electrode of the transistor so as to control writing, operation and reading of the memory unit.
When the transistor is started, the bit line is grounded, and the source voltage is greater than the threshold voltage of the erasing current, injecting pulse current from the bottom electrode to realize the switching of the resistive random access memory from low resistance to high resistance; and conversely, when the source line is grounded and the bit line voltage meets the threshold voltage of the programming current, injecting pulse current from the top electrode to realize the switching of the resistive random access memory from high resistance to low resistance.
And applying a gate voltage to turn on the transistor, applying an initialization activation voltage to the top electrode, and setting the resistive random access memory in a programmable/erasable state.
As another aspect of the present invention, there is provided a hamming distance calculation method using the above memristor, including the steps of:
initializing the memristor to a high resistance state by an erase operation;
encoding a first binary string in the bit line, encoding a second binary string in the source line;
encoding the first binary string in the source line, encoding the second binary string in the bit line.
Wherein the step of encoding a first binary string in the bit line and a second binary string in the source line, a "0" representing ground and a "1" representing a high level pulse; and the transistor is turned on, the bit line is set at a high level, only the first binary character string is set to be 1, and the resistance state of the resistive random access memory is changed by the signal of the second binary character string to be 0, so that the corresponding bit 'inclusive non' Boolean logic operation between the first binary character string and the second binary character string with equal length is realized.
Wherein the step of encoding a first binary string in the source line and a second binary string in the bit line, a "0" representing ground and a "1" representing a high level pulse; and the transistor is turned on, the bit line is set at a high level, only the first binary character string is 0, and the resistance state of the resistive random access memory is changed by a signal of the second binary character string being 1, so that the operation of 'containing not' Boolean logic operation of the corresponding bit between the second binary character string with the same length and the first binary character string is realized, and the operation of the Hamming distance between the first binary character string and the second binary character string is realized.
The memristor is a storage array, and Hamming distance calculation operation is carried out on the N-bit string by using the storage unit of the column in the storage array; wherein the magnitude of N depends on the device switching ratio and the device resistance fluctuation.
As another aspect of the present invention, a computing-integrated application based on the hamming distance calculation method is provided, which further includes turning on transistor reading; the method specifically comprises the following steps:
when reading, 0.2V reading voltage exists between a source line and a reading bit line, and the reading bit line controls the transistor to be opened to generate reading current; the hamming distance is read from the total current according to kirchhoff's law.
Based on the technical scheme, compared with the prior art, the memristor, the Hamming distance calculation method and the memory calculation integrated application have at least one or part of the following beneficial effects:
(1) the memristor provided by the invention can realize resistance state inversion by using pulse voltage of 20ns, has nanosecond writing speed, can be used for realizing a fast and low-write delay memory-computation integrated array based on a unique circuit design, and has ultralow energy consumption (about 0.224 pJ);
(2) the current limiting layer is added in the memristor device, the effect is to stabilize the state after set, the fluctuation of high and low resistance states is reduced, and the reliability of Hamming distance calculation is improved;
(3) the memristor array provided by the invention can realize Hamming distance calculation and result storage of character strings in 3 operation cycles by utilizing voltage control;
(4) the invention discloses a structure of a memristor array and an operation method of a reconfigurable logic integrating read-write operation and memory operation, and the memristor array is simple in structure, compatible in a material system and a CMOS (complementary metal oxide semiconductor) process and beneficial to large-scale preparation and integration.
(5) The method improves the mode of calculating the Hamming distance by using the array diagonal device in the prior work, and improves the flexibility of the memristor memory-calculation integrated array. Compared with the traditional computing architecture and other memristor schemes, the method can realize high-speed Hamming distance computation and result storage under smaller area overhead.
Drawings
Fig. 1 is a schematic structural diagram of 1T1R (one-transporter-one-RR AM) based on an RRAM according to an embodiment of the present invention;
FIG. 2 shows the DC scanning I-V characteristics of the 1T1R structure provided by the embodiment of the present invention;
FIG. 3 shows the result of a 1T1R structure pulse erase/write operation according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of NIMP logic operation based on 1T1R structure according to an embodiment of the present invention;
FIG. 5 illustrates a step of calculating the 1-bit Hamming distance according to an embodiment of the present invention;
FIG. 6 is a read result of the 1-bit Hamming distance calculation provided by the embodiment of the present invention;
FIG. 7 shows the calculation of the N-bit Hamming distance in the 1T1R array structure according to an embodiment of the present invention.
Detailed Description
The invention provides an RRAM unit capable of realizing stable writing and erasing under the control of bipolar pulse voltage and application of an integrated device array thereof.
The invention provides a high-speed ultralow-energy-consumption storage and calculation integrated memristor structure, and the device architecture has the Hamming distance calculation application of realizing exclusive OR (XOR) operation and an integrated array thereof.
The basic unit of the device consists of one transistor and one RRAM (1T 1R). compared with the traditional three-layer RRAM structure, the invention has the advantages that the top electrode and HfO are arrangedxInserting TaO betweenxTherefore, the stability of the device is improved, and the reliability of Hamming distance calculation is improved. And simultaneously, through the design of reading and writing and logic operation circuits, the Hamming weight and Hamming distance of two equal-length binary character strings are calculated integrally by using the RRAM array.
First, TaOxThe layer provides excellent resistance uniformity for the high and low resistance states. This is due to TaOxThe layer acts as a current-confining layer,the transistor is beneficial to reducing surge current brought by rapid pulse switching during the forming and programming operation, and the device has the characteristics of rapidness and low power consumption while the stability of the device is improved.
Secondly, a 1T1R structure and a read-write circuit are constructed by using the resistive random access memory, and controllable devices in the array are read and written in parallel. The binary information of the character string I (A) and the character string II (B) is respectively applied by voltage signals of a word line and a source line, and the application positions of the two signals are exchanged in the next operation, so that the calculation of the Hamming distance between the two character strings is realized, and the storage result is stored in the RRAM.
Finally, a read voltage is applied across the operated memory cell to generate a total read current, and the specific value of the Hamming distance is read by the peripheral circuitry.
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
As shown in fig. 1, it is a schematic structural diagram of 1T1R based on RRAM; the memristor consists of an RRAM and a transistor 105, wherein the basic structure of the RRAM comprises a top electrode 101, a current limiting layer 102, a resistance change material layer 103 and a bottom electrode 104, wherein the top electrode and the bottom electrode are made of one of TiN, Ti, Pt, Ag, Au, Pd, Ru, W and other metals or alloys, and the resistance change material layer is made of HfOX、TaOx、TiOx、ZrO2、Al2O3、NiO、ZnO、Ta2O5One of them. The current confinement layer is made of SiOx、Al2O3、TiOx、TaOx、Ta2O5One of the components acts to stabilize the state after set, reducing fluctuation of the low resistance state, and increasing reliability of the hamming distance calculation result. In the array structure, a word line is connected with a gate of a transistor to control the on and off of the transistor, and a bit line and a source line are respectively connected with a top electrode of the resistive random access memory and a source electrode of the transistor to further control the writing, operation and reading of a memory cell.
When the transistor is started, the bit line is grounded and the source voltage is greater than the threshold voltage of the erasing current, injecting pulse current from the bottom electrode to realize the switching of the resistive random access memory from low resistance to high resistance; on the contrary, when the source line is grounded and the bit line voltage meets the threshold voltage of the programming current, the injection pulse current is injected from the top electrode, so that the resistive random access memory is switched from high resistance to low resistance.
For the manufactured device, a gate voltage is applied to turn on the transistor, and a forming voltage (3-4V) is applied to the top electrode, so that the resistive random access memory is set to be in a programmable/erasable state.
As shown in fig. 2, the structure is 1T1R and the I-V characteristic is scanned by direct current; the device has bipolar switching characteristics, when a word line is arranged at a high level, a transistor is started, if V is greater than 0, a top electrode is arranged at the high level, a source line is grounded, a conductive filament is generated in a resistance change material layer, and an RRAM is in a low-resistance state and can be represented by binary information '1'; if the top electrode V <0 is grounded, and the source line is at a high level, the conductive filament of the resistive switching material layer is broken, and at this time, the RRAM is in a high-resistance state, which can be represented by binary information "0".
In the reading process, the word line is set at a high level, the transistor is turned on, the top electrode applies a reading voltage difference of 0.2V, and different current values are respectively generated according to the high resistance state and the low resistance state according to kirchhoff law and the difference of resistance states stored in the RRAM.
FIG. 3 shows the result of the pulse erase/write operation of the 1T1R structure; in practical applications, the resistive state of the RRAM can be changed by pulse programming/erasing. In the erase operation shown in FIG. 3(a), a voltage pulse of 20ns is applied to the source at 12 μ s. And applying a reading voltage of 0.2V before and after applying the pulse to read the resistance state of the device. From the results, it can be seen that the read current was measured to be about 4 μ A before the pulse was applied, and about 0.2 μ A after the current was applied, confirming that the 20ns voltage pulse erase operation switched the device from the low resistance to the high resistance state. In the programming operation shown in FIG. 3(b), a voltage pulse of 20ns is applied to the top electrode at 12 μ s. The device resistance was also read by applying a read voltage of 0.2V before and after the pulse application. From the results, it can be seen that the read current measured before the pulse was applied was about 0.2 μ A, while the read current after the current was applied was about 5.5 μ A, confirming that a voltage pulse programming operation of 20ns switched the device from a high resistance to a low resistance state. The above parameters are not particularly limited, and may be varied depending on the material system and the conditions such as physical dimensions.
As shown in fig. 4, a schematic diagram of "NIMP" boolean logic operation between the source voltage signal and the gate voltage signal is implemented. Based on the operations described in fig. 3, different boolean logic operations can be constructed by applying voltages to different ports of the 1T1R device, which becomes the basis for implementing hamming distance calculation and other integrated storage functions. In the operation method of the present invention, for two binary strings a and B, we use "NIMP" logic to implement hamming distance calculation for both.
When the "NIMP" logic is used, first, the RRAM needs to be initialized to the high-resistance state by using the erase operation described in fig. 3(a), which represents the binary information "0". During logic operation, the bit line to which the top electrode is connected is placed in a high state (HVS) during an operation period, and the source line voltage Vs and the gate voltage Vg are used as input values to be calculated. Wherein the low level represents "0" and the high level represents "1". When Vg is 0, or Vg is 0 and Vs is 1, the transistor is turned off, and the RRAM resistance state keeps the original high resistance state unchanged; when Vg is equal to 1 and Vs is equal to 0, the transistor is turned on, and a voltage drop exists between the bit line and the source line, that is, a programming operation is performed, and the resistance is converted from an initial high-resistance state to a low-resistance state, which represents binary information "1". When Vg is equal to 1, the transistor is turned on, but there is no voltage difference between the bit line and the source line, and thus the RRAM still maintains the initial high resistance state. Thereby realizing the operation of binary information 'Vg NIMP Vs'.
The invention also provides a Hamming distance calculation method by utilizing the memristor, which comprises the following steps:
initializing the memristor to a high resistance state by an erase operation;
encoding a first binary string (A) in the bit line, encoding a second binary string (B) in the source line;
encoding the first binary string (A) in the source line and the second binary string (B) in the bit line.
As shown in FIG. 5, a scheme for implementing Hamming distance calculation for 1-bit binary numbers A and B is provided. First, the device is initialized to the high resistance state by an erase operation, as shown in fig. 5(a), in the same manner as the initialization step described above. Next, as shown in fig. 5(B), a is encoded into the word line as Vg, and B is encoded into the source line Vs, and the operation of "a NIMP B" is completed by the steps described in fig. 4. Then, B is encoded into the word line as Vg, and a is encoded into the source line Vs, thereby realizing the operation of "B NIMP a". And comprehensively realizing the operation of the A XOR B. The calculation result of the Hamming distance is stored in the RRAM, namely, when the character A is different from the character B, the device is programmed to be in a low resistance state, and the Hamming distance is 1; on the contrary, when the two values are the same, the device keeps the original high resistance state, and the Hamming distance is 0.
The invention also provides an integrated application of the memory and calculation integration based on the Hamming distance calculation method, which also comprises the steps of starting transistor reading relative to the Hamming distance calculation method; the method specifically comprises the following steps:
when reading, 0.2V reading voltage exists between a source line and a reading bit line, and the reading bit line controls the transistor to be opened to generate reading current; the hamming distance is read from the total current according to kirchhoff's law.
When the Hamming distance result is read, the source line is set at a high level and the bit line is set at a low level, and a read voltage is applied to generate a voltage drop between the bit line and the source line, so that the resistance state stored in the RRAM can be read according to the read current flowing through the RRAM. As shown in FIG. 6, I1、I2The RRAM reading circuit respectively corresponds to the reading currents of a single RRAM in a low resistance state and a high resistance state, and the distribution of the RRAM and the low resistance state and the high resistance state is not overlapped, so that the RRAM reading circuit can read and distinguish the RRAM and the RRAM through a peripheral amplifying circuit, and the Hamming distance operation result stored in the RRAM is read.
FIG. 7 is a method for implementing N-bit Hamming distance calculation by expanding the device into a two-dimensional array structure. First, as shown in fig. 7(a), initialization is required before writing and calculating the memory cell, the procedure is the same as the initialization method described above, and the initialization can be performed in parallel for N RRAMs in the same column. In subsequent operation of the scheme, the bit line of the column in which the desired computational cell is located is applied high, while the bit lines of the remaining columns of the array are left floating. The character string a is written and calculated as a word line signal by controlling the gate voltage of the transistor, and the character string B is a source line voltage signal, as shown in fig. 7 (B). When the character is "0", it is at low level, and when the character is "1", it is at high level. In this operation, each single 1T1R structure follows the operation method and programming rule of the calculation of the hamming distance of the 1-bit information described in fig. 5, and realizes the logical operation of "a NIMP B", that is, the equal-length character string a is 001 … 1 and the equal-length character string B is 010 … 1, and after the NIMP operation, the state of the RRAM is "001 … 1".
The second calculation cycle, B as the gating voltage and A as the wordline signal, writes the information into the RRAM array as shown in FIG. 7(c), and the switching rule is the same as the operation described in FIG. 5, and the operation of "B NIMP A" is performed in the RRAM, except that "B NIMP A" is performedi＝1，AiThe memory cell of 0 is programmed to a low resistance state "1", and the remaining resistance states keep the result in the first calculation cycle unchanged. After the second computing period is finished, the storage information in the RRAM is 011 … 0', so that after the second computing period is finished, the RRAM array realizes the XOR operation of the characters corresponding to the N-Bit character strings A and B. The number of stored "1" is the hamming distance of two strings. The calculation result of the adjacent Hamming distance is the difference value (low resistance current-high resistance current) of the corresponding currents of the high and low resistance states of a single device unit (50 uA). The number of bits of N is determined by the device switching ratio.
In reading, the source line of the column where the calculation is performed is set to low level and the bit line is set to high level, the transistor is turned on, and when a reading voltage is applied to the source line, a voltage drop is generated between the reading bit line and the source line, and the number of low resistance states stored in the RRAM can be reflected according to the total current flowing through the RRAM (as shown by an arrow in fig. 7 (d)), so that the hamming distance is obtained.
This scheme uses a certain column of the RRAM array for computation, while the rest of the array is floated, without performing additional operations. Compared with the method of operating by using the unit where the diagonal line is located in the prior art, the utilization rate of the array is increased while character strings are written in parallel.
Furthermore, the above definitions of the various elements and methods are not limited to the particular structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by one of ordinary skill in the art, for example:
(1) the shape of the storage unit can be simply replaced by a cuboid, a ring and the like;
(2) the numerical values set forth herein may vary from process to process.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A memristor is characterized by comprising a transistor and a resistive random access memory, wherein the drain electrode of the transistor is connected with the bottom electrode of the resistive random access memory; the resistive random access memory includes: the current limiting layer stabilizes the volatility of low resistance by reducing surge current and optimizing heat distribution, so that the Hamming distance calculation accuracy is improved.
2. The memristor according to claim 1, wherein the top and bottom electrodes are composed of any alloy of one or more metals of TiN, Ti, Pt, Ag, Au, Pd, Ru, W, and the resistive switching material layer is made of HfOX、TaOx、TiOx、ZrO2、Al2O3、NiO、ZnO、Ta2O5One of the above; the current confinement layer is made of SiOx、Al2O3、TiOx、TaOx、Ta2O5Is one of the above constitutions.
3. The memristor of claim 1, further comprising:
word lines, bit lines, and source lines; the word line is connected with the grid electrode of the transistor and controls the transistor to be switched on and off, and the bit line and the source line are respectively connected with the top electrode of the resistive random access memory and the source electrode of the transistor so as to control writing, operation and reading of the memory unit.
4. The memristor according to claim 3, wherein when the transistor is turned on, the bit line is grounded, and the source voltage is greater than the threshold voltage of the erase current, an injection pulse current is injected from the bottom electrode, so that the switching of the resistive random access memory from low resistance to high resistance is realized; and conversely, when the source line is grounded and the bit line voltage meets the threshold voltage of the programming current, injecting pulse current from the top electrode to realize the switching of the resistive random access memory from high resistance to low resistance.
5. The memristor according to claim 1, wherein a gate voltage is applied to turn on the transistor and an initialization activation voltage is applied to the top electrode to place the resistive random access memory in a programmable/erased state.
6. A hamming distance calculation method using the memristor of any of claims 1-5, comprising the steps of:
initializing the memristor to a high resistance state by an erase operation;
encoding a first binary string in the bit line, encoding a second binary string in the source line;
encoding the first binary string in the source line, encoding the second binary string in the bit line.
7. The hamming distance calculating method of claim 6 wherein said steps of encoding a first binary string in said bit line and a second binary string in said source line, information "0" representing ground, "1" representing a high level pulse; and the transistor is turned on, the bit line is set at a high level, only the first binary character string is set to be 1, and the resistance state of the resistive random access memory is changed by the signal of the second binary character string to be 0, so that the corresponding bit 'inclusive non' Boolean logic operation between the first binary character string and the second binary character string with equal length is realized.
8. The hamming distance calculating method of claim 6 wherein said steps of encoding a first binary string in said source line and a second binary string in said bit line, information "0" for ground, "1" for a high level pulse; and the transistor is turned on, the bit line is set at a high level, only the first binary character string is 0, and the resistance state of the resistive random access memory is changed by a signal of the second binary character string being 1, so that the operation of 'containing not' Boolean logic operation of the corresponding bit between the second binary character string with the same length and the first binary character string is realized, and the operation of the Hamming distance between the first binary character string and the second binary character string is realized.
9. The Hamming distance calculation method of claim 6, wherein the memristor is a memory array, and the Hamming distance calculation operation is performed on an N-bit string by using the memory cells in the column of the memory array; wherein the magnitude of N depends on the device switching ratio and the device resistance fluctuation.
10. An integrated application of the hamming distance calculation method of any one of claims 6-9 in a computer, further comprising turning on transistor reading; the method specifically comprises the following steps:
when reading, 0.2V reading voltage exists between a source line and a reading bit line, and the reading bit line controls the transistor to be opened to generate reading current; the hamming distance is read from the total current according to kirchhoff's law.
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| CN102104110A (en) * | 2010-11-16 | 2011-06-22 | 复旦大学 | Resistance change memory with optimized resistance change characteristic and preparation method thereof |
| US20160093802A1 (en) * | 2014-09-26 | 2016-03-31 | Winbond Electronics Corp. | Self-rectifying resistive random access memory cell structure |
| US20160225824A1 (en) * | 2015-02-03 | 2016-08-04 | Crossbar, Inc. | Resistive memory cell with intrinsic current control |
| CN111968689A (en) * | 2020-08-27 | 2020-11-20 | 清华大学 | Signal processing device and signal processing method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116048479A (en) * | 2023-04-03 | 2023-05-02 | 南京大学 | Quick programming method for memory and calculation integrated chip |
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