CN113127287A - Processor control method and device and electronic equipment - Google Patents
Processor control method and device and electronic equipment Download PDFInfo
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- CN113127287A CN113127287A CN201911405007.0A CN201911405007A CN113127287A CN 113127287 A CN113127287 A CN 113127287A CN 201911405007 A CN201911405007 A CN 201911405007A CN 113127287 A CN113127287 A CN 113127287A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
Abstract
The invention provides a processor control method and device and electronic equipment. A method of controlling a processor, comprising the steps of: monitoring a response signal aiming at a control instruction after the processor sends the control instruction; and if the answer signal is not monitored within the preset time length, finishing monitoring the answer signal. In this way, in the embodiment of the present invention, by monitoring the response signal for the control instruction sent by the processor within the preset time period, if the module targeted by the control instruction fails to return the response signal in response to the control instruction even though the module targeted by the control instruction fails, the processor may also end monitoring the response signal after the preset time period, thereby avoiding continuously monitoring the response signal and increasing the load of the processor.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method and an apparatus for controlling a processor, and an electronic device.
Background
As shown in fig. 1, an MCU (micro controller Unit) 100 is an indispensable important device in embedded system applications in various fields. The MCU100 internally includes a processor 101 and a plurality of on-chip modules 103 connected to the processor 101 through on-chip communication interfaces 102, and may be connected to the off-chip modules 300 through different communication interfaces 200 to implement different functions.
During operation, the processor generally sends control commands to the functional modules, such as the on-chip modules or the off-chip modules, and then waits for responses from the functional modules. If the functional modules fail to respond to the processor in time, the processor can continuously wait for the response of the functional modules, so that the working resources of the processor are occupied, and the load of the processor is increased.
Disclosure of Invention
The embodiment of the invention provides a control method and device of a processor and electronic equipment, and aims to solve the problem that the load of the processor can be increased by the existing control method of the processor.
In order to solve the technical problem, the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a method for controlling a processor, including:
monitoring a response signal aiming at a control instruction after the processor sends the control instruction to a functional module;
and if the answer signal is not monitored within the preset time length, finishing monitoring the answer signal.
Optionally, after the processor sends the control instruction, the method further includes:
establishing a first timer with the timing duration being the preset duration;
the monitoring response signals aiming at the control instructions comprises the following steps:
monitoring a response signal aiming at the control instruction within the timing time of the first timer;
if the answer signal is not monitored within the preset time, ending the monitoring of the answer signal, including:
and if the response signal is not monitored when the first timer is timed out, ending the monitoring of the response signal.
Optionally, after monitoring a response signal for the control instruction, the method further includes:
and if the answer signal is monitored, closing the first timer.
Optionally, after the ending of the listening for the reply signal, the method further comprises:
the first timer is turned off.
Optionally, after the ending of the listening for the reply signal, the method further includes:
acquiring the working state of the functional module aimed at by the control instruction;
and if the functional module is in a fault state, sending a fault prompt signal to a user.
Optionally, after detecting the operating state of the functional module to which the control instruction is directed, the method further includes:
determining the importance level of the control instruction;
and if the functional module is in a non-fault state and the importance degree grade of the control instruction is greater than a preset grade threshold value, the control instruction is sent to the functional module again.
Optionally, the sending the control instruction to the functional module again further includes:
and establishing a second timer, and monitoring a response signal aiming at the retransmitted control instruction within the timing duration of the second timer.
Optionally, the timing duration of the second timer is less than the timing duration of the first timer.
In a second aspect, an embodiment of the present invention provides a control apparatus for a processor, including:
the monitoring module is used for monitoring a response signal aiming at the control instruction after the processor sends the control instruction to the functional module;
and the interruption module is used for ending the monitoring of the response signal if the response signal is not monitored within the preset time length.
Optionally, the method further comprises:
the establishing module is used for establishing a first timer with the timing duration being the preset duration;
the monitoring module is specifically configured to monitor a response signal for the control instruction within a timing time of the first timer;
the interruption module is specifically configured to end monitoring of the response signal if the response signal is not monitored when the first timer ends.
Optionally, the apparatus further includes a closing module, configured to close the first timer if the answer signal is monitored.
Optionally, the method further comprises:
the acquisition module is used for acquiring the working state of the functional module aimed by the control instruction;
and the first sending module is used for sending a fault prompt signal to a user if the functional module is in a fault state.
Optionally, the method further comprises:
the determining module is used for determining the importance degree grade of the control instruction;
and the second sending module is used for sending the control instruction to the functional module again if the functional module is in a non-failure state and the importance degree grade of the control instruction is greater than a preset grade threshold value.
In a third aspect, an embodiment of the present invention provides an electronic device, including a processor, a memory, and a computer program stored on the memory and operable on the processor, where the computer program, when executed by the processor, implements the steps of the control method of the processor according to any one of the above.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the control method of the processor described in any one of the above.
In this way, in the embodiment of the present invention, by monitoring the response signal for the control instruction sent by the processor within the preset time period, if the module targeted by the control instruction fails to return the response signal in response to the control instruction even though the module targeted by the control instruction fails, the processor may also end monitoring the response signal after the preset time period, thereby avoiding continuously monitoring the response signal and increasing the load of the processor.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a microcontroller and an off-chip module connected to the microcontroller;
FIG. 2 is a flow chart of a method for controlling a processor according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for controlling a processor according to an embodiment of the present invention;
fig. 4 is a block diagram of a control device of a processor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a control method of a processor.
As shown in fig. 2, the method comprises the steps of:
step 201: and monitoring a response signal aiming at the control instruction after the processor sends the control instruction to the functional module.
In the technical solution of this embodiment, the control instruction is sent to the corresponding functional module by the processor to control the corresponding functional module to implement the corresponding function.
The functional module may be an actual module system or chip, and taking the example that the method is applied to a vehicle as an illustration, the processor may be a processor in an MCU in an on-board computer or a vehicle controller of the vehicle, and the functional module may refer to an on-chip module of the MCU, or may be an off-chip module, such as a control chip of an air conditioning system of the vehicle. The functional modules may also refer to virtual modules, such as computer program modules, that implement particular functions.
After the processor phase functional module sends the corresponding control instruction, the corresponding functional module returns a response signal aiming at the control instruction according to the requirement, so that the processor can obtain the execution condition or other information of the control instruction.
Step 202: and if the answer signal is not monitored within the preset time length, finishing monitoring the answer signal.
In this embodiment, the monitoring of the response signal is performed within a preset time period, which may be set as required, for example, various time periods such as 1 minute, 5 minutes, 10 minutes, and the like.
Within the preset time period, if the response signal is monitored, the relevant operation is further performed according to needs, and reference may be made to the relevant technology, which is not further defined and described herein.
If the answer signal is not monitored within the preset time length, the monitoring for the answer signal is ended, and simultaneously, hardware loads provided by monitoring for the answer signal, such as corresponding work processes of the processor, corresponding memory loads and the like, are recovered.
In one embodiment, the listening process for the reply signal is specifically to turn on a receiving function for a specific signal, and the reply signal is the specific signal, so that the processor can receive and process the reply signal if within a preset time period.
After the preset time length is reached, the receiving function aiming at the specific signal is closed, at the moment, the processor cannot receive the response signal no matter whether the response signal is returned or not, and correspondingly, the response signal does not need to be processed by consuming loads.
In this way, in the embodiment of the present invention, by monitoring the response signal for the control instruction sent by the processor within the preset time period, if the module targeted by the control instruction fails to return the response signal in response to the control instruction even though the module targeted by the control instruction fails, the processor may also end monitoring the response signal after the preset time period, thereby avoiding continuously monitoring the response signal and increasing the load of the processor.
Optionally, after the processor sends the control instruction, the method further includes:
establishing a first timer with the timing duration being the preset duration;
the monitoring response signals aiming at the control instructions comprises the following steps:
monitoring a response signal aiming at the control instruction within the timing time of the first timer;
if the answer signal is not monitored within the preset time, ending the monitoring of the answer signal, including:
and if the response signal is not monitored when the first timer is timed out, ending the monitoring of the response signal.
In this embodiment, the preset duration is determined by establishing a countdown timer, and before the countdown timer is finished, the processor may receive the response signal, or may understand that the function of receiving the response signal is in an on state.
When the timer finishes timing, if the answer signal is not received, the monitoring of the answer signal is finished, and therefore the load of the processor is saved.
Furthermore, after the timer completes the function, the timer is also closed, and the recovery of the hardware performance can be realized. Specifically, if the answer signal is monitored, the first timer is closed. And if the answer signal is not monitored, closing the first timer when the timing of the timer is over.
Therefore, whether the response signal is received or not, the first timer is closed under a certain condition, and the longest time of the first timer does not exceed the timing duration of the first timer, so that the occupation of hardware load is reduced.
Optionally, after the ending of the listening for the reply signal, the method further includes:
acquiring the working state of the functional module aimed at by the control instruction;
and if the functional module is in a fault state, sending a fault prompt signal to a user.
In this embodiment, if the response signal is not received, it indicates that the functional module targeted by the control instruction is in an abnormal state, specifically, a fault may occur, or the response signal may not be normally transmitted due to other reasons, for example, the system data processing amount is large.
Therefore, in this embodiment, the working state of the functional module is further detected, and a specific detection method refers to related technologies, and a specific detection method is not further limited herein.
If the functional module is found to be out of order, a corresponding prompt signal is sent to the user through one or more modes including but not limited to voice, pop window, image and vibration to prompt the existence of the failure, so that the user can know the existing problems and timely eliminate the failure.
Optionally, after detecting the operating state of the functional module to which the control instruction is directed, the method further includes:
determining the importance level of the control instruction;
and if the functional module is in a non-fault state and the importance degree grade of the control instruction is greater than a preset grade threshold value, the control instruction is sent to the functional module again.
If the functional module is in a non-failure state, it may be that the control instruction is not normally transmitted or the response signal is not normally returned due to various factors such as data transmission, temporary busy functional module, and the like.
If the importance degree of the task executed by the processor by sending the control instruction is low, no matter whether the control instruction is executed successfully or not, the control instruction does not need to be sent again so as to avoid occupying the load of the processor.
Conversely, if the task is relatively important, the control instruction is re-sent once to improve the probability that the task is normally executed.
Optionally, the sending the control instruction to the functional module again further includes:
and establishing a second timer, and monitoring a response signal aiming at the retransmitted control instruction within the timing duration of the second timer.
Similarly, after the control command is retransmitted, in this embodiment, a second timer is further established to listen for the response signal within the timing duration of the second timer, and if the response signal is received within the timing duration of the second timer, the control command is executed in the functional module, similarly to the above process.
When a response signal corresponding to the control command transmitted first is not received, the control command of relatively importance is repeatedly transmitted, which contributes to an increase in the possibility of execution of the control command.
In an alternative embodiment, the timing duration of the second timer is less than the timing duration of the first timer.
In this embodiment, if the control command is transmitted for the second time and a valid response signal is not obtained yet, the possibility of obtaining a response signal subsequently is low. Therefore, in this embodiment, the timing duration of the second timer is controlled to be shorter than the timing duration of the first timer, and of course, the timing duration of the second timer cannot be shorter than the normal return duration of the reply signal. In this way, by setting the timing duration of the second timer, the possibility of receiving the response signal can be improved to some extent, and the processor load which may be increased due to the excessively long waiting time can be avoided.
As shown in fig. 3, the control method of the processor in this embodiment may be understood that, when a certain command needs to be executed, the processor first sends a control instruction to the functional module, and simultaneously establishes a timer (the first timer mentioned above), and then starts a function of receiving a response signal corresponding to the control instruction.
Within the timing time range of the timer (the preset time length), if the response signal is received, the functional module is indicated to work normally, and at this time, the timer and the function of receiving the response signal can be closed.
If the timer is overtime, that is, the response signal is not received within the preset time length, it indicates that the functional module may have a fault, and at this time, the timer and the receiving function for the response signal are also turned off, so as to reduce the load of the processor.
As shown in fig. 4, an embodiment of the present invention further provides a control apparatus 400 for a processor, including:
a monitoring module 401, configured to monitor a response signal for a control instruction after the processor sends the control instruction to a function module;
an interruption module 402, configured to terminate monitoring of the response signal if the response signal is not monitored within a preset time period.
Optionally, the method further comprises:
the establishing module is used for establishing a first timer with the timing duration being the preset duration;
the monitoring module 401 is specifically configured to monitor a response signal for the control instruction within the timing time of the first timer;
the interrupting module 402 is specifically configured to end monitoring the response signal if the response signal is not monitored when the first timer is timed out.
Optionally, the method further comprises:
and the closing module is used for closing the first timer if the response signal is monitored.
Optionally, the closing module is further configured to close the first timer after the end of the listening for the reply signal.
Optionally, the method further comprises:
the acquisition module is used for acquiring the working state of the functional module aimed by the control instruction;
and the prompt signal sending module is used for sending a fault prompt signal to a user if the functional module is in a fault state.
Optionally, the method further comprises:
the determining module is used for determining the importance degree grade of the control instruction;
and the sending module is used for sending the control instruction to the functional module again if the functional module is in a non-fault state and the importance degree grade of the control instruction is greater than a preset grade threshold value.
Optionally, the establishing module is further configured to establish a second timer, and monitor a response signal for the retransmitted control instruction within a timing duration of the second timer.
Optionally, the timing duration of the second timer is less than the timing duration of the first timer.
The control device 400 of the processor of this embodiment can implement the processes of the above method embodiments, and implement substantially the same technical effects, which are not described herein again.
Optionally, an embodiment of the present invention further provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, where the computer program, when executed by the processor, implements each process of the embodiment of the control method for the processor, and can achieve the same technical effect, and details are not repeated here to avoid repetition.
The embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements each process of the control method embodiment of the processor, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here. The computer-readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (15)
1. A method for controlling a processor, comprising the steps of:
monitoring a response signal aiming at a control instruction after the processor sends the control instruction to a functional module;
and if the answer signal is not monitored within the preset time length, finishing monitoring the answer signal.
2. The method for controlling a processor according to claim 1, wherein after the processor sends the control instruction, the method further comprises:
establishing a first timer with the timing duration being the preset duration;
the monitoring response signals aiming at the control instructions comprises the following steps:
monitoring a response signal aiming at the control instruction within the timing time of the first timer;
if the answer signal is not monitored within the preset time, ending the monitoring of the answer signal, including:
and if the response signal is not monitored when the first timer is timed out, ending the monitoring of the response signal.
3. The method of claim 2, wherein the listening for a reply signal to the control instruction further comprises:
and if the answer signal is monitored, closing the first timer.
4. The method of controlling a processor according to claim 2, wherein after the ending of the listening for the reply signal, the method further comprises:
the first timer is turned off.
5. The method of controlling a processor according to claim 1, wherein after the ending of the listening for the reply signal, further comprising:
acquiring the working state of the functional module aimed at by the control instruction;
and if the functional module is in a fault state, sending a fault prompt signal to a user.
6. The method for controlling a processor according to claim 5, wherein after the detecting the operating state of the functional module to which the control instruction is directed, the method further comprises:
determining the importance level of the control instruction;
and if the functional module is in a non-fault state and the importance degree grade of the control instruction is greater than a preset grade threshold value, the control instruction is sent to the functional module again.
7. The method of controlling a processor according to claim 6, wherein said resending the control instruction to the functional module further comprises:
and establishing a second timer, and monitoring a response signal aiming at the retransmitted control instruction within the timing duration of the second timer.
8. The method of controlling a processor according to claim 6, wherein a timing length of the second timer is shorter than a timing length of the first timer.
9. A control apparatus of a processor, comprising:
the monitoring module is used for monitoring a response signal aiming at the control instruction after the processor sends the control instruction to the functional module;
and the interruption module is used for ending the monitoring of the response signal if the response signal is not monitored within the preset time length.
10. The processor control apparatus of claim 9, further comprising:
the establishing module is used for establishing a first timer with the timing duration being the preset duration;
the monitoring module is specifically configured to monitor a response signal for the control instruction within a timing time of the first timer;
the interruption module is specifically configured to end monitoring of the response signal if the response signal is not monitored when the first timer ends.
11. The processor control device of claim 10, further comprising a shutdown module to shut down the first timer if the reply signal is heard.
12. The processor control apparatus of claim 9, further comprising:
the acquisition module is used for acquiring the working state of the functional module aimed by the control instruction;
and the first sending module is used for sending a fault prompt signal to a user if the functional module is in a fault state.
13. The processor control apparatus of claim 12, further comprising:
the determining module is used for determining the importance degree grade of the control instruction;
and the second sending module is used for sending the control instruction to the functional module again if the functional module is in a non-failure state and the importance degree grade of the control instruction is greater than a preset grade threshold value.
14. An electronic device, comprising a processor, a memory and a computer program stored on the memory and executable on the processor, the computer program, when executed by the processor, implementing the steps of the control method of the processor according to any one of claims 1 to 8.
15. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of a method of controlling the processor of any one of claims 1 to 8.
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