CN113126817A - Capacitance sensing circuit, related chip and touch device - Google Patents

Capacitance sensing circuit, related chip and touch device Download PDF

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CN113126817A
CN113126817A CN202110268896.1A CN202110268896A CN113126817A CN 113126817 A CN113126817 A CN 113126817A CN 202110268896 A CN202110268896 A CN 202110268896A CN 113126817 A CN113126817 A CN 113126817A
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terminal
capacitance
coupled
switch
circuit
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黄思衡
王文祺
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Huiding Technology Private Ltd
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Yaoxin Technology Co ltd
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Priority to PCT/CN2021/096743 priority patent/WO2022188276A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means

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Abstract

The application discloses a capacitance sensing circuit, a related chip and a touch device. The capacitance sensing circuit comprises an input end, a charging circuit, a discharging time control circuit and a capacitance amplifying circuit. The input end is coupled to a capacitor of the touch panel, and the capacitor has an inherent capacitance value. The charging circuit provides an operating voltage to the input terminal in a first period so that the capacitor is charged to the operating voltage. The discharge time control circuit controls the discharge circuit to discharge the capacitor during the discharge time. The capacitance amplifying circuit generates a sensing voltage according to the reference voltage and the voltage of the input end in a third time interval after the second time interval.

Description

Capacitance sensing circuit, related chip and touch device
Technical Field
The present disclosure relates to a capacitive sensing circuit, and more particularly, to a capacitive sensing circuit for touch detection.
Background
Fig. 1 is a schematic diagram of touch detection using the capacitive sensing element CS 1. In fig. 1, the capacitance sensing element CS1 has a plate capacitor structure, wherein the upper plate E1 of the capacitance sensing element CS1 is disposed below the protection panel CP, so that when a finger or a conductive object approaches the capacitance sensing element CS1, the coupling capacitance of the finger or the object is coupled to the upper plate E1 of the capacitance sensing element CS1, and the lower plate E2 of the capacitance sensing element CS1 is grounded. For example, when a finger or a conductive object approaches the capacitive sensing element CS1, a coupling capacitance C is generated between the top plate E1 of the capacitive sensing element CS1 and the fingerBKAnd the coupling capacitor CBKCan be equivalent to the human bodyContainer CBGConnected in series and grounded. That is, the capacitance sensing element CS1 and the coupling capacitor CBKAnd human equivalent capacitance CBGThe equivalent capacitors after the two are connected in series are connected in parallel. In this case, the capacitance value sensed by the capacitance sensing element CS1 is not limited to the inherent capacitance value CbaseIn addition, the coupling capacitor C is connected with the capacitance sensing part CS1 in parallel because of the proximity of the human bodyBKAnd human equivalent capacitance CBGIt is related. For example, the sensing capacitance value C of the capacitance sensing element CS1SMay be represented by formula (1).
CS＝Cbase+ Delta C type (1)
In the formula (1), Δ C is a sensing capacitance variation of the capacitance sensing element CS1 caused by the proximity of a human body, and according to the foregoing description, the sensing capacitance variation Δ C is equivalent to the coupling capacitance CBKAnd human equivalent capacitance CBGThe capacitance value after the two are connected in series.
Since the sensing capacitance value C of the capacitive sensing element CS1 is obtained when a human body approaches the capacitive sensing element CS1SThe change is generated, and therefore, whether a touch event is generated on the touch panel can be determined according to the magnitude of the sensing capacitance change Δ C. However, in a flexible touch screen, such as a Y-OCTA screen, the capacitance value C inherent in the capacitive sensing element isbaseBetween about 200pF and 600pF, and the sensing capacitance change ac due to the proximity of the human body is only about 300 fF. Since there is a difference of about thousand times between the two, when detecting the variation Δ C of the sensing capacitance, it is determined that the inherent capacitance C is simultaneously detectedbaseAnd the sensing capacitance variation Δ C are sensed together, even if the inherent capacitance value C is detectedbaseThe sensing result of (2) has only a small error, and may also cause a significant error to the sensing result of the sensed capacitance variation Δ C, so that the accuracy of touch detection is reduced. Therefore, how to reduce the inherent capacitance value C when detecting the capacitance variation Δ CbaseThe influence on the sensing result becomes a problem to be solved.
Disclosure of Invention
One objective of the present disclosure is to disclose a capacitive sensing circuit, a related chip and a touch device capable of reducing errors, so as to solve the above problems.
An embodiment of the present application provides a capacitance sensing circuit for generating a plurality of sensing voltages according to variations of sensing capacitance values of a plurality of capacitance sensing elements of a touch panel. The capacitance sensing circuit comprises a first input end, a first charging circuit, a first discharging circuit and a first capacitance amplifying circuit. The first input end is coupled to a first capacitance sensing element of the touch panel, and the first capacitance sensing element has a first inherent capacitance value. The first charging circuit is coupled to an operating voltage and used for providing the operating voltage to the first input end in a first period so that the first capacitance sensing element is charged to the operating voltage. The first discharge circuit is coupled to a ground voltage for discharging the first capacitive sensing element. The discharge time control circuit is used for controlling the discharge time of the first capacitance sensing part by the first discharge circuit in a second time interval after the first time interval. The first capacitance amplifying circuit is used for generating a first sensing voltage according to a reference voltage and the voltage of the first input end in a third time interval after the second time interval. The operating voltage is twice the reference voltage.
Another embodiment of the present application provides a chip including the capacitance sensing circuit.
Another embodiment of the present application provides a touch device, which includes a capacitive sensing circuit, a touch panel, and a controller. The controller is used for judging a touch event on the touch panel according to the sensing voltages.
The capacitance sensing circuit, the related chip and the touch device can enable the sensing capacitance piece to release preset electric quantity so as to reduce the influence of the intrinsic capacitance value of the sensing capacitance piece on the sensing voltage, and therefore the sensing capacitance value variation caused by the approach of a human body can be presented more directly.
Drawings
Fig. 1 is a schematic diagram of touch detection using a capacitive sensing element.
Fig. 2 is a schematic view of a touch device according to an embodiment of the present application.
Fig. 3 is a timing diagram of signals detected by the capacitance sensing circuit of fig. 2.
Fig. 4 is a schematic diagram of a discharge time control circuit according to an embodiment of the present application.
FIG. 5 is a schematic diagram of a capacitive sensing circuit according to another embodiment of the present application.
Fig. 6 is a timing diagram of signals in the detection of the capacitance sensing circuit of fig. 5.
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
Fig. 2 is a schematic diagram of a touch device 10 according to an embodiment of the present disclosure. The touch device 10 may include a capacitive sensing circuit 100, a touch panel TP1, and a controller U1. The touch panel TP1 may include a plurality of capacitive sensing elements CS 1-CSN, and the capacitive sensing circuit 100 may be coupled to the capacitive sensing elements CS 1-CSN. The capacitive sensing devices CS1 through CSN can be disposed at different positions on the touch panel TP1, the capacitive sensing circuit 100 can generate the sensing voltages VS1 through VSN according to the variation of the sensing capacitance values of the capacitive sensing devices CS1 through CSN, and the controller U1 in the touch device 10 can determine a touch event on the touch panel TP1, such as whether there is a touch on the touch panel TP1 and the touched position coordinates according to the sensing voltages VS1 through VSN. In some embodiments, the capacitive sensing circuit 100 may be fabricated separately as a chip or disposed in the same chip as the controller U1.
In some embodiments, the touch panel TP1 can support both self-capacitance sensing and mutual capacitance sensing to determine touch events. For example, the touch panel TP1 may include horizontal electrodes and vertical electrodes. When a touch event is determined by mutual capacitance sensing, the lateral electrodes of touch panel TP1 receive the code signals, and the code signals on the lateral electrodes are coupled to the vertical electrodes through mutual capacitances between the lateral electrodes and the vertical electrodes. When a finger touches a portion near the intersection of a horizontal electrode and a vertical electrode, the mutual capacitance between the horizontal electrode and the vertical electrode changes, so that the coupling signal on the vertical electrode correspondingly changes, and therefore, by sensing the signal change on the vertical electrode, a touch event on the touch panel TP1 can be determined. When the touch event is determined by self-capacitance sensing, the touch panel TP1 can perform touch detection by using the self-capacitance of the horizontal electrode and the vertical electrode because the horizontal electrode and the system ground have self-capacitance and the vertical electrode and the system ground have self-capacitance. That is, each of the capacitive sensing elements CS 1-CSN shown in fig. 2 can be a self-capacitance formed by the lateral electrode itself and the ground terminal or a self-capacitance formed by the longitudinal electrode itself and the ground terminal in the touch panel TP 1. However, in some other embodiments, the touch panel TP1 may only use self-capacitance sensing to determine touch events, and the capacitive sensing elements CS1 through CSN may be arranged in other ways or formed in other structures.
The capacitance sensing circuit 100 includes input terminals 1101 to 110N, and the input terminals 1101 to 110N are respectively coupled to corresponding capacitance sensing elements of the capacitance sensing elements CS1 to CSN of the touch panel TP 1. The capacitance sensing circuit 100 can detect the variation of the capacitance values of the capacitance sensing elements CS1 to CSN through the input terminals 1101 to 110N to output the corresponding sensing voltages VS1 to VSN.
For example, the capacitance sensing circuit 100 may include first charging circuits 1201 to 120N, first discharging circuits 1301 to 130N, and first capacitance amplifying circuits 1401 to 140N. For convenience of understanding, the operations of the first charging circuit 1201, the first discharging circuit 1301 and the first capacitance amplifying circuit 1401 are taken as an example, and in the present embodiment, the first charging circuits 1202 to 120N, the first discharging circuits 1302 to 130N and the first capacitance amplifying circuits 1402 to 140N may have the same structures and may operate according to the same principles as the first charging circuit 1201, the first discharging circuit 1301 and the first capacitance amplifying circuit 1401, respectively.
In fig. 2, the first input terminal 1101 may be coupled to the first capacitance sensing element CS 1. The first charging circuit 1201 may be coupled to the operating voltage VDD, and may provide the operating voltage VDD to the first input terminal 1101 in a first period of time so that the first capacitive sensing element CS1 is charged to the operating voltage VDD. The first discharging circuit 1201 is coupled to the ground voltage VSS, and is capable of discharging a portion of the electric energy from the first capacitive sensing element CS1 during a discharging time in a second period after the first period, so as to reduce the first intrinsic capacitance C of the first capacitive sensing element CS1B1The effect on the first sense voltage VS 1. Then, the first capacitance amplifying circuit 1401 can generate the first sensing voltage VS1 according to the reference voltage VCM and the voltage of the first input terminal 1101 in a third period after the second period.
In fig. 2, the first capacitance amplifying circuit 1401 may include a differential amplifier 142 and an integrating capacitor CINT. The differential amplifier 142 has a first input terminal and a second input terminal, the first input terminal of the differential amplifier 142 may be a positive input terminal, for example, and the second input terminal of the differential amplifier 142 may be a negative input terminal, for example. The first input terminal of the differential amplifier 142 may be coupled to the reference voltage VCM, and the integrating capacitor CINTMay be coupled between the second input and the output of the differential amplifier 142. In the present embodiment, the reference voltage VCM can be regarded as a reference common mode voltage of the differential amplifier 142, and the negative input terminal of the differential amplifier 142 is coupled to the first input terminal 1101 during the third period, so that during the third period, the differential amplifier 142 can amplify the difference between the voltage of the first input terminal 1101 and the reference voltage VCM to generate the first sensing voltage VS 1.
If the first capacitive sensing element CS1 releases the target electric quantity Q1 during the second period of time without a touch event on the first capacitive sensing element CS1, the voltage VR1 of the first input terminal 1101 will be shown in formula (2), and the first sensing voltage VS1 will be shown in formula (3).
Figure BDA0002973318730000071
Figure BDA0002973318730000072
In the present embodiment, if the operating voltage VDD is twice the reference voltage VCM, then when the target charge Q1 is equal to the difference between the operating voltage VDD and the reference voltage VCM and the first inherent capacitance CB1When the first voltage VR1 and the first sensing voltage VS1 at the first input terminal 1101 are multiplied by (4) and (5), respectively.
Figure BDA0002973318730000073
Figure BDA0002973318730000074
According to equations (4) and (5), the first input terminal and the second input terminal of the differential amplifier 142 will be at the reference voltage VCM also during the third period, and thus the first sensing voltage VS1 will be 0 during the third period. That is, when no touch event occurs on the first capacitive sensing element CS1, the first sensing voltage VS1 and the first intrinsic capacitance C of the first capacitive sensing element CS1B1Is irrelevant to the size of the device. In contrast, when the touch event occurs on the first capacitive sensing element CS1 and the sensing capacitance value of the first capacitive sensing element CS1 changes, the voltage VR1 of the first input terminal 1101 can be represented by formula (6), and the first sensing voltage VS1 can be represented by formula (7).
Figure BDA0002973318730000081
Figure BDA0002973318730000082
In equations (6) and (7), Δ C1 is the variation of the sensing capacitance value of the first capacitive sensing element CS1 caused by the proximity of a human body, that is, when a touch event occurs on the first capacitive sensing element CS1, the sensing capacitance value of the first capacitive sensing element CS1 is changed from the original first inherent capacitance value CB1Becomes a first inherent capacitance value CB1And the sum of the sensed capacitance value change Δ C1. In this case, according to the formula (7), when the touch event occurs on the first capacitive sensing element CS1, the first sensing voltage VS1 is only related to the variation Δ C1 of the sensing capacitance value of the first capacitive sensing element CS1 caused by the proximity of the human body, and still related to the first intrinsic capacitance value C of the first capacitive sensing element CS1 itselfB1The first sensing voltage VS1 can more directly exhibit the sensing capacitance variation Δ C1 of the first capacitive sensing element CS1 caused by the approach of a human body, so that the touch device 10 can perform touch detection more accurately.
In fig. 2, the first charging circuit 1201 may include a first switch SW1 and a first resistor R1. The first switch SW1 has a first terminal, a second terminal and a control terminal, the first terminal of the first switch SW1 is coupled to the operating voltage VDD, and the control terminal of the first switch SW1 receives the first control signal SIGCT1. The first resistor R1 has a first end and a second end, the first end of the first resistor R1 is coupled to the second end of the first switch SW1, and the second end of the first resistor R1 is coupled to the first input terminal 1101.
The first discharge circuit 1301 may include a second resistor R2 and a second switch SW 2. The second resistor R2 has a first terminal and a second terminal, and the first terminal of the second resistor R2 is coupled to the first input terminal 1101. The second switch SW2 has a first terminal, a second terminal, and a control terminal, the first terminal of the second switch SW2 is coupled to the second terminal of the second resistor R2, the second terminal of the second switch SW2 is coupled to the ground voltage VSS, and the control terminal of the second switch SW2 receives the second control signal SIGCT2。
The first capacitive amplification circuit 1401 may include a differential amplifier 142, a fifth switch SW5, a sixth switch SW6, and an integrating capacitorContainer CINT. The differential amplifier 142 has a first input terminal, a second input terminal and an output terminal, and the first input terminal of the differential amplifier 142 is coupled to the reference voltage VCM. In this embodiment, the first input terminal of the differential amplifier 142 may be a positive input terminal, and the second input terminal of the differential amplifier 142 may be a negative input terminal.
The fifth switch SW5 has a first terminal, a second terminal and a control terminal, the first terminal of the fifth switch SW5 is coupled to the first input terminal 1101, the second terminal of the fifth switch SW5 is coupled to the second input terminal of the differential amplifier 142, and the control terminal of the fifth switch SW5 receives the fourth control signal SIGCT4. Integrating capacitor element CINTHaving a first end and a second end, an integrating capacitor element CINTIs coupled to the second input terminal of the differential amplifier 142, and an integrating capacitor element CINTAnd a second terminal coupled to the output terminal of the differential amplifier 142. The sixth switch SW6 has a first terminal, a second terminal and a control terminal, and the first terminal of the sixth switch SW6 is coupled to the integrating capacitor CINTAnd a second terminal of the sixth switch SW6 is coupled to the integrating capacitor CINTA control terminal of the sixth switch SW6 may receive a reset control signal SIGRST。
Fig. 3 is a timing diagram of signals detected by the capacitance sensing circuit 100. In the first period TP1 of fig. 3, the first control signal SIGCT1At a high potential, a second control signal SIGCT2At low voltage, the first switch SW1 is turned on and the second switch SW2 is turned off, so the first charging circuit 1201 charges the first capacitive sensing element CS1 through the first resistor R1.
Next, in the second period TP2 of fig. 3, the first control signal SIGCT1At a low potential, a second control signal SIGCT2At high, the first switch SW1 is turned off and the second switch SW2 is turned on, so the first discharging circuit 1301 discharges the first capacitive sensing element CS1 through the second resistor R2. According to the physical characteristics of the capacitor discharge, the size of the second resistor R2 is properly selected and the second control signal SIG is properly controlledCT2Discharge time T at high potentialDSCIn this case, the first capacitance can be controlledThe discharged amount of the sensing member CS1 in the second period TP 2. For example, if the target charge to be discharged is (VDD-VCM) CB1Indicating that the voltage at the first input terminal 1101 has to be discharged from the operating voltage VDD to the magnitude of the reference voltage VCM. If the operating voltage VDD is twice the reference voltage VCM, the discharge time T is determined according to the discharge characteristic of the capacitorDSCAnd a first inherent capacitance value C of the first capacitive sensing element CS1B1And the second resistor R2 can be expressed by the formula (8) and can be reduced to the formula (9).
Figure BDA0002973318730000101
TDSC＝ln 2×R2×CB1Formula (9)
That is, in the second period TP2, if the second control signal SIGCT2Can be at a discharge time TDSCThe first capacitance sensing element CS1 releases the target charge (VDD-VCM) CB1. Thus, according to the description of equation (4), the voltage VR1 at the first input terminal 1101 will be equal to the first inherent capacitance C of the first capacitive sensing element CS1B1Is irrelevant.
Next, in the third period TP3, the fourth control signal SIGCT4The voltage level of the first capacitor amplification circuit 1401 is high, such that the fifth switch SW5 is turned on, and the first capacitor amplification circuit 1401 generates the first sensing voltage VS1 according to the difference between the voltage VR1 at the first input terminal 1101 and the reference voltage VCM. In this case, the target charge amount (VDD-VCM) C is discharged due to the first capacitive sensing element CS1B1Therefore, the first sensing voltage VS1 will be equal to the first inherent capacitance C of the first capacitive sensing element CS1B1Regardless, the capacitance change Δ C1 of the first capacitive sensing element CS1 caused by the proximity of a human body can be more directly presented, so that the touch device 10 can perform touch detection more accurately.
In fig. 3, the fourth control signal SIGCT4Reset signal SIG before highRSTCan be changed from low potential to high potential and then recovered from high potentialThen, the voltage is reduced to a low level, so that the integrating capacitor C in the first capacitor amplifying circuit 1401 is reducedINTCan be reset to discharge in advance to avoid the integral capacitor CINTThe residual charge affects the generation of the first sensing voltage VS 1. Although in FIG. 3, the reset signal SIGRSTIs changed to the high potential between the second period TP2, i.e., the third period TP3, however, in some other embodiments, the reset signal SIGRSTProvided that the fifth switch SW5 is turned on by the fourth control signal SIGCT4Before conducting, the voltage is changed from low potential to high potential and then restored from high potential to low potential to make the integrating capacitor CINTIt is sufficient to be completely discharged to complete the reset, and thus it may become a high potential in the second period TP 2.
Furthermore, in the embodiment, in order to control the discharging time of the first discharging circuit 1301 to the first capacitance sensing element CS1, that is, the second control signal SIG more accuratelyCT2Discharge time T at high potentialDSCThe capacitance sensing circuit 100 may include a discharge time control circuit 150 to generate the second control signal SIGCT2To control the discharge time T of the first discharge circuit 1301 in the second period TP2DSCThereby enabling the first capacitance sensing part CS1 to be discharged for a discharge time TDSCReleasing the target electric quantity. Fig. 4 is a schematic diagram of a discharge time control circuit 150 according to an embodiment of the present application. The discharge time control circuit 150 includes a reference capacitance element CRA third switch SW3, a third resistor R3, a fourth resistor R4, a fourth switch SW4, a comparator 152, a D-type flip-flop 154 and an AND gate 156.
Reference capacitor element CRHaving a first end and a second end, a reference capacitor element CRAnd the second terminal of the second transistor is coupled to a ground voltage VSS. The third switch SW3 has a first terminal, a second terminal and a control terminal, the first terminal of the third switch SW3 is coupled to the ground voltage VSS, and the third switch SW3 receives the first control signal SIGCT1. The third resistor R3 has a first terminal and a second terminal, the first terminal of the third resistor R3 is coupled to the second terminal of the third switch SW3, and the second terminal of the third resistor R3 is coupled to the reference capacitor CRThe first end of (a). The fourth resistor R4 has a first end and a second end, and the first end of the fourth resistor R4Coupled to the reference capacitor CRThe first end of (a). The fourth switch SW4 has a first terminal, a second terminal and a control terminal, the first terminal of the fourth switch SW4 is coupled to the second terminal of the fourth resistor R4, the second terminal of the fourth switch SW4 is coupled to the operating voltage VDD, and the control terminal of the fourth switch SW4 can receive the second control signal SIGCT2。
The comparator 152 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the comparator 152 is coupled to the reference voltage VCM, the second input terminal of the comparator 152 is coupled to the reference capacitor CRThe first end of (a). The D-type flip-flop 154 has a data terminal D, a reset terminal RST, a rising edge trigger terminal TRG, an output terminal Q, and an inverted output terminal Q'. The reset RST of the D-type flip-flop 154 receives a first control signal SIGCT1Inverted control signal SIGCT1BThe rising edge trigger terminal of the D-type flip-flop 154 is coupled to the output terminal of the comparator 152. The AND gate 156 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the AND gate 156 is coupled to the inverted output terminal Q' of the D-type flip-flop 154, and the second input terminal of the AND gate 156 can receive the third control signal SIGCT3And the output of the and gate 156 may output a second control signal SIGCT2。
In the first period TP1 of fig. 3, the first control signal SIGCT1To a high potential, and inverting the control signal SIGCT1BThe voltage is low, so the D-type flip-flop 154 is in a reset state, and the inverted output Q' outputs a high signal. However, because of the third control signal SIGCT3The first period TP1 is kept at the low voltage level, so the second control signal SIG output from the and gate 156CT2Still at a low potential.
Next, in the second period TP2 of fig. 3, the first control signal SIGCT1Becomes a low potential and the third control signal SIGCT3Becomes high, both input terminals of the AND gate 156 are at high, and thus the second control signal SIG starts to be outputted at high levelCT2. When the second control signal SIGCT2When the voltage level is high, the discharge time control circuit 150 will couple the reference capacitor C via the fourth resistor R4RFirst end of (2) chargingElectric, while referring to the capacitive element CRWhen the first terminal of the comparator 152 is charged to be greater than the reference voltage VCM, the voltage level outputted from the comparator 152 will change, causing the D-type flip-flop 154 to be triggered and output a low voltage signal from the inverting output terminal Q', so that the second control signal SIG outputted from the and gate 156CT2Will go back to the low potential.
In this embodiment, the capacitor element C is referred toRAnd the first inherent capacitance C of the first capacitive sensing element CS1B1The capacitance of the fourth resistor R4 is equal to that of the second resistor R2. In addition, since the operating voltage VDD is twice the reference voltage VCM, the reference capacitance element CRThe time required for the first terminal of the comparator 152 to be charged from the ground voltage VSS to the reference voltage VCM to make the output voltage level of the comparator 152 transition is equal to the time required for the first capacitive sensing element CS1 to discharge the target charge (VDD-VCM) C through the second resistor R2B1The time required to discharge from the operating voltage VDD to the reference voltage VCM is the same, that is, the discharge-time control circuit 150 may cause the second control signal SIGCT2Discharge time T at second period TP2DSCIs internally kept at a high potential and is discharged for a time TDSCAfter the end, the voltage level returns to the low level, so that the first capacitive sensing element CS1 can discharge the target electrical quantity (VDD-VCM) C close to or equal to the target electrical quantityB1The amount of electricity of.
In addition, in some embodiments, the reference capacitor C may be used to reduce the area required by the capacitive sensing circuit 100RIs a first intrinsic capacitance value CB1K is greater than 1, and the resistance value of the third resistor R3 is K times the resistance value of the first resistor R1, and the resistance value of the fourth resistor R4 is K times the resistance value of the second resistor R2. Thus, the reference capacitor CRThe product of the capacitance of (C) and the third resistor R3 (or the fourth resistor R4) is equal to the first intrinsic capacitance CB1The product of the first resistor R1 (or the second resistor R2) is the same, so that the two resistors have the same charge-discharge time constant and the same charge-discharge characteristics. In this case, the reference capacitance element CRWhen the output potential of the comparator 152 is changed from the ground voltage VSS to the reference voltage VCMThe target charge (VDD-VCM) C is discharged from the first capacitive sensing element CS1 through the second resistor R2B1The time required for discharging from the operating voltage VDD to the reference voltage VCM is the same, and the reference capacitor CRThe required area can be reduced.
Further, in the present embodiment, the third control signal SIGCT3Will remain at the high potential in the second period TP2 and in order to ensure the second control signal SIGCT2Not early changed back to low potential, third control signal SIGCT3Can be kept at a high potential for a long time to ensure the second control signal SIGCT2After the fourth switch SW4 is turned on, the reference capacitor element C is turned onRIs charged to the reference voltage VCM and then becomes a low potential without being affected by the third control signal SIGCT3Early low, causing AND gate 156 to early gate the second control signal SIGCT2Pulling back the low potential.
Since the capacitance sensing circuit 100 can discharge the target amount of electricity from the first capacitance sensing element CS1, the first inherent capacitance C of the first capacitance sensing element CS1 can be eliminatedB1The influence on the first sensing voltage VS1 makes the first sensing voltage VS1 more directly exhibit the variation Δ C1 of the sensing capacitance of the first capacitive sensing element CS1 caused by the proximity of human body and the first inherent capacitance CB1Is irrelevant to the size of the device. In this way, the touch device 10 can obtain a more accurate result when performing the touch detection according to the first sensing voltage VS 1.
In the embodiment of FIG. 2, the second control signal SIG generated by the charge-time control circuit 150CT2It can also be used to control other discharging circuits 1302 to 130N to discharge the predetermined amount of electricity from the capacitive sensing elements CS2 to CSN. For example, if the discharge circuits 1302 to 130N are also in the second control signal SIG under the condition that the capacitance values of the capacitive sensing elements CS1 to CSN are all the sameCT2Discharge time T at high potentialDSCDischarging the capacitive sensing elements CS 2-CSN eliminates the portion of the sensing voltages VS 2-VSN related to the intrinsic capacitance of the capacitive sensing elements CS 1-CSN, thereby more directly presenting the capacitive sensing elements CS 2-CSNThe CSN is the amount of change in the sensing capacitance due to the proximity of a human body.
However, in some embodiments, due to the differences in the manufacturing process, the capacitance values of the capacitive sensing elements CS 1-CSN may not be identical, and may have an error of about 10% therebetween. In this case, the capacitance sensing circuit 100 may generate the second control signal SIG with reference to the capacitance sensing element having the smallest intrinsic capacitance valueCT2And additionally, the error of the inherent capacitance value of other capacitance sensing parts is further removed by the counteracting capacitance.
Fig. 5 is a schematic diagram of a capacitance sensing circuit 200 according to another embodiment of the present application. The capacitance sensing circuit 200 has a similar structure to the capacitance sensing circuit 100 and can operate according to a similar principle. The capacitance sensing circuit 200 may include input terminals 2101 to 210N, charging circuits 2201 to 220N, discharging circuits 2301 to 230N, capacitance amplifying circuits 2401 to 240N, a discharge time control circuit 250, cancellation capacitance elements 2601 to 260N, and cancellation capacitance control circuits 2701 to 270N.
In the present embodiment, since the intrinsic capacitances of the capacitive sensing elements CS 1-CSN are not all the same, after the intrinsic capacitances of the capacitive sensing elements CS 1-CSN are measured, the capacitive sensing element with the smallest intrinsic capacitance can be selected as the reference. For example, if the first inherent capacitance value C of the capacitive sensing element CS1B1The capacitance value of the reference capacitance element C in the discharge time control circuit 250 is smaller than the inherent capacitance values of the other capacitance sensing elements CS 2-CSNRIs set as a first intrinsic capacitance value CB1K times lower. In this way, the discharge time control circuit 250 can control the second control signal SIGCT2At discharge time TDSCIs kept at a high potential, and the first capacitive sensing element CS1 discharges a target charge (VDD-VCM) C after chargingB1. According to the descriptions of equations (6) to (7), the target charge (VDD-VCM) C is discharged from the first capacitive sensing element CS1B1Then, the first sensing voltage VS1 can more directly exhibit the sensing capacitance variation Δ C1 of the first capacitive sensing element CS1 caused by the proximity of human body and the first inherent capacitance CB1Size of (2)Is irrelevant.
After the charging circuits 2302 to 230N charge the capacitive sensing elements CS2 to CSN, the discharging circuits 2302 to 230N also charge the capacitive sensing elements CS2 to CSN according to the second control signal SIGCT2The capacitance sensing elements CS 2-CSN discharge corresponding amounts of electricity synchronously, however, the intrinsic capacitance values of the capacitance sensing elements CS 2-CSN and the first intrinsic capacitance value CB1It may not be completely the same, and therefore, after the capacitive sensing elements CS 2-CSN discharge the corresponding amount of power, the influence of the intrinsic capacitance values of the capacitive sensing elements CS 2-CSN on the sensing voltages VS 2-VSN cannot be completely eliminated, that is, the sensing voltages VS 2-VSN are still related to the intrinsic capacitance values of the capacitive sensing elements CS 2-CSN. To solve this problem, the capacitance sensing circuit 200 can further cancel the amount of electricity that should be released but not released in the capacitance sensing elements CS 2-CSN by the cancellation capacitance elements 2601-260N and the cancellation capacitance control circuits 2701-270N, thereby reducing the error caused by the different inherent capacitance values of the capacitance sensing elements CS 2-CSN.
In fig. 5, the second canceling capacitor element 2602 has a first end and a second end, and the second canceling capacitor control circuit 2702 is coupled to the second canceling capacitor element 2602 and the second input end 2102. In the present embodiment, the second cancellation capacitance control circuit 2702 may include a seventh switch SW7, an eighth switch SW8, a ninth switch SW9 and a tenth switch SW 10.
The seventh switch SW7 has a first terminal, a second terminal and a control terminal, the first terminal of the seventh switch SW7 may be coupled to the ground voltage VSS, the second terminal of the seventh switch SW7 may be coupled to the first terminal of the second offset capacitor 2602, and the control terminal of the seventh switch SW7 may receive the first control signal SIGCT1. The eighth switch SW8 has a first terminal, a second terminal and a control terminal, the first terminal of the eighth switch SW8 is coupled to the second terminal of the second offset capacitor 2602, the second terminal of the eighth switch SW8 is coupled to the operating voltage VDD, and the control terminal of the eighth switch SW8 receives the first control signal SIGCT1. The ninth switch SW9 has a first terminal, a second terminal and a control terminal, the first terminal of the ninth switch SW9 is coupled to the second terminal of the second offset capacitor 2602, the second terminal of the ninth switch SW9 is coupled to the ground voltage VSS, and the control terminal of the ninth switch SW9 is coupled to the ground voltage VSSCan receive a fifth control signal SIGCT5. The tenth switch SW10 has a first terminal, a second terminal and a control terminal, the first terminal of the tenth switch SW10 is coupled to the first terminal of the second offset capacitor 2602, the second terminal of the tenth switch SW10 is coupled to the second input terminal 2102, and the control terminal of the tenth switch SW10 receives the fifth control signal SIGCT5。
Fig. 6 is a timing diagram of signals detected by the capacitance sensing circuit 200. In the first period TP1, the first control signal SIGCT1At a high potential, a second control signal SIGCT2And a fourth control signal SIGCT4And a fifth control signal SIGCT5Is at a low potential. At this time, the second capacitance sensing element CS2 is charged to the operating voltage VDD, the first terminal of the second cancellation capacitor element 2602 is coupled to the ground voltage VSS, and the second terminal of the second cancellation capacitor element 2602 is coupled to the operating voltage VDD.
In the second period TP2, the first control signal SIGCT1Is low and the second control signal SIGCT2Will be at time TDSCIs maintained at a high voltage level such that the second capacitive sensing element CS2 also discharges a voltage close to (VDD-VCM) CB1The amount of electricity of. If the second intrinsic capacitance value C of the second capacitive sensing element CS2 is presentB2And a first inherent capacitance value C of the first capacitive sensing element CS1B1Has a difference of Δ CBThen the second capacitive sensing element CS2 is at time TDSCAfter the partial electric quantity is released internally, the residual electric quantity needs to be released so as to remove the difference value delta CBThe second sensing voltage VS2 and the second inherent capacitance C of the second capacitive sensing element CS2 are influenced by the second sensing voltage VS2B2Is irrelevant to the size of the device.
In order to be able to eliminate the amount of power left to be discharged, in the fourth period TP4 between the second period TP2 and the third period TP3, the fifth control signal SIGCT5Becomes high, the first terminal of the second cancellation capacitor 2602 is coupled to the second input 2102, and the second terminal of the second cancellation capacitor 2602 is coupled to the ground voltage VSS. In this case, the charges stored in the second capacitance sensing element CS2 and the second cancellation capacitance element 2602 are accumulated in the second capacitance sensing element CS2 and the second canceling capacitor element 2602.
In the case that the capacitance sensing element CS2 is not discharged in advance, if the capacitance value of the cancellation capacitor element 2602 is one third of the intrinsic capacitance value of the capacitance sensing element CS2, the cancellation capacitor element 2602 can receive part of the charges in the capacitance sensing element CS2 to remove the part of the sensing voltage VS2 related to the intrinsic capacitance value of the capacitance sensing element CS 2. However, in the present embodiment, since the capacitance sensing circuit 200 can discharge part of the capacitance sensing element CS2 through the discharge circuit 2302, a smaller offset capacitance element 2602 can be used, and the part of the sensing voltage VS2 related to the inherent capacitance of the capacitance sensing element CS2 can still be effectively removed. For example, if the first intrinsic capacitance value CB1And a second inherent capacitance value CB2Has a difference of Δ CBThe discharging circuits 2301 and 2302 are also based on the second control signal SIG of the discharging time control circuit 250CT2Discharge time T at high potentialDSCDischarging is performed, according to the characteristic of capacitor discharging, when the capacitance of the second offset capacitor 2602 is the first inherent capacitance CB1And a second inherent capacitance value CB2Difference Δ C ofBIs/are as follows
Figure BDA0002973318730000191
The remaining power to be removed can be transferred to the second offset capacitor 2602. As such, in the third period TP3, when the fourth control signal SIG isCT4When the voltage level is high, the second sensing voltage VS2 generated by the second capacitance amplifying circuit 2402 can directly exhibit the variation of the sensing capacitance value of the second capacitance sensing element CS2 caused by the approaching of the human body.
In addition, since in general, the difference Δ CBAbout a first intrinsic capacitance value C B110% of the capacitance, the capacitance required for the offset capacitor 2602 of the capacitance sensing circuit 200 can be significantly reduced compared to the prior art. Similarly, the cancellation capacitor elements 2603 through 260N and the cancellation capacitor control circuits 2703 through 270N may also be cancelled by the operation of the cancellation capacitor elements 2602 and the cancellation capacitor control circuits 2702The capacitance values of the capacitance sensing elements CS 3-CSN that should be discharged but not discharged are also smaller, so that the capacitance values needed to cancel the capacitance elements 2603-260N are also smaller, thereby significantly reducing the area needed by the capacitance sensing circuit 200.
In addition, in some embodiments, the canceling capacitor elements 2601 through 260N may include variable capacitors or capacitor arrays, since the intrinsic capacitance values of the capacitive sensing elements CS1 through CSN in the touch panel TP1 are not known when the capacitive sensing circuit 200 is manufactured. Thus, the capacitance values of the offset capacitors 2601 to 260N can be adjusted according to actual requirements. For example, in the present embodiment, the cancellation capacitor 2602 can be controlled by a control signal according to the first intrinsic capacitance CB1And a second inherent capacitance value CB2Difference Δ C ofBBut is changed to effectively eliminate the remaining power to be eliminated in the second capacitive sensing element CS2 during the fourth period TP 4.
Furthermore, although the second control signal SIG can be generated by the discharge time control circuits 150 and 250 in the aforementioned embodimentsCT2Enabling the first capacitive sensing element CS1 to be at time T of the second period TP2DSCMiddle release target electric quantity (VDD-VCM) CB1To eliminate the first inherent capacitance C of the first capacitance sensing element CS1B1The effect on the first sense voltage VS 1. However, in some other embodiments, the second control signal SIG may be generated by the discharge-time control circuit 250 according to the predicted value of the minimum intrinsic capacitance of the capacitive sensing elements CS 1-CSN according to the pre-estimationCT2Then, the offset capacitance elements 2601 to 260N and the offset capacitance control circuits 2701 to 270N are used to remove the charges left in the capacitance sensing elements CS1 to CSN without removal by the aforementioned method. Therefore, it is not necessary to actually detect the intrinsic capacitance values of the capacitive sensing elements CS 1-CSN, and the portions of the sensing voltages VS 1-VSN related to the intrinsic capacitance values of the capacitive sensing elements CS 1-CSN can be effectively removed, so that the sensing voltages VS 1-VSN can directly exhibit the variation of the sensing capacitance values of the capacitive sensing elements due to the proximity of a human body, and the touch device can perform more accurate sensingAnd touch detection.
In summary, the capacitive sensing circuit, the related chip and the touch device provided in the embodiments of the present application can release part of the electric quantity from the capacitive sensing element through the discharging circuit when sensing the capacitive sensing element in the touch panel, so that the influence of the inherent capacitance value of the capacitive sensing element on the sensing voltage can be effectively eliminated. In addition, the capacitance sensing circuit, the related chip and the touch device provided by the embodiment of the application can further eliminate the influence of the intrinsic capacitance value of the capacitance sensing element on the sensing voltage by using the offset capacitance element and the offset capacitance control circuit, so that the sensing voltage generated by the capacitance sensing circuit can directly present the sensing capacitance value variation of the capacitance sensing element caused by the approach of a human body, and the accuracy of touch detection is improved.
The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can still make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (17)

1. A capacitance sensing circuit for generating a plurality of sensing voltages according to variations of sensing capacitance values of a plurality of capacitance sensing elements of a touch panel, the capacitance sensing circuit comprising:
a first input terminal coupled to a first capacitance sensing element of the touch panel, the first capacitance sensing element having a first inherent capacitance value;
a first charging circuit, coupled to an operating voltage, for providing the operating voltage to the first input terminal of the capacitance sensing circuit during a first period of time to charge the first capacitance sensing element to the operating voltage;
a first discharge circuit coupled to a ground voltage for discharging the first capacitance sensing element;
the discharge time control circuit is used for controlling the discharge time of the first capacitance sensing part by the first discharge circuit in a second time interval after the first time interval; and
the first capacitance amplifying circuit is used for generating a first sensing voltage according to a reference voltage and the voltage of the first input end of the capacitance sensing circuit in a third time interval after the second time interval, wherein the operating voltage is twice of the reference voltage.
2. The capacitive sensing circuit of claim 1, wherein the first charging circuit comprises:
a first switch having a first end, a second end, and a control end, the first end of the first switch being coupled to an operating voltage, and the control end of the first switch being configured to receive a first control signal; and
a first resistor having a first end and a second end, the first end of the first resistor being coupled to the second end of the first switch, and the second end of the first resistor being coupled to the first input end of the capacitance sensing circuit.
3. The capacitive sensing circuit of claim 2, wherein said first discharge circuit comprises:
a second resistor having a first end and a second end, the first end of the second resistor being coupled to the first input end of the capacitance sensing circuit; and
a second switch having a first terminal, a second terminal, and a control terminal, the first terminal of the second switch being coupled to the second terminal of the second resistor, the second terminal of the second switch being coupled to the ground voltage, and the control terminal of the second switch being configured to receive a second control signal.
4. The capacitive sensing circuit of claim 3, wherein the discharge time control circuit comprises:
a reference capacitor having a first terminal and a second terminal, the second terminal of the reference capacitor being coupled to the ground voltage;
a third switch having a first terminal, a second terminal, and a control terminal, the first terminal of the third switch being coupled to the ground voltage, and the third switch being configured to receive the first control signal;
a third resistor having a first end and a second end, the first end of the third resistor being coupled to the second end of the third switch, and the second end of the third resistor being coupled to the first end of the reference capacitor;
a fourth resistor having a first end and a second end, the first end of the fourth resistor being coupled to the first end of the reference capacitor;
a fourth switch having a first end, a second end, and a control end, the first end of the fourth switch being coupled to the second end of the fourth resistor, the second end of the fourth switch being coupled to the operating voltage, and the control end of the fourth switch being configured to receive the second control signal;
a comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the comparator is coupled to the reference voltage, and the second input terminal of the comparator is coupled to the first terminal of the reference capacitor;
a D-type flip-flop having a reset terminal, a rising edge trigger terminal, and an inverted output terminal, wherein the reset terminal of the D-type flip-flop is configured to receive an inverted control signal that is inverted from the first control signal, and the rising edge trigger terminal of the D-type flip-flop is coupled to the output terminal of the comparator; and
and an AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the AND gate is coupled to the inverted output terminal of the D-type flip-flop, the second input terminal of the AND gate is configured to receive a third control signal, and the output terminal of the AND gate is configured to output the second control signal.
5. The capacitive sensing circuit of claim 4, wherein:
the capacitance value of the reference capacitance part is one K times of the first inherent capacitance value, wherein K is greater than or equal to 1;
the resistance value of the third resistor is K times that of the first resistor; and
the resistance value of the fourth resistor is K times of the resistance value of the second resistor.
6. The capacitive sensing circuit of claim 4, wherein:
the first control signal is high in the first period and turns on the third switch, and the first control signal is low in the second period and turns off the third switch; and
the third control signal is a low potential in the first period, and the third control signal is a high potential in the second period.
7. The capacitive sensing circuit of claim 1, wherein the first capacitive amplification circuit comprises:
a differential amplifier having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the differential amplifier being coupled to the reference voltage;
a fifth switch having a first end, a second end, and a control end, the first end of the fifth switch being coupled to the first input end of the capacitance sensing circuit, and the second end of the fifth switch being coupled to the second input end of the differential amplifier;
an integrating capacitor having a first end and a second end, the first end of the integrating capacitor being coupled to the second input end of the differential amplifier, and the second end of the integrating capacitor being coupled to the output end of the differential amplifier; and
a sixth switch having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth switch being coupled to the first terminal of the integrating capacitor, and the second terminal of the sixth switch being coupled to the second terminal of the integrating capacitor, the control terminal of the sixth switch being configured to receive a reset control signal.
8. The capacitive sensing circuit of claim 1, further comprising:
a first offset capacitor having a first end and a second end; and
a first cancellation capacitance control circuit coupled to the first cancellation capacitance element and the first input terminal of the capacitance sensing circuit, for coupling the first terminal of the first cancellation capacitance element to the ground voltage and the second terminal of the first cancellation capacitance element to the operating voltage during the first period, and for coupling the first terminal of the first cancellation capacitance element to the first input terminal of the capacitance sensing circuit and the second terminal of the first cancellation capacitance element to the ground voltage during a fourth period between the second period and the third period.
9. The capacitive sensing circuit of any one of claims 1 to 8, further comprising:
a second input terminal coupled to a second capacitance sensing element of the touch panel, the second capacitance sensing element having a second inherent capacitance value;
a second charging circuit for providing the operating voltage to the second input terminal of the capacitance sensing circuit in a first period of time so that the second capacitance sensing element is charged to the operating voltage;
a second discharge circuit for synchronously discharging the second capacitive sensing element and the first capacitive sensing element during the second period; and
the second capacitance amplifying circuit is used for generating a second sensing voltage according to the reference voltage and the voltage of the second input end of the capacitance sensing circuit in the third period.
10. The capacitive sensing circuit of claim 9, wherein said second intrinsic capacitance value is greater than said first intrinsic capacitance value, and further comprising:
a second offset capacitor having a first end and a second end; and
a second offset capacitance control circuit coupled to the second offset capacitance element and the second input terminal of the capacitance sensing circuit, for coupling the first terminal of the second offset capacitance element to the ground voltage and the second terminal of the second offset capacitance element to the operating voltage during the first period, and for coupling the first terminal of the second offset capacitance element to the second input terminal of the capacitance sensing circuit and the second terminal of the second offset capacitance element to the ground voltage during a fourth period between the second period and the third period.
11. The capacitive sensing circuit of claim 10, wherein the second cancellation capacitance control circuit comprises:
a seventh switch having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh switch being coupled to the ground voltage, and the second terminal of the seventh switch being coupled to the first terminal of the second offset capacitor;
an eighth switch having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth switch being coupled to the second terminal of the second offset capacitor, and the second terminal of the eighth switch being coupled to the operating voltage;
a ninth switch having a first terminal, a second terminal, and a control terminal, the first terminal of the ninth switch being coupled to the second terminal of the second offset capacitor, and the second terminal of the ninth switch being coupled to the ground voltage; and
a tenth switch having a first end, a second end, and a control end, the first end of the tenth switch being coupled to the first end of the second offset capacitor, and the second end of the tenth switch being coupled to the second input end of the capacitance sensing circuit.
12. The capacitance sensing circuit of claim 10, wherein the capacitance value of the second cancellation capacitance element is the difference between the first intrinsic capacitance value and the second intrinsic capacitance value
Figure FDA0002973318720000071
And (4) doubling.
13. The capacitance sensing circuit of claim 12, wherein the second cancelling capacitance element comprises a variable capacitance or a capacitance array, wherein a capacitance value of the variable capacitance or the capacitance array is changeable by a control signal depending on the difference of the first intrinsic capacitance value and the second intrinsic capacitance value.
14. The capacitive sensing circuit of claim 1 wherein said first discharge circuit causes said first capacitive sensing element to discharge a target charge during said discharge time, said target charge being less than or equal to a product of a difference of said operating voltage minus said reference voltage and said first intrinsic capacitance value.
15. A chip, comprising:
a capacitance sensing circuit as claimed in any one of claims 1 to 14.
16. The chip of claim 15, further comprising:
and the controller is used for judging the touch event on the touch panel according to the sensing voltages.
17. A touch device, comprising:
the capacitive sensing circuit of any one of claims 1 to 14;
the touch panel; and
and the controller is used for judging the touch event on the touch panel according to the sensing voltages.
CN202110268896.1A 2021-03-12 2021-03-12 Capacitance sensing circuit, related chip and touch device Pending CN113126817A (en)

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