CN113114404B - Device and method for expanding universal eCPRI interface - Google Patents
Device and method for expanding universal eCPRI interface Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/0055—Synchronisation arrangements determining timing error of reception due to propagation delay
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W80/00—Wireless network protocols or protocol adaptations to wireless operation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W92/00—Interfaces specially adapted for wireless communication networks
Abstract
The invention discloses a general eCPRI interface expanding device and a method, wherein the method divides the data flow transmission direction into an uplink transmission direction and a downlink transmission direction, the uplink transmission direction is that a slave end transmits data to a master end, the downlink transmission direction is that the master end transmits data to the slave end, and aiming at the uplink transmission direction, firstly, multi-path data are arbitrated and prioritized, and a plurality of slave ports upload the data to the master port through internal RAM resources and arbitration logic in a time sharing way, and the input data are cached by utilizing the internal RAM resources of an FPGA; for the downlink transmission direction, the data is issued to a specific slave port or broadcast to a multi-slave port by analyzing the MAC address of the network packet destination. Aiming at the synchronous time service and time delay test function in the eCPRI protocol, the invention adopts hardware time stamp, device time delay compensation and SyncE means to ensure the accuracy of master-slave time service. The invention can realize the expansion function of the forwarding eCPRI interface, reduce the quantity of forwarding equipment and the upgrading cost, and increase the utilization rate and the transmission efficiency of the eCPRI interface of BBU equipment.
Description
Technical Field
The invention relates to the field of wireless communication, in particular to a general eCPRI interface expanding device and method.
Background
With the advent of the 5G age, the base station antenna Massive MIMO technology was applied and the carrier bandwidth was greatly expanded. The original CPRI interface bandwidth between BBU and RRU can not meet the requirement of the 5G age, and the upgrade version eCPRI interface is inoculated. Patent application document with application number of CN201710780967.X mentions that when designing a general main controller, each manufacturer does not reserve too many of the size of the controller and the number of interfaces in consideration of cost, product volume, subsequent product planning, etc.
The solution of the eCPRI protocol is to reduce the forward rate. Under the background that the data transmission of the communication protocol stack is coded layer by layer and the data quantity of the bottom layer is larger, the protocol stack is sunk to the RRU under the Low Phy function of the original BBU, so that the purpose of reducing the communication bandwidth between the BBU and the RRU is achieved. But at the same time increases the complexity of the RRU.
The eCPRI solves the problem of bandwidth bottleneck of the 5G base station forward communication, and is a trend of future forward communication interfaces.
However, there are few eCPRI devices on the market. There is no patent and equipment supporting eCPRI expansion and exchange, but there is a need for a practical application scenario. The eCPRI interfaces of BBU devices are limited and adding more eCPRI interfaces means higher implementation and device costs.
Disclosure of Invention
Based on the above, the invention aims to solve the technical problem of the expansion of the eCPRI interface.
In order to achieve the above purpose, the present invention provides a general eCPRI interface expanding device, which includes a device port;
the device port includes: a main end adopts a high-speed 50Gb/s bandwidth network port and is used for connecting BBU ports; the slave ends adopt 10Gb/s bandwidth network ports and are used for connecting RRU ports;
the internal assembly includes: the system comprises an FPGA chip, a power supply circuit, a clock circuit, an SFP28 connector and four SFP+ connectors, wherein the power supply circuit outputs power for the interface expanding device, the clock circuit provides a working clock for the FPGA, and the SFP28 connector and the SFP+ connectors are connected with a high-speed serial bidirectional receiving and transmitting interface of the FPGA chip.
The bandwidth of the BBU port is larger than 10Gb/s, and the bandwidth of the RRU port is smaller than or equal to 10Gb/s.
The time information of the eCPRI interface comprises PTP1588 Type data of Synchronization Plane and Message Type 5 unidirectional delay measurement data of a User Plane.
The Synchronization Plane has a time synchronization function, and the User Plane has a function of measuring the One-way delay of the Message Type 5 One-Way Delay Measurement.
The general eCPRI interface expansion device adopts a PTP1588 protocol, an eCPRI interface protocol and a SyncE synchronization function, and is used for counteracting time synchronization errors and delay measurement errors of BBU and RRU caused by transmission and processing of the expansion device.
Dividing a data flow transmission direction into an uplink transmission direction and a downlink transmission direction, wherein the uplink transmission direction is from a slave end to a master end, the downlink transmission direction is from the master end to the slave end, and the interface expansion method comprises the following steps:
for the uplink transmission direction, firstly, multi-path data are arbitrated, and priority ranking is carried out according to a rule set by people; the multiple slave ports upload data to the master port in a time-sharing manner through internal RAM resources and arbitration logic, and the input data are cached by utilizing the internal RAM resources of the FPGA;
for the downlink transmission direction, the data is distributed to a specific slave port or broadcast to a multi-slave port by analyzing the MAC address of the network packet destination.
The interface expanding method further comprises the following steps:
s1: performing PTP1588v2 protocol analysis and eCPRI protocol analysis on the data selected by the MAC address;
s2: splitting data into two types of time type and non-time type;
s3: the data after the shunting are respectively transmitted to time and data processing links;
s4: and performing time compensation on the time type transmission data.
The method for time compensating the time type transmission data comprises the following steps:
s41: the expansion device analyzes the eCPRI protocol and extracts a time information field of a time type from each port network packet;
s42: the Ethernet IPcore of the FPGA is utilized to have a hardware time stamping function, and the time when a time information packet enters and outputs the device is captured;
s43: calculating the time difference between two moments by utilizing the time information field analyzed by the retention delay correction, and replacing the time information field of the original time packet text with a compensated new time packet text segment;
s44: and aligning the corrected time type data with the non-time type data, and merging and outputting the time type data and the non-time type data.
And calculating the time length of the information packet entering and exiting the device by using an FPGA internal counter, wherein the calculation accuracy is determined by the driving clock frequency of the FPGA logic function.
The beneficial effects of this application:
1. the expansion function of the forwarding eCPRI interface can be realized, and the quantity of forwarding equipment and the upgrading cost are reduced;
2. the utilization rate of the eCPRI interface of BBU equipment can be increased, and the transmission efficiency of the eCPRI interface is increased;
3. synchronization and delay measurement errors among the forwarding devices caused by expanding the devices can be compensated;
4. the invention has strong universality and compatibility and accords with eCPRI standard protocol;
5. the invention has flexible design, is realized by adopting the FPGA, and can flexibly support a plurality of port numbers according to scene requirements.
Drawings
Fig. 1 is an application schematic diagram of an eCPRI expanding device of the present invention;
fig. 2 is a schematic structural diagram of an eCPRI expanding device;
FIG. 3 is a schematic diagram of a delay compensation process;
FIG. 4 is a schematic view of the internal structure of the device;
the achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
For a clearer understanding of technical features, objects, and effects of the present invention, a specific embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in fig. 1 and fig. 2, in this embodiment, a general-purpose eCPRI interface expansion device is provided, which is implemented based on FPGA, and uses prefabricated 10Gb/s and 50/40Gb/s ethernet ipcore to implement a high-speed eCPRI interface. The device port is divided into a structure of 1 master end and a plurality of slave ends. The main end is a high-speed 50Gb/s bandwidth network port, the slave end is a slightly lower 10Gb/s bandwidth network port, meanwhile, the BBU port connected with the main end of the device is required to be more than 10Gb/s, and the RRU port bandwidth connected with the slave end of the device is less than or equal to 10Gb/s.
Specifically, as shown in fig. 4, the interface expanding device includes a device port and an internal component;
the device port includes: a main end adopts a high-speed 50Gb/s bandwidth network port and is used for connecting BBU ports; the slave ends adopt 10Gb/s bandwidth network ports and are used for connecting RRU ports;
the internal assembly includes: the system comprises an FPGA chip, a power supply circuit, a clock circuit, an SFP28 connector and four SFP+ connectors, wherein the power supply circuit outputs power for the interface expanding device, the clock circuit provides a working clock for the FPGA, and the SFP28 connector and the SFP+ connectors are connected with a high-speed serial bidirectional receiving and transmitting interface of the FPGA chip.
The data can be transmitted by the master end with high bandwidth in a time sharing way and the data of a plurality of slave ends, but the total data bandwidth of the plurality of slave ends and a single master end is consistent in a period of time, and the conditions of insufficient transmission bandwidth and data overflow are avoided.
The data flow direction is divided into upstream and downstream. The downstream master distributes the data to a specific slave port or broadcasts the data to a multi-slave port by resolving the destination MAC address of the network packet. And the uplink multi-slave terminal uploads the data to the master port in a time sharing way through the internal Ram resource and the arbitration logic.
Besides the expansion on the data link, the eCPRI protocol Synchronization Plane has a time synchronization function, and the User Plane has a function of measuring the One-way delay of the Message Type 5 One-Way Delay Measurement. The eCPRI interface expansion device needs to compensate the time delay amount of the data packet caused by processing and transmission in the expansion device.
The expansion device analyzes the eCPRI protocol and extracts the time information fields of the two time types from each port network packet. Meanwhile, the Ethernet IPcore of the FPGA is utilized to have a hardware time stamping function, the time when the time information packet enters and exits the device is captured with high precision, the time difference between the two times is calculated, and the time information field of the original time packet is replaced by a new time packet field after compensation. According to the PTP1588 protocol and the eCPRI protocol, the method can offset time synchronization errors and delay measurement errors of BBU and RRU caused by transmission and processing of an expanding device.
Specifically, in this embodiment, as shown in fig. 3, the eCPRI interface of the forwarding scenario is extended, and in particular, the BBUeCPRI interface is extended. The data flow direction is divided into an uplink and a downlink, and the transmission data type is divided into a time type and a non-time type.
Firstly, a data exchange mode between a master terminal and a plurality of slave terminals is described:
for the downlink transmission direction, i.e. the master sends to the slave. By resolving the data frame header MAC address, routing information can be obtained from which slave port the data should be output, and the data may be end-to-end or broadcast data.
In the uplink direction, multiple paths of slave-end data can be uploaded at the same time, and multiple paths of data need to be arbitrated and ordered. The priority ranking is performed according to manually set rules, such as chronological, data type, or port priority. The high priority data is output first, and the low priority data is output later. And caching the output data by utilizing RAM resources in the FPGA.
The eCPRI interface protocol is based on the Ethernet protocol, and the basic operation particles of uplink data arbitration and sequencing are an Ethernet packet.
The time compensation mode of the time type transmission data is then described:
the method is described by a time delay compensation structure of a single slave end; the data with the downlink direction selected by the MAC address is subjected to PTP1588v2 protocol analysis and eCPRI protocol analysis, and the data is split into two types, namely a non-time type. And outputting the split data to a time and data processing link respectively. The non-time type data is not processed at all. The time type data needs to analyze the time information field, records the retention time delay of the information packet entering and exiting the expansion device, and corrects the analyzed time information field by using the retention time delay. And finally, aligning the corrected time type data with the non-time type data, and merging and outputting the corrected time type data to the slave end.
The time information of the eCPRI interface comprises two data types of PTP1588 Type data of Synchronization Plane and Message Type 5 unidirectional delay measurement data of a User Plane.
The retention time delay calculation mode uses the Ethernet IPcore hardware time stamping function of the FPGA to capture the time of entering and exiting the device of the time information packet with high precision, and uses an internal counter of the FPGA to calculate the time of entering and exiting the device of the data packet. The calculation precision is determined along with the driving clock frequency of the logic function of the FPGA, and the time compensation precision of the theoretical device is +/-2 ns under the clock condition of 500 MHz.
The time information field replacement mode replaces the characteristic that the time stamping point of the network packet entering and exiting the Ethernet MAC is prior to the time information field, and the replacement function of the data segment is realized by utilizing the time difference of the output and the input.
It should be noted that the uplink time compensation mode is consistent with the downlink.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (5)
1. The universal eCPRI interface expanding device is characterized by comprising a device port and an internal component;
the device port includes: a main end adopts a high-speed 50Gb/s bandwidth network port and is used for connecting BBU ports; the slave terminals adopt a 10Gb/s bandwidth network port and are used for connecting the RRU port, the master terminal transmits data with the data of the slave terminals in a high-bandwidth time-sharing manner, and the total data bandwidth of the slave terminals is consistent with that of the single master terminal in a period of time; the data flow direction is divided into an uplink direction and a downlink direction, the main end of the downlink direction distributes data to a specific slave port or broadcasts the data to a multi-slave port by analyzing the MAC address of the network packet, and the multi-slave end of the uplink direction uploads the data to the main port by internal Ram resources and arbitration logic in a time sharing way;
the internal assembly includes: the system comprises an FPGA chip, a power supply circuit, a clock circuit, an SFP28 connector and four SFP+ connectors, wherein the power supply circuit outputs power for an interface expanding device, the clock circuit provides a working clock for the FPGA, and the SFP28 connector and the SFP+ connectors are connected with a high-speed serial bidirectional receiving and transmitting interface of the FPGA chip;
the time information of the eCPRI interface comprises PTP1588 Type data of Synchronization Plane and Message Type 5 unidirectional delay measurement data of User Plane, wherein Synchronization Plane has a time synchronization function, the User Plane has the function of Message Type 5 One-Way Delay Measurement unidirectional delay measurement, and the eCPRI interface expansion device compensates the time delay amount caused by processing and transmitting a data packet in the expansion device;
the general eCPRI interface expanding device adopts a PTP1588 protocol, an eCPRI interface protocol and a SyncE synchronization function and is used for counteracting time synchronization errors and delay measurement errors of BBU and RRU caused by transmission and processing of the expanding device;
the general eCPRI interface expanding device analyzes the eCPRI protocol, extracts time information fields of two time types of BBU and RRU from each port network packet, utilizes the Ethernet IPcore of the FPGA to have a hardware time stamping function, captures the time when the time information packet enters and exits the device with high precision, calculates the time difference value of the two time, replaces the time information field of the original time packet with a new compensated time packet field, and counteracts the time synchronization error and delay measurement error of the BBU and the RRU caused by transmission and processing of the expanding device according to the PTP1588 protocol and the eCPRI protocol.
2. The universal eCPRI interface extension apparatus of claim 1, wherein the BBU port bandwidth is greater than 10Gb/s and the RRU port bandwidth is less than or equal to 10Gb/s.
3. The general eCPRI interface expanding method, based on the general eCPRI interface expanding device according to any of claims 1-2, is characterized in that the data flow transmission direction is divided into an uplink transmission direction and a downlink transmission direction, the uplink transmission direction is that data is sent from a slave end to a master end, the downlink transmission direction is that the master end sends data to the slave end, the interface expanding method includes:
for the uplink transmission direction, firstly, multi-path data are arbitrated, and priority ranking is carried out according to a rule set by people; the multiple slave ports upload data to the master port in a time-sharing manner through internal RAM resources and arbitration logic, and the input data are cached by utilizing the internal RAM resources of the FPGA;
for the downlink transmission direction, the data is distributed to a specific slave port or broadcast to a multi-slave port by analyzing the MAC address of the network packet destination;
further comprises:
s1: performing PTP1588v2 protocol analysis and eCPRI protocol analysis on the data selected by the MAC address;
s2: splitting data into two types of time type and non-time type;
s3: the data after the shunting are respectively transmitted to time and data processing links;
s4: and performing time compensation processing on the time type transmission data.
4. The method for expanding a generic eCPRI interface of claim 3, wherein the method for time compensating the time-type transmission data comprises:
s41: the expansion device analyzes the eCPRI protocol and extracts a time information field of a time type from each port network packet;
s42: the Ethernet IPcore of the FPGA is utilized to have a hardware time stamping function, and the time when a time information packet enters and outputs the device is captured;
s43: calculating the time difference between two moments by utilizing the time information field analyzed by the retention delay correction, and replacing the time information field of the original time packet text with a compensated new time packet text segment;
s44: and aligning the corrected time type data with the non-time type data, and merging and outputting the time type data and the non-time type data.
5. The universal eCPRI interface extension method of claim 4, further comprising: and calculating the time length of the time information packet entering and exiting the device by using an FPGA internal counter, wherein the calculation accuracy is determined by the driving clock frequency of the FPGA logic function.
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| CN114143384B (en) * | 2022-01-14 | 2024-04-12 | 深圳市佳贤通信科技股份有限公司 | CPRI and ECPRI protocol data fusion transmission method |
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