CN113114273A - Check matrix extraction method, system and equipment of LDPC code - Google Patents
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- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract
The invention provides a check matrix extraction method, a check matrix extraction system, check matrix extraction equipment and a check matrix extraction storage medium of LDPC codes, wherein the check matrix extraction method comprises the following steps: dividing the collected serial data into two paths of I/Q paths, and respectively carrying out frame header detection through a register; after detecting the frame header, clearing a first counter, counting the number of bits in a block, and when the first counter is N-1, automatically increasing 1 by a second counter until the second counter is M; marking the serial numbers of the M blocks counted by the second counter, carrying out XOR operation on the marked P block and the marked P +1 block, and simultaneously carrying out XOR operation on the 1 st block and the M block shifted by one bit from the right; and combining all the check equations subjected to the XOR operation to obtain a check matrix. The check matrix is mainly used for calculating the check equation during LDPC parallel iterative decoding, the information of the check equation is stored in the check matrix of the LDPC code, the generated matrix is the basis of encoding during encoding, and the check matrix is also the basis of calculating the check equation during decoding.
Description
Technical Field
The invention belongs to the technical field of error correcting codes, and particularly relates to a method, a system, equipment and a storage medium for extracting a check matrix of an LDPC code.
Background
In the process of transmission, binary data usually encounters some noises or interferences, so that errors occur during reception, and in wireless transmission, these electronic noises are usually unavoidable, and if data errors occur during reception, one way is that we can refuse reception and request the other party to retransmit, but in many cases, data is transmitted in real time, and the above operations are not allowed; error correcting codes have been developed for this purpose, and in communication systems, forward error correcting codes are generally used to detect and correct error codes, and LDPC (low density parity check code) is a block code.
When data is transmitted, a forward error correction code is added with bits according to a certain algorithm, the bits are redundant for the data, the receiver can judge whether the transmitted data is logic "1" or logic "0" according to the received data and redundant check bits, or the receiver can give a probability for indicating the probability size that the data is logic "1" or logic "0", and the data is soft-decision data. The decoding process typically uses maximum likelihood to obtain a guess that is closest to the originally transmitted data. At present, there are many forward error correction codes widely used, such as convolutional codes, RS codes, turbo codes. LDPC is a block code that has been developed rapidly recently and is recognized by a plurality of transmission protocols, and its general decoding algorithm is sum-Product Rule (sum-Product algorithm). According to the principle of the sum-product algorithm, people develop an approximate algorithm, namely an iterative algorithm, which can be realized by a hardware circuit, but the existing method has the problems of high complexity, large resource occupation, low efficiency and low speed in the realization, thereby hindering the wide application of the LDPC.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the problems in the prior art, a check matrix is provided for calculating a check equation when the check matrix is used for LDPC parallel iterative decoding, the information of the check equation is stored in the check matrix of the LDPC code, the generated matrix is the basis of encoding when encoding, and the check matrix is also the basis of calculating the check equation when decoding.
In order to solve the technical problems, the invention adopts the technical scheme that:
in a first aspect, the present invention provides a method for extracting a check matrix of an LDPC code, where the LDPC code includes M information blocks and M check blocks, each of the check blocks and the information blocks includes N bits, where M, N are positive integers greater than 0, and the method includes:
dividing the collected serial data into two paths of I/Q paths, and respectively carrying out frame header detection through a register;
after detecting the frame header, clearing a first counter, counting the number of bits in a block, and when the first counter is N-1, automatically increasing 1 by a second counter until the second counter is M;
marking the serial numbers of the M blocks counted by the second counter, carrying out XOR operation on the marked P block and the P +1 block, and carrying out XOR operation on the 1 st block and the M block shifted by one bit from the right, wherein P is a positive integer greater than or equal to 1 and less than or equal to M-1;
and combining all the check equations subjected to the XOR operation to obtain a check matrix.
In a second aspect, the present invention further provides a check matrix extraction system for an LDPC code, where the LDPC code includes M information blocks and M check blocks, each of the check blocks and the information block includes N bits, where M, N are positive integers greater than 0, and the system includes:
a detection module: the device is used for dividing the collected serial data into two paths of I/Q paths and respectively carrying out frame head detection through a register;
a counting module: the first counter is cleared after the frame header is detected, the number of bits in the block is counted, and when the first counter is N-1, the second counter automatically increments by 1 until the second counter is M;
a calculation module: the M blocks are used for marking serial numbers of the M blocks counted by the second counter, the marked P block and the P +1 block are subjected to XOR operation, and the 1 st block and the M block shifted to the right by one bit are subjected to XOR operation at the same time, wherein P is a positive integer which is greater than or equal to 1 and less than or equal to M-1;
combining the modules: and the check equations after the exclusive or operation are combined to obtain a check matrix.
In a third aspect, the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the processor implements the steps of the method for extracting a check matrix of an LDPC code according to the first aspect.
In a fourth aspect, the present invention also provides a storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the method for extracting a check matrix of an LDPC code according to the first aspect.
The invention provides a check matrix extraction method of an LDPC code, wherein the LDPC code comprises M information blocks and M check blocks, each check block and each information block comprise N bits, wherein M, N are positive integers greater than 0, and the method comprises the following steps: dividing the collected serial data into two paths of I/Q paths, and respectively carrying out frame header detection through a register; after detecting the frame header, clearing a first counter, counting the number of bits in a block, and when the first counter is N-1, automatically increasing 1 by a second counter until the second counter is M; marking the serial numbers of the M blocks counted by the second counter, carrying out XOR operation on the marked P block and the P +1 block, and carrying out XOR operation on the 1 st block and the M block shifted by one bit from the right, wherein P is a positive integer greater than or equal to 1 and less than or equal to M-1; and combining all the check equations subjected to the XOR operation to obtain a check matrix. The check matrix can determine whether decoding is correct according to the influence of each received bit in the check equation, and because the generated matrix used by the LDPC coding is characterized by a sparse matrix, the performance of errors of the received bits in the check equation can be deduced to be very characteristic, comprehensive judgment and decoding can be carried out according to the characteristics, and the final correct decoding can be obtained through repeated iteration; the check matrix is mainly used for calculating the check equation during LDPC parallel iterative decoding, the information of the check equation is stored in the check matrix of the LDPC code, the generated matrix is the basis of encoding during encoding, and the check matrix is also the basis of calculating the check equation during decoding.
Drawings
The detailed structure of the invention is described in detail below with reference to the accompanying drawings
FIG. 1 is a flow chart of the LDPC code check matrix extraction method of the present invention;
FIG. 2 is a sub-flow diagram of the LDPC code check matrix extraction method of the present invention;
FIG. 3 is a schematic view of another sub-flow of the LDPC code extraction method of the present invention;
FIG. 4 is a schematic diagram of a program module of the LDPC code check matrix extraction system of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic flow chart of a check matrix extraction method of an LDPC code in an embodiment of the present application, in the check matrix extraction method of the LDPC code in the present embodiment, the LDPC code includes M information blocks and M check blocks, each of the check blocks and the information blocks includes N bits, where M, N is a positive integer greater than 0, and the method includes:
In this embodiment, the I/Q is two parallel paths, the collected serial data is divided into two paths, the input serial data is detected by the register, and the frame header in the serial data is detected by comparing the input serial data with the extracted frame header, where the bit number of the frame header is fixed.
And 102, after the frame header is detected, clearing a first counter, counting the number of bits in a block, and when the first counter is N-1, automatically increasing 1 by a second counter until the second counter is M.
In this embodiment, after detecting the frame header, marking the detected frame header, outputting a frame header indication signal, and after detecting the frame header, clearing the first counter, starting counting, and counting the number of bits in the information block and the check block, wherein the counting is performed under the condition that the enabling is valid; whether the logic inside the block is 1 or 0, counting is performed, and after the first counter finishes counting the internal bit number of each block, the second counter increments by 1, wherein the bit number inside the block is fixed, and the block number is also fixed until the second counter is full of all the blocks.
103, marking serial numbers of M blocks counted by the second counter, performing exclusive-or operation on the marked P block and the P +1 block, and performing exclusive-or operation on the 1 st block and the M block shifted to the right by one bit, wherein P is a positive integer greater than or equal to 1 and less than or equal to M-1.
In this embodiment, after the second counter counts all the blocks, and after each block is also marked with a serial number, the M check blocks are subjected to xor operation on the front and rear two groups by using the block as a unit (N bits are used as one block to make the difference between adjacent blocks, i.e., the bit interval difference), and when the front and rear two groups are subjected to xor operation, a group of check equations needs to be additionally extracted, that is, the first block of the check block is extracted first, then the last block of the check block (i.e., the mth block) is extracted, and after the last block is shifted right by one bit, the xor operation is performed to obtain the check equation.
And step 104, combining all the check equations subjected to the exclusive or operation to obtain a check matrix.
In this embodiment, a plurality of check equations obtained by performing xor operation on two groups of previous and next check blocks in the M check blocks by using the block as a unit, and additionally extracted check equations are sorted and combined to obtain a finally extracted check matrix.
The embodiment of the application provides a check matrix extraction method of an LDPC code, the LDPC code comprises M information blocks and M check blocks, each check block and information block comprises N bits, wherein M, N is positive integers greater than 0, and the method comprises the following steps: dividing the collected serial data into two paths of I/Q paths, and respectively carrying out frame header detection through a register; after detecting the frame header, clearing a first counter, counting the number of bits in a block, and when the first counter is N-1, automatically increasing 1 by a second counter until the second counter is M; marking the serial numbers of the M blocks counted by the second counter, carrying out XOR operation on the marked P block and the P +1 block, and carrying out XOR operation on the 1 st block and the M block shifted by one bit from the right, wherein P is a positive integer greater than or equal to 1 and less than or equal to M-1; and combining all the check equations subjected to the XOR operation to obtain a check matrix. The check matrix can determine whether decoding is correct according to the influence of each received bit in the check equation, and because the generated matrix used by the LDPC coding is characterized by a sparse matrix, the performance of errors of the received bits in the check equation can be deduced to be very characteristic, comprehensive judgment and decoding can be carried out according to the characteristics, and the final correct decoding can be obtained through repeated iteration; the check matrix is mainly used for calculating the check equation during LDPC parallel iterative decoding, the information of the check equation is stored in the check matrix of the LDPC code, the generated matrix is the basis of encoding during encoding, and the check matrix is also the basis of calculating the check equation during decoding.
Further, marking the serial numbers of the M blocks counted by the second counter, performing an exclusive or operation on the marked P-th block and the P + 1-th block, and performing an exclusive or operation on the 1-th block and the M-th block shifted by one bit from the right further includes:
and recording the position of the data with the bit of 1 in each check block and each information block and the sequence number of the blocks, and calculating the relative offset value.
In this embodiment, the block number and the position of the data with the bit number of 1 in the information block and the check block are found, the position with the bit number of 1 is in 0-N-1, and after the block number and the position are found and recorded, a relative offset value can be calculated, where the relative offset value is an offset value of the check bit relative to the information bit, that is, a numerical value of a corresponding position element in the check matrix, which is a numerical value obtained by the foregoing method, and the numerical value is shifted, checked and corrected according to the position information and the offset value given by the check matrix when decoding. When extracting the check matrix, in order to analyze the corresponding relation between the information bits and the check bits, writing a special data source, wherein the data source coding rule is as follows: only 1bit of 1 ' data is contained in the information length of one frame, and other bits are all ' 0 ', so that the corresponding relation between the information bits and the check bits can be found more easily.
In this embodiment, when software simulation is used, which number of check blocks related to bit 1 in an information block is found out, and when simulation is performed, two different (different by 1 bit) check blocks in front and back adjacent check blocks need to be found out, which indicates that bit 1 in the information block (the information block in which the bit 1 is located) participates in the check equation of the two check blocks.
Further, the number of the information blocks is the same as the number of the check blocks.
In this embodiment, the most typical coding rate is analyzed in the embodiments of the present application, and the number of parity blocks is the same as that of information blocks, and is generally the number of statistical information blocks when performing statistics.
Further, referring to fig. 2, fig. 2 is a schematic sub-flow diagram of a check matrix extraction method of an LDPC code in the embodiment of the present application, where after detecting the frame header, clearing a first counter, and counting a number of bits in a block, and when the first counter is N-1, a second counter automatically increments by 1 until the second counter is M, including:
In this embodiment, since the first counter is cleared when starting to count, and the fixed number of bits of each block is N, the first counter should be N-1 when it is full, the first counter is cleared when it is full, another block is counted, and the first counter should continue to count when it is not full. For example, if N is 240, the first counter is counted as 222, but not 239, the first counter should be counted as 223, and if the first counter counts 240 bits from 0 to 239, the first counter should be cleared and another block should be counted again.
Further, after detecting the frame header, clearing the first counter, and counting the number of bits in the block, and when the first counter is N-1, automatically incrementing by 1 by the second counter until the second counter is M, further comprising:
and when the frame header is detected, assigning the value of the second counter to be 1.
In this embodiment, after detecting the frame header, the first counter starts counting, where a certain block is already being counted, so the second counter is assigned to 1.
Further, referring to fig. 3, fig. 3 is another sub-flow diagram of the method for extracting a check matrix of an LDPC code in this embodiment, where after the frame header is detected, the first counter is cleared, the number of bits in the block is counted, and when the first counter is N-1, the second counter automatically increments by 1 until the second counter is M, the method further includes:
In this embodiment, since the second counter is assigned to 1 when starting to count, and the fixed block number is M, the second counter should be M after counting, the second counter is assigned to 1 when counting all the blocks, and then counting is resumed, and when the second counter does not count all the blocks, counting should be continued. For example, when N is 40, the second counter counts 30, but not 40, and the second counter should count 31, and if the second counter counts 40 blocks from 1 to 40, the value of 1 should be assigned and counting should be resumed.
Further, after detecting the frame header, clearing the first counter, and counting the number of bits in the block includes:
and outputting a frame header indicating signal when the frame header is detected, wherein the frame header indicating signal generates an enabling signal, the corresponding enabling of the frame header is invalid, and the corresponding enabling of the information bit and the check bit is valid.
In the present embodiment, the number of blocks and the number of blocks are counted only when the enable is enabled, and the enable signal is generated by the frame header indication signal.
In this embodiment, the process of performing two sets of xor operations on the parity bits in a block unit (taking N bits as a block to make the difference between adjacent blocks, i.e. the bit interval difference) is as follows:
......
wherein, P0Extracting a group of check equations in addition, namely extracting a first block of a check block, then extracting a last block (namely an Mth block) of the check block, simultaneously shifting the last block by one bit to the right, then carrying out XOR operation to obtain the check equation, and taking P as the reference value0～PM-1The M check equations are combined to obtain the requirementAnd (5) extracting the check matrix.
Further, an embodiment of the present application further provides a check matrix extraction system 400 of an LDPC code, referring to fig. 4, fig. 4 is a schematic diagram of program modules of the check matrix extraction system 400 of the LDPC code in the embodiment of the present application, and in this embodiment, the check matrix extraction system 400 of the LDPC code includes:
the detection module 401: the device is used for dividing the collected serial data into two paths of I/Q paths and respectively carrying out frame head detection through a register;
the counting module 402: the first counter is cleared after the frame header is detected, the number of bits in the block is counted, and when the first counter is N-1, the second counter automatically increments by 1 until the second counter is M;
the calculation module 403: the M blocks are used for marking serial numbers of the M blocks counted by the second counter, the marked P block and the P +1 block are subjected to XOR operation, and the 1 st block and the M block shifted to the right by one bit are subjected to XOR operation at the same time, wherein P is a positive integer which is greater than or equal to 1 and less than or equal to M-1;
the combination module 404: and the check equations after the exclusive or operation are combined to obtain a check matrix.
The check matrix extraction system 400 of the LDPC code provided in the embodiment of the present application, the LDPC code includes M information blocks and M check blocks, each of the check blocks and the information blocks includes N bits, where M, N are positive integers greater than 0, and the method includes: dividing the collected serial data into two paths of I/Q paths, and respectively carrying out frame header detection through a register; after detecting the frame header, clearing a first counter, counting the number of bits in a block, and when the first counter is N-1, automatically increasing 1 by a second counter until the second counter is M; marking the serial numbers of the M blocks counted by the second counter, carrying out XOR operation on the marked P block and the P +1 block, and carrying out XOR operation on the 1 st block and the M block shifted by one bit from the right, wherein P is a positive integer greater than or equal to 1 and less than or equal to M-1; and combining all the check equations subjected to the XOR operation to obtain a check matrix. The check matrix can determine whether decoding is correct according to the influence of each received bit in the check equation, and because the generated matrix used by the LDPC coding is characterized by a sparse matrix, the performance of errors of the received bits in the check equation can be deduced to be very characteristic, comprehensive judgment and decoding can be carried out according to the characteristics, and the final correct decoding can be obtained through repeated iteration; the check matrix is mainly used for calculating the check equation during LDPC parallel iterative decoding, the information of the check equation is stored in the check matrix of the LDPC code, the generated matrix is the basis of encoding during encoding, and the check matrix is also the basis of calculating the check equation during decoding.
Further, the present application also provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the processor implements the steps in the check matrix extraction method of the LDPC code.
Further, the present application also provides a storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps in the check matrix extraction method of the LDPC code as described above.
Each functional module in the embodiments of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the above description, for those skilled in the art, according to the idea of the embodiment of the present application, there are variations in the specific implementation and application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A check matrix extraction method of an LDPC code, wherein the LDPC code comprises M information blocks and M check blocks, each check block and information block comprises N bits, wherein M, N is a positive integer greater than 0, and the method comprises:
dividing the collected serial data into two paths of I/Q paths, and respectively carrying out frame header detection through a register;
after detecting the frame header, clearing a first counter, counting the number of bits in a block, and when the first counter is N-1, automatically increasing 1 by a second counter until the second counter is M;
marking the serial numbers of the M blocks counted by the second counter, carrying out XOR operation on the marked P block and the P +1 block, and carrying out XOR operation on the 1 st block and the M block shifted by one bit from the right, wherein P is a positive integer greater than or equal to 1 and less than or equal to M-1;
and combining all the check equations subjected to the XOR operation to obtain a check matrix.
2. The method of claim 1, wherein the marking the M blocks counted by the second counter with serial numbers, xoring the marked pth block with the P +1 th block, and xoring the 1 st block with the mth block shifted to the right by one bit further comprises:
and recording the position of the data with the bit of 1 in each check block and each information block and the sequence number of the blocks, and calculating the relative offset value.
3. The method of claim 2, wherein the number of blocks of the information block is the same as the number of blocks of the parity block.
4. The method according to claim 1, wherein the clearing a first counter and counting the number of bits inside a block after detecting the frame header, and the automatically incrementing a second counter by 1 until the second counter is M when the first counter is N-1 comprises:
when the first counter is N-1, clearing the first counter;
when the first counter is not N-1, then the first counter is automatically incremented by 1.
5. The method according to claim 1, wherein the clearing the first counter and counting the number of bits inside the block after detecting the frame header, and the automatically incrementing the second counter by 1 until the second counter is M when the first counter is N-1 further comprises:
and when the frame header is detected, assigning the value of the second counter to be 1.
6. The method according to claim 1, wherein the clearing the first counter and counting the number of bits inside the block after detecting the frame header, and the automatically incrementing the second counter by 1 until the second counter is M when the first counter is N-1 further comprises:
when the second counter is M, the second counter is assigned to be 1;
when the second counter is not M, the second counter is automatically incremented by 1.
7. The method of claim 1, wherein the detecting the frame header, clearing a first counter, and counting a number of bits within a block comprises:
and outputting a frame header indicating signal when the frame header is detected, wherein the frame header indicating signal generates an enabling signal, the corresponding enabling of the frame header is invalid, and the corresponding enabling of the information bit and the check bit is valid.
8. A check matrix extraction system of an LDPC code, wherein the LDPC code includes M information blocks and M check blocks, each of the check blocks and the information blocks includes N bits, and M, N is a positive integer greater than 0, and the system includes:
a detection module: the device is used for dividing the collected serial data into two paths of I/Q paths and respectively carrying out frame head detection through a register;
a counting module: the first counter is cleared after the frame header is detected, the number of bits in the block is counted, and when the first counter is N-1, the second counter automatically increments by 1 until the second counter is M;
a calculation module: the M blocks are used for marking serial numbers of the M blocks counted by the second counter, the marked P block and the P +1 block are subjected to XOR operation, and the 1 st block and the M block shifted to the right by one bit are subjected to XOR operation at the same time, wherein P is a positive integer which is greater than or equal to 1 and less than or equal to M-1;
combining the modules: and the check equations after the exclusive or operation are combined to obtain a check matrix.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for extracting a check matrix of an LDPC code according to any one of claims 1 to 7 when executing the computer program.
10. A storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements the steps in the method for check matrix extraction of LDPC codes as claimed in any one of claims 1 to 7.
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