CN113114271A - Low density parity check coding apparatus and method - Google Patents
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Abstract
The application relates to the technical field of 5G, and particularly discloses a low-density parity check coding device and method. The device comprises: the remainder generation module is used for generating a remainder result of each matrix element in the check matrix on the lifting factor; the external storage module is used for storing the residue taking result generated by the residue generation module; the on-chip access control module is used for acquiring a surplus result at a preset moment; and the cyclic accumulation module is used for performing cyclic shift operation on the input data according to the residue taking result. Because the operation of taking the balance of each matrix element in the check matrix to the lifting factor is carried out by the off-chip remainder generation module in advance, when the cyclic accumulation module needs to carry out cyclic shift operation on input data, the balance taking result can be obtained only by an external storage module and an on-chip access control module through two-stage access, a large amount of resources and logics in the chip do not need to be consumed in the whole process, the condition of overall layout wiring congestion is avoided, the requirement of high processing speed is also considered, and the operation rate is improved.
Description
Technical Field
The invention relates to the technical field of 5G, in particular to a low-density parity check coding device and method.
Background
The LDPC (Low Density Parity Check Code) coding technology belongs to the popular coding technology in the fields of local area network and metropolitan area network, wired data service interface, mobile communication and the like.
The LDPC code is defined based on a check matrix, and the encoding and decoding processes of the LDPC code are based on the check matrix. In 5G LDPC coding, it is necessary to perform a remainder on a lifting factor for each element in a check matrix, and then perform a cyclic shift operation on input data using the remainder. However, on-chip memory resources are very valuable, the remainder fetching operation consumes valuable resources and requires more additional logic, resulting in congestion of the overall layout and routing and a reduction in the operation rate.
Disclosure of Invention
Based on this, it is necessary to provide a low density parity check encoding apparatus, method, electronic device, and computer-readable storage medium for solving the problems that in 5G LDPC encoding, an operation of taking a remainder for each element in a check matrix consumes on-chip resources and additional logic, causes congestion of overall layout and wiring, and reduces an operation rate.
A low density parity check encoding apparatus, the apparatus comprising:
the remainder generation module is used for generating a remainder result of each matrix element in the check matrix on the lifting factor;
the external storage module is connected with the remainder generation module and used for storing the remainder obtaining result generated by the remainder generation module;
the on-chip access control module is connected with the external storage module and is used for acquiring the remainder result at a preset moment;
and the cyclic accumulation module is connected with the on-chip access control module and is used for performing cyclic shift operation on input data according to the residue taking result.
In one embodiment, the number of the lifting factors is several, the remainder generation module is configured to generate several sets of remainder results of different lifting factors for each matrix element in the check matrix, and the remainder results of the same lifting factor for each matrix element in the check matrix are a set of remainder results.
In one embodiment, the result of the remainder of each matrix element for the lifting factor in the check matrix is a remainder table formed by a remainder obtained by the remainder of each matrix element for the lifting factor, and the row-column arrangement sequence of the remainder table corresponds to the row-column arrangement sequence of each matrix element in the check matrix.
In one embodiment, the external storage module comprises an external storage unit and a storage controller;
the external storage unit comprises a DDR and is used for storing the remainder result generated by the remainder generation module;
the storage controller is used for controlling the access of the external storage unit to the remainder result.
In one embodiment, the storage controller is configured to store the remainder result generated by the remainder generation module in the external storage unit at a boot time, and is further configured to fetch the remainder result corresponding to the updated lifting factor and stored in the on-chip access control module at a time when the lifting factor is updated.
In one embodiment, the on-chip access control module is configured to obtain a remainder result corresponding to an updated lifting factor from the external storage module at a time when the lifting factor is updated, and store the remainder result in the cyclic accumulation module in a preset manner, where the preset manner includes a row-by-row storage manner.
In one embodiment, the loop accumulation module is configured to loop left shift the input data n times, where n is the remainder value in the remainder table.
A low density parity check encoding method, the method comprising:
pre-generating a remainder result of each matrix element in the check matrix to the lifting factor;
at the starting time, storing the remainder result of each matrix element in the check matrix to the lifting factor into an external storage module;
at the moment of updating the lifting factor configuration, acquiring a remainder result corresponding to the updated lifting factor from an external storage module;
and performing cyclic shift operation on the input data according to the remainder result.
An electronic device comprising a memory storing a computer program and a processor implementing the low density parity check coding method as described above when the processor executes the computer program.
A computer readable storage medium having stored therein computer instructions which, when executed by a processor, implement a low density parity check encoding method as described above.
The low-density parity check coding device comprises a remainder generation module, an external storage module, an on-chip access control module and a cyclic accumulation module, wherein the remainder generation module is used for generating a remainder obtaining result of each matrix element in a check matrix on a lifting factor in advance, the external storage module is used for storing the remainder obtaining result generated by the remainder generation module, the on-chip access control module is used for obtaining the remainder obtaining result at a preset moment, and the cyclic accumulation module carries out cyclic shift operation on input data according to the remainder obtaining result. Because the operation of taking the balance of each matrix element in the check matrix to the lifting factor is carried out by the off-chip remainder generation module in advance, when the cyclic accumulation module needs to carry out cyclic shift operation on input data, the balance taking result can be obtained only by an external storage module and an on-chip access control module through two-stage access, a large amount of resources and logics in the chip do not need to be consumed in the whole process, the condition of overall layout wiring congestion is avoided, the requirement of high processing speed is also considered, and the operation rate is improved.
Drawings
Fig. 1 is a schematic structural diagram of an ldpc encoding apparatus according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of another embodiment of an ldpc encoding apparatus according to an embodiment of the present application;
fig. 3 illustrates a manner in which an external storage unit stores a check matrix HBG1 in the ldpc encoding apparatus according to an embodiment of the present application;
fig. 4 illustrates a manner in which an external storage unit stores a check matrix HBG2 in the ldpc encoding apparatus according to an embodiment of the present application;
FIG. 5 is a diagram illustrating a write-in manner of an on-chip access control module according to an exemplary embodiment;
fig. 6 is a flowchart of a low density parity check coding method according to a second embodiment of the present application;
fig. 7 is a schematic structural diagram of an electronic device according to a third embodiment of the present application.
Description of reference numerals:
100. a remainder generation module; 200. an external storage module; 210. an external storage unit; 220. a storage controller; 300. an on-chip access control module; 400. a cyclic accumulation module; 500. a memory; 600. a processor.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As described in the background art, both the encoding and decoding processes of the LDPC code are based on the check matrix, for example, in the encoding process, an operation of taking a remainder of a lifting factor needs to be performed on each matrix element in the check matrix, and then a cyclic shift operation is performed on the input byte data by using the remainder, and then since the memory resources in the chip are limited and precious, the operation of taking the remainder consumes a large amount of on-chip resources and a large amount of additional logic, which causes congestion of the overall layout and wiring, and reduces the operation rate.
To solve the above problems, the present application provides a low density parity check encoding apparatus, a method, an electronic device, and a computer-readable storage medium.
Example one
The embodiment of the application provides a low-density parity check coding device which is used for carrying out low-density parity check coding.
Referring to fig. 1, the low density parity check coding apparatus of the present embodiment includes a remainder generation module 100, an external storage module 200, an on-chip access control module 300, and a cyclic accumulation module 400.
The remainder generation module 100 is configured to generate a remainder result of each matrix element in the check matrix for the lifting factor; the external storage module 200 is connected to the remainder generation module 100, and is configured to store a remainder obtaining result generated by the remainder generation module 100; the on-chip access control module 300 is connected to the external storage module 200, and is configured to obtain the remainder result at a preset time; the cyclic accumulation module 400 is connected to the on-chip access control module 300, and configured to perform a cyclic shift operation on input data according to the remainder result.
The low-density parity check coding device provided by the embodiment, because the operation of taking the remainder of each matrix element to the lifting factor in the check matrix is performed by the remainder generation module 100 outside the chip in advance, when the cyclic accumulation module 400 needs to perform cyclic shift operation on input data, the remainder taking result can be obtained only by two-stage access through the external storage module 200 and the in-chip access control module 300, a large amount of resources and logics in the chip do not need to be consumed in the whole process, thereby avoiding the situation of overall layout wiring congestion, simultaneously considering the requirement of high processing speed, and improving the operation rate.
The remainder generation module 100 is disposed outside the chip, which is outside the integrated circuit of the chip, that is, the remainder generation module 100 is an external device independent of the chip, and does not occupy the internal resources of the chip. The external memory module 200 may also be disposed off-chip to save resources inside the chip. The chip adopted in the low density parity check coding device in the embodiment can select the FPGA, that is, the remainder generation module 100 and the external storage module 200 are arranged outside the FPGA, the on-chip access control module 300 is arranged inside the FPGA, and in the coding process, the remainder is acquired into the cyclic accumulation module through the two-stage access process of the external storage module 200 and the on-chip access control module 300, so that the cyclic accumulation module 400 performs cyclic shift operation according to the remainder, in the process, the remainder extraction operation is not required inside the FPGA, a large amount of resources are saved, and when cyclic shift is not required, the remainder generated in advance by the remainder generation module 100 does not occupy the on-chip resources of the FPGA.
In one embodiment, the lifting factors include a plurality of lifting factors, and the remainder generation module 100 is configured to generate a plurality of sets of remainder results of different lifting factors for each matrix element in the check matrix, where the remainder results of the same lifting factor for each matrix element in the check matrix are a set of remainder results.
Specifically, there may be several lifting factors, and in practical applications, there may be 51 lifting factors, which are assumed to include 2, 3, 5, 7, 9, 11, etc., and are not listed here. For the lifting factor 2, the remainder generation module 100 generates a remainder result of each matrix element in the check matrix for the lifting factor 2, and forms a group of remainder results; for the lifting factor 3, the remainder generation module 100 generates a remainder result of each matrix element in the check matrix for the lifting factor 3, and forms a set of remainder results; for the lifting factor 5, the remainder generation module 100 generates a remainder result of each matrix element in the check matrix for the lifting factor 5, and forms a group of remainder results; by analogy, for different lifting factors, the remainder generation module 100 generates the remainder results of the matrix elements in the check matrix for the different lifting factors in advance, and forms different sets of the remainder results corresponding to the different lifting factors.
The method and the device have the advantages that a plurality of groups of residue taking results are obtained in advance according to a plurality of different lifting factors, so that the subsequent process of quickly calling the residue taking results corresponding to the currently used lifting factors from the plurality of groups of residue taking results when the currently used lifting factors are determined is facilitated, and the coding efficiency is improved.
In one embodiment, the result of the remainder of each matrix element for the lifting factor in the check matrix is a remainder table formed by a remainder obtained by the remainder of each matrix element for the lifting factor, and the row-column arrangement sequence of the remainder table corresponds to the row-column arrangement sequence of each matrix element in the check matrix.
The elements in the check matrix are arranged in a matrix form, each matrix element performs a remainder operation on the lifting factors to obtain remainders, and finally the remainders with the same number as the matrix elements are obtained, one remainder corresponds to one matrix element, and the remainders form a remainder table according to the row-column arrangement sequence of the matrix elements, for example, the matrix elements in the 1 st row and the 1 st column in the check matrix, the remainders obtained by the remainder operation on the lifting factors are also located in the 1 st row and the 1 st column in the remainder table, the matrix elements in the 2 nd row and the 3 rd column in the check matrix, and the remainders obtained by the remainder operation on the lifting factors are also located in the 2 nd row and the 3 rd column in the remainder table.
In addition, the number of the check matrixes may be one or two or more. When a plurality of check matrixes are provided, the above-mentioned residue taking operation is carried out on each check matrix, so that the current check matrix and the lifting factor are determined during encoding, and the residue taking result corresponding to the current check matrix and the lifting factor can be quickly obtained.
The remainder generation module 100 is illustrated with one specific example:
the check matrix has two, respectively HBG1 and HBG2, HBG1 being a matrix of 46 rows and 26 columns with 46 x 26 matrix elements, and HBG2 being a matrix of 42 rows and 14 columns with 42 x 14 matrix elements. The lifting factor is 51.
46 × 26 matrix elements in the HBG1 are respectively subjected to remainder taking on 51 lifting factors to obtain 51 remainder tables, the remainder taking result of 46 × 26 matrix elements on the same lifting factor is a remainder table with 46 rows and 26 columns, and the arrangement sequence of the remainders in the remainder table corresponds to the arrangement sequence of the matrixes corresponding to the remainder tables.
42 × 14 matrix elements in the HBG2 are respectively subjected to remainder taking on 51 lifting factors to obtain 51 remainder tables, the remainder taking result of the 42 × 14 matrix elements on the same lifting factor is a remainder table with 42 rows and 14 columns, and the arrangement sequence of the remainders in the remainder table corresponds to the arrangement sequence of the matrixes corresponding to the remainder tables.
That is, a total of 102 remainder tables are generated by the remainder generation module 100 for being called by the following module.
In one embodiment, referring to fig. 2, the external storage module 200 includes an external storage unit 210 and a storage controller 220;
the external storage unit 210 includes a DDR for storing the remainder generation result generated by the remainder generation module 100;
the storage controller 220 is used for controlling the access of the external storage unit 210 to the remainder result.
The DDR is a storage unit externally hung on the FPGA chip, the storage space is large, and the remainder result generated by the remainder generation module 100 is stored by utilizing the advantage of the large DDR storage space. The memory controller 220 is used to control the access of the external memory unit 210 to the remainder result, that is, the memory controller 220 may be controlled by the FPGA chip to obtain the generated remainder result from the remainder generation module 100 at an appropriate time, and may also send the stored remainder result to the next-level access module, that is, the on-chip access control module 300, at an appropriate time. The memory controller 220 may be located inside the FPGA chip.
The data storage structure of the remainder result inside the DDR is explained by a specific example:
the check matrices are two, i.e., HBG1 and HBG2, fig. 3 is a storage manner of a remainder table corresponding to the check matrix HBG1, and fig. 4 is a storage manner of a remainder table corresponding to the check matrix HBG 2. In fig. 3 and 4, j denotes the column index of the check matrix, which has 26 columns for the check matrix HBG1, the column index being from 0 to 25; for the check matrix HBG2, which has 14 columns, the column numbers are from 0 to 13. In FIGS. 3 and 4, P denotes the remainder, the subscript consisting of 2 digits, the first digit representing the row number and the second digit representing the column number, e.g., P00Denotes the remainder, P, corresponding to the elements of row 0 and column 0450Indicating the remainder for the 45 row 0 column element correspondence.
In addition, since each remainder is 9 bits wide, in DDR access for compatibility with 32-bit AXI bus, each 32-bit data is divided into 2 16 bits, 2 remainders are stored, and zero padding is performed on the upper 7 bits of each 16 bits. For the check matrix HBG1, which corresponds to a lifting factor, there is a remainder table with 46 rows and 26 rows, each remainder table is 46 × 26/2 × 32/8 ═ 2392Byte, and 51 such remainder tables are stored corresponding to 51 lifting factors. For the check matrix HBG2, which corresponds to a lifting factor, there is a remainder table with 42 rows and 14 columns, but 4 rows 0 are added later for compatibility with the remainder table of HBG1, each remainder table is 46 × 14/2 × 32/8 ═ 1288Byte, and 51 such remainder tables are stored corresponding to 51 lifting factors.
In one embodiment, the memory controller 220 is configured to store the remainder result generated by the remainder generation module 100 into the external storage unit 210 at a power-on time, and further configured to fetch the remainder result corresponding to the updated lifting factor stored in the external storage unit 210 at a time of updating the lifting factor, and store the remainder result into the on-chip access control module 300.
That is, the memory controller 220 stores the remainder result generated by the remainder generation module 100 into the external memory unit 210 (i.e., the first-level memory space) at the time of booting for subsequent quick call. When the lifting factor is updated at each time slot, the remainder result corresponding to the updated lifting factor is retrieved from the remainder results in the external storage unit 210 and stored in the on-chip access control module 300 (i.e., the second-level storage space). The timeslot is a term of a 5G physical layer, and refers to a set of configured minimum time intervals, and data of each timeslot corresponds to a set of parameters, that is, each timeslot needs to update the lifting factor once. Assuming that the lifting factor of the current timeslot update is 2, the remainder table obtained by performing a remainder operation on the lifting factor 2by the current check matrix is fetched from the external storage unit 210.
Referring to fig. 2, the on-chip access control module 300 may include a BRAM, and the remainder result corresponding to the updated boost factor may be retrieved and stored in the BRAM.
Specifically, the manner of retrieving the remainder result corresponding to the updated lifting factor from the external storage unit 210 to the on-chip access control module 300 may be: the on-chip access control module 300 is provided with 26 × 46 registers of 9 bits, each clock takes out2 remainders from the DDR (since the data taken from the DDR by the FPGA goes through the AXI bus, the data bit width adopted by the AXI bus of the DDR interface is 32 bits, and as can be seen from the foregoing, the data of the 32 bits includes 2 remainders) and writes into the registers, and only effective remaining bits (i.e., data of 0 part of padding is removed) in the DDR are taken out. For the check matrix HBG1, 26 × 46/2 is 598 valid clocks, and for the check matrix HBG2, 14 × 46/2 is 322 valid clocks.
In one embodiment, the on-chip access control module 300 is configured to obtain a remainder result corresponding to an updated lifting factor from the external storage module 200 at a time of updating the lifting factor, and store the remainder result into the cyclic accumulation module 400 in a predetermined manner, where the predetermined manner includes a row-by-row storage manner.
For the description of the on-chip access control module 300 obtaining the remainder result corresponding to the updated lifting factor from the external storage module 200 at the time of updating the lifting factor, reference is made to the foregoing.
The on-chip access control module 300 may also take out the remainder result in a predetermined manner and send the remainder result to the cyclic accumulation module 400, in this embodiment, a row-by-row storage manner is selected. The method specifically comprises the following steps: taking the remainder table with the remainder result of 46 rows and 26 columns as an example, 46 remainder values can be taken out per clock, that is, a column of remainder values can be taken out simultaneously, so that parallel operation can be realized, and thus, 46 data can be simultaneously circularly shifted by the circular accumulation module 400 at the same time by using relatively cheap LUT resources to exchange a rate of 46 times. A total of 26 clocks are required to transmit 46 rows and 26 columns of the remainder table.
In one embodiment, the loop accumulation module 400 is configured to loop left shift the input data n times, where n is the remainder value in the remainder table.
In practical application, Zc (i.e. lifting factor) input bits need to be combined to be used as subsequent input data to be processed. From Zc, 46 Zc _ out may be converted, e.g. Zc _ out0, Zc _ out1, Zc _ out2 … Zc _ out 45. When the on-chip access control module 300 fetches the 46 remainder values in the first row in the first effective clock, the first cycle left shift operation may be performed on the 46 input data Zc _ out according to the 46 remainder values, and the number of cycle left shifts is the corresponding remainder value; and when the clock is valid for the second time, taking out 46 remainder values of the second column, continuously circularly and leftwards shifting 46 data obtained after the last circularly and leftwards shifting according to the 46 remainder values of the second column, and the like to realize the circularly shifting and accumulating operation of the input data. The number of the cyclic accumulation modules 400 can be 46, and one cyclic accumulation module 400 is responsible for a cyclic shift operation of input data.
The principle of the low density parity check coding apparatus is described below with reference to a specific example:
the lifting factor Zc configured in the upper layer is 4, and the verification matrix is HBG1, which is specifically implemented as follows:
at the time of starting up, 102 remainder tables generated by the remainder generation module 100 are stored in the DDR, and each remainder table corresponds to a base address and a storage length.
For example, at the start of the current time slot, the Zc of the upper layer software configuration is 4, and the check matrix selects HBG 1. The base address corresponding to the remainder table corresponding to the check matrix HBG1 with the lifting factor Zc of 4 is found first, and data with the length of 2392Byte is fetched from the base address by the memory controller 220.
26 × 46 registers of 9 bits are defined in advance in FPGA, and P is respectively00,P10,…,P440,P450,P01,P11,…,P4425,P4525. Writing 2 remainders into each clock, only taking effective bit in DDR, wherein the 1 st clock obtains P by adopting a mode of intercepting the effective bit00,P10Value of (A), P00For the lower 9 bits (P) of the input data00<＝tdata[8:0])，P10Is the lower 9 (P) of the upper 16 bits of the input data00<＝tdata[24:16]) (ii) a 2 nd clock gets P20,P30Value of (A), P20For the lower 9 bits (P) of the input data20<＝tdata[8:0])，P30Is the lower 9 (P) of the upper 16 bits of the input data30<＝tdata[24:16]) (ii) a And so on as shown in fig. 5. HBG1 requires 26 x 46/2 ═ 598 valid clocks.
Reading: the read clock rd _ clk is transmitted in 26 cycles, with 46 remainder elements transmitted per clock. Reading P at 1 st clock00,P10,…,P 4502 nd clock reading P01,P11,…,P451And so on, the last clock (26 th clock) reads the last 46 remainders P025,P125,…,P4525。
Example two
An embodiment of the present application provides a low density parity check coding method, and referring to fig. 6, the method includes the following steps:
s100, pre-generating a remainder result of each matrix element in the check matrix on the lifting factor;
step S300, storing the remainder result of each matrix element in the check matrix to the lifting factor into the external storage module 200 at the starting time;
step S500, at the moment of updating the lifting factor configuration, acquiring a remainder result corresponding to the updated lifting factor from the external storage module 200;
and S700, performing cyclic shift operation on the input data according to the remainder result.
Because the operation of taking the balance of the lifting factors by each matrix element in the check matrix is carried out outside the chip in advance, when the cyclic shift operation of input data is required, the balance taking result can be obtained only by two-stage access through the external storage module 200 and the on-chip access control module 300, a large amount of resources and logics in the chip are not required to be consumed in the whole process, the condition of overall layout and wiring congestion is avoided, the requirement of high processing speed is also considered, and the operation rate is improved.
The low density parity check coding method provided in this embodiment and the low density parity check coding apparatus provided in embodiment 1 belong to the same inventive concept, and for specific steps of the low density parity check coding method, reference may be made to the corresponding description in embodiment one, and details are not repeated here.
EXAMPLE III
The embodiment of the present application provides an electronic device, as shown in fig. 7, including a memory 500 and a processor 600, where the memory 500 and the processor 600 are communicatively connected with each other, and may be connected through a bus or in another manner, and fig. 7 takes the example of connection through a bus as an example.
The memory 500, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions corresponding to the low density parity check coding method in the embodiments of the present invention. The processor 600 executes various functional applications and data processing, i.e., a low density parity check coding method, of the processor 600 by executing non-transitory software programs, instructions, and modules stored in the memory 500.
The memory 500 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by the processor 600, and the like. Further, the memory 500 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 500 optionally includes memory located remotely from processor 600, which may be connected to the processor via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A low density parity check coding apparatus, the apparatus comprising:
the remainder generation module is used for generating a remainder result of each matrix element in the check matrix on the lifting factor;
the external storage module is connected with the remainder generation module and used for storing the remainder obtaining result generated by the remainder generation module;
the on-chip access control module is connected with the external storage module and is used for acquiring the remainder result at a preset moment;
and the cyclic accumulation module is connected with the on-chip access control module and is used for performing cyclic shift operation on input data according to the residue taking result.
2. The ldpc encoding apparatus as claimed in claim 1, wherein the lifting factors have a plurality, the remainder generation module is configured to generate a plurality of sets of results obtained by subtracting different lifting factors from each matrix element in the check matrix, and the results obtained by subtracting the same lifting factor from each matrix element in the check matrix are a set of results obtained by subtracting the same lifting factor from each matrix element.
3. The ldpc encoding apparatus according to claim 1, wherein the result of the complementation of the lifting factors by each matrix element in the check matrix is a remainder table formed by a remainder obtained by the complementation of the lifting factors by each matrix element, and a row-column arrangement order of the remainder table corresponds to a row-column arrangement order of each matrix element in the check matrix.
4. The low density parity check encoding apparatus of claim 1, wherein the external storage module comprises an external storage unit and a storage controller;
the external storage unit comprises a DDR and is used for storing the remainder result generated by the remainder generation module;
the storage controller is used for controlling the access of the external storage unit to the remainder result.
5. The ldpc encoding apparatus as claimed in claim 4, wherein the storage controller is configured to store the remainder obtaining result generated by the remainder generating module into the external storage unit at a power-on time, and further configured to retrieve the remainder obtaining result corresponding to the updated lifting factor stored in the external storage unit at a time when the lifting factor is updated, and store the remainder obtaining result into the on-chip access control module.
6. The LDPC encoding apparatus of claim 3, wherein the on-chip access control module is configured to obtain a remainder result corresponding to the updated lifting factor from the external storage module at a time of updating the lifting factor, and store the remainder result into the cyclic accumulation module in a predetermined manner, wherein the predetermined manner includes a row-by-row storage manner.
7. The ldpc encoding apparatus of claim 3 wherein the cyclic accumulation module is configured to cyclically left shift the input data n times, where n is a remainder value in the remainder table.
8. A low density parity check coding method, the method comprising:
pre-generating a remainder result of each matrix element in the check matrix to the lifting factor;
at the starting time, storing the remainder result of each matrix element in the check matrix to the lifting factor into an external storage module;
at the moment of updating the lifting factor configuration, acquiring a remainder result corresponding to the updated lifting factor from an external storage module;
and performing cyclic shift operation on the input data according to the remainder result.
9. An electronic device comprising a memory and a processor, the memory storing a computer program, wherein the processor implements the low density parity check encoding method of claim 8 when executing the computer program.
10. A computer-readable storage medium having stored thereon computer instructions which, when executed by a processor, implement the low density parity check encoding method of claim 8.
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