CN113114176A

CN113114176A - Delay unit

Info

Publication number: CN113114176A
Application number: CN202110490607.2A
Authority: CN
Inventors: 陈培炜; 陈宪谷
Original assignee: Lianen Microelectronics Co ltd
Current assignee: Lianen Microelectronics Co ltd
Priority date: 2020-05-04
Filing date: 2021-05-06
Publication date: 2021-07-13
Anticipated expiration: 2041-05-06
Also published as: CN113114176B; TW202143644A

Abstract

The invention provides a delay unit. The first input transistor is coupled between a power supply and a first output end, and is provided with a control end for receiving a first input signal. The second input transistor is coupled between the power supply and a second output end, and is provided with a control end for receiving a second input signal. The first mirror transistor is coupled between a variable current source and a ground terminal, and has a control terminal coupled to the variable current source. The second mirror transistor is coupled between the first output terminal and the ground terminal, and has a control terminal coupled to the variable current source. The third mirror transistor is coupled between the second output terminal and the ground terminal, and has a control terminal coupled to the variable current source. The variable capacitor is coupled between the first output end and the second output end.

Description

Delay unit

Technical Field

The present invention relates to a delay unit, and more particularly, to a linearly adjustable delay unit.

Background

In a communication system, when noise interference occurs to a signal, signal distortion is easily caused. Thus, in communication systems, compensation or cancellation techniques are used to avoid signal distortion. Nowadays, in high frequency communication systems, in order to transmit signals to a longer distance, equalization techniques of Pre-emphasis (Pre-emphasis) or De-emphasis (De-emphasis) are generally used at the transmitting end.

The pre-emphasis and de-emphasis are both to increase the energy of the high frequency part of the signal to compensate for the attenuation of the high frequency part of the signal caused by the transmission channel. For example, pre-emphasis may leave the low frequency portion of the signal unchanged and boost the high frequency portion of the signal. De-emphasis attenuates the low frequency portion of the signal while preserving the high frequency portion of the signal.

In some communication systems (e.g., de-emphasis circuits), delay cells or delayers may be required to adjust the timing of signals. Fig. 1A shows a conventional delay cell 10. The delay cell 10 includes P-type transistors P1-P4, N-type transistors N1 and N2, and a current source 20. The P-type transistor P1 is coupled between the power supply VCC and the positive output terminal 17P, and the P-type transistor P2 is coupled between the power supply VCC and the negative output terminal 17N. In addition, the gate of the P-type transistor P1 is coupled to the gate of the P-type transistor P2 for receiving the control voltage Vctrl. The P-type transistor P3 is coupled between the power supply VCC and the positive output terminal 17P, and the gate of the P-type transistor P3 is coupled to the positive output terminal 17P. The P-type transistor P4 is coupled between the power supply VCC and the negative output terminal 17N, and the gate of the P-type transistor P4 is coupled to the negative output terminal 17N. The P-type transistors P3 and P4 can be replaced by resistors. The N-type transistor N1 is coupled between the positive output terminal 17P and the node m1, and the N2 is coupled between the negative output terminal 17N and the node m 1. The gate of the N-type transistor N1 is coupled to the positive input terminal 14P of the delay cell 10 and is used for receiving the input signal V_IP. The gate of the N-type transistor N2 is coupled to the negative input terminal 14N of the delay cell 10 and is used for receiving the input signal V_IN. The current source 20 is coupled between the node m1 and the ground GND. In the delay unit 10, the input signal V can be changed by changing the control voltage Vctrl_IPAnd V_INDelayed by a delay time td to provide output signals VOP and VON at the positive output terminal 17P and the negative output terminal 17N, respectively. However, when the control voltage Vctrl is changed, the resistance (rds) between the drain and the source of the P-type transistors P1 and P2 is changed and the conductance (gds) between the drain and the source is also changed, so that the control voltage Vctrl cannot linearly control the delay time td, as shown in fig. 1B. If the delay time td of the signal cannot be adjusted in a linear manner, signal distortion will result.

In view of the above, it is important to have a delay unit capable of linear adjustment.

Disclosure of Invention

In order to solve the above-mentioned technical problem, an object of the present application is to provide a delay unit capable of linear adjustment.

The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme. In one aspect, a delay cell is provided according to the present application, which includes a first input transistor, a second input transistor, a variable current source, a first mirror transistor, a second mirror transistor, a third mirror transistor, and a variable capacitor. The first input transistor is coupled between a power supply and a first output end, and has a control end for receiving a first input signal. The second input transistor is coupled between the power supply and a second output terminal, and has a control terminal for receiving a second input signal. The first mirror transistor is coupled between the variable current source and a ground terminal, and has a control terminal coupled to the variable current source. The second mirror transistor is coupled between the first output terminal and the ground terminal, and has a control terminal coupled to the variable current source. The third mirror transistor is coupled between the second output terminal and the ground terminal, and has a control terminal coupled to the variable current source. The variable capacitor is coupled between the first output end and the second output end. The first input signal and the second input signal are a first pair of differential signals.

From another aspect, the present invention provides a delay cell comprising a first input transistor, a second input transistor, a first variable current source, a second variable current source and a variable capacitor. The first input transistor is coupled between a power supply and a first output end, and has a control end for receiving a first input signal. The second input transistor is coupled between the power supply and a second output terminal, and has a control terminal for receiving a second input signal. The first variable current source is coupled between the first output terminal and a ground terminal. The second variable current source is coupled between the second output terminal and the ground terminal. The variable capacitor is coupled between the first output end and the second output end. The first input signal and the second input signal are a first pair of differential signals.

The technical problem solved by the application can be further realized by adopting the following technical measures.

Drawings

Fig. 1A is a schematic diagram of a conventional delay cell architecture.

FIG. 1B is a diagram of the control voltage and delay time of a conventional delay cell.

FIG. 2 is a block diagram of an exemplary de-emphasis circuit.

FIG. 3 is a diagram of an exemplary delay cell architecture.

Fig. 4A is a waveform diagram of the delay cell of fig. 3 according to an example.

FIG. 4B is a graph illustrating capacitance versus delay time for an exemplary sub-capacitor.

FIG. 5 is a diagram of another exemplary delay cell architecture.

Detailed Description

The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The foregoing and other features and advantages of the invention will be apparent from the following, more particular description of preferred embodiments, as illustrated in the accompanying drawings.

The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present application is not limited thereto.

To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of a battery management system according to the present invention with reference to the accompanying drawings and preferred embodiments will be made as follows.

Referring to fig. 2, an exemplary de-emphasis (de-emphasis) circuit 100 is shown. The de-emphasis circuit 100 includes a main driver 110, a de-emphasis driver 120, a delay unit 130, inductors L1 and L2, capacitors C1 and C2, a diode D1, a current source 140, and resistors R1 and R2. The signals TXin-and TXin + are differential signals, and the signals TXin-and TXin + are provided to the main driver 110 and the delay unit 130. Delay unit 130 delays signals TXIN-and TXIN + to generate signals TD-and TD + to de-emphasis driver 120, and delay time TD is linearly adjustable. The positive output of the main driver 110 and the negative output of the de-emphasis driver 120 are coupled together via a node n11, and the negative output of the main driver 110 and the positive output of the de-emphasis driver 120 are coupled together via a node n 12. Thus, a third differential pair of output signals Vo + and Vo-is obtained at nodes n11 and n12 based on the first differential pair of signals from the primary driver 110 corresponding to signals TXin-and TXin + and the second differential pair of signals from the de-emphasis driver 120 corresponding to signals TD-and TD +. The resistor R1 is coupled between the power supply VCC and the node n11, and the resistor R2 is coupled between the power supply VCC and the node n 12. The capacitor C1 is coupled between the nodes n11 and n13, and the capacitor C2 is coupled between the nodes n12 and n 14. The inductor L1 is coupled between the node n13 and the power supply VCC, and the inductor L2 is coupled between the node n14 and the current source 140. The anode of the diode D1 is coupled to the node n13, and the cathode of the diode D1 is coupled to the node n 14. The current source 140 is coupled between the inductor L2 and the ground GND.

Fig. 3 is a block diagram of an exemplary delay cell 130A of the present application. Delay cell 130A includes transistors Q1-Q5, capacitor 155, and variable current source 150. Transistors Q3 and Q4 are input transistors and have the same size. The transistor Q3 is coupled between the power supply VCC and the positive output terminal 135P of the delay unit 130A, and the transistor Q4 is coupled between the power supply VCC and the negative output terminal 135N of the delay unit 130A. In addition to this, the present invention is,transistors Q3 and Q4 are bipolar transistors (BJTs). A control terminal (i.e., a base) of the transistor Q3 is coupled to the positive input terminal 132P of the delay unit 130A and is used for receiving an input signal V_IP. The control terminal (i.e., base) of the transistor Q4 is coupled to the negative input terminal 132N of the delay unit 130A and is configured to receive the input signal VIN. In some embodiments, the transistors Q3 and Q4 may be mos field effect transistors (e.g., PMOS transistors) or other types of field effect transistors.

In fig. 3, the transistors Q1, Q2, and Q5 are also bipolar transistors, and the transistors Q1 and Q2 have the same size. The transistor Q1 is coupled between the positive output terminal 135P and the ground terminal GND, and the transistor Q2 is coupled between the negative output terminal 135N and the ground terminal GND. The control terminals (bases) of the transistors Q1 and Q2 are coupled together and are coupled to the control terminal of the transistor Q5 and the variable current source 150. The transistor Q5 is coupled between the variable current source 150 and the ground GND. The variable current source 150 provides an adjustable bias current Ibias to the transistor Q5. In addition, the current I1 flowing through the transistor Q1 and the current I2 flowing through the transistor Q2 are generated by a mirror (mirror) bias current Ibias. In other words, the transistors Q1, Q2, and Q5 and the variable current source 150 form a mirror circuit, and the transistors Q1, Q2, and Q5 are mirror transistors. In addition, the currents I1 and I2 are proportional to the bias current Ibias, and the currents I1 and I2 have the same amount of current. In some embodiments, the transistors Q1, Q2, and Q5 may be mos field effect transistors (e.g., NMOS transistors) or other types of field effect transistors.

In one embodiment, the present invention relates to an emitter Follower (emitter Follower) circuit architecture or a Source Follower (Source Follower) circuit architecture that can be used in a Bipolar Junction Transistor (BJT).

In one embodiment, the capacitor 155 is coupled between the positive output port 135P and the negative output port 135N, and is divided into sub-capacitors C connected in series_SW1And C_SW2. Sub-capacitor C_SW1And C_SW2Is a variable capacitor, and a sub-capacitor C_SW1And C_SW2With the same capacitance value. In addition, delay unit 130A further includes parasitic capacitances CL1 and CL 2. Parasitic capacitance CL1 is a parasitic capacitance shown on positive output terminal 135P, and parasitic capacitance CL2 is a parasitic capacitance shown on negative output terminal 135N. The delay unit 130A has symmetry in layout, so the parasitic capacitances CL1 and CL2 have substantially the same capacitance. In addition, by controlling the sub-capacitor C_SW1And C_SW2Can convert the input signal V into_IPAnd V_INDelay a delay time td to provide the output signal V at the positive output terminal 135P and the negative output terminal 135N, respectively_OPAnd V_ON. In addition, according to the capacitor 155 and the parasitic capacitors CL1 and CL2, the delay time td can be obtained as shown by the following equation:

wherein C is_SWIs representative of a sub-capacitance C_SW1And C_SW2The capacitance value of (1), CL, represents the capacitance values of parasitic capacitances CL1 and CL2, and gm_Q3Is a transconductance (transconductance) representation of transistors Q3 and Q4.

Further, fig. 4A is a waveform diagram of the delay unit 130A of fig. 3 according to an example. Input signal V_IPIs a signal received at a positive input 132P, and an output signal V_OPIs the signal provided at the positive output 135P. In FIG. 4A, an input signal V_IPAnd an output signal V_OPHaving the same waveform. Furthermore, an input signal V_IPAnd an output signal V_OPThe delay time td therebetween is equal to the time difference between time t1 and time t2, i.e., td is t2-t 1. For input signal V with fixed frequency_IPAnd V_INIn other words, the current sub-capacitor C_SW1And C_SW2Capacitance value C of_SWAs it increases, the delay time td increases. On the contrary, the current sub-capacitor C_SW1And C_SW2Capacitance value C of_SWAs this decreases, the delay time td decreases.

In some embodiments, when the input signal V is_IPAnd V_INWhen the frequency F is changed, the amount of the bias current Ibias can be adjusted to adjust the currentThe current I1 flowing through the transistor Q1 and the current I2 flowing through the transistor Q2 are such that the delay time td is equal to the input signal V_IPAnd V_INIs proportional to the frequency F (or period TP). For example, when inputting signal V_IPAnd V_INAt a frequency F of 10 gigahertz (10GHz), the sub-capacitance C is adjustable_SW1And C_SW2Capacitance value C of_SWTo obtain the desired delay time td, e.g., delayed by one-half cycle. Generally, the frequency F and the period TP are in inverse relationship, i.e., F is 1/TP. In some embodiments, when the input signal V is_IPAnd V_INIs changed, the delay time td and the input signal V must be maintained in order to provide the correct signal to the subsequent correlation circuit_IPAnd V_INIs fixed, the ratio between the frequencies F (or periods TP) of (a) and (b) is fixed. For example, when inputting signal V_IPAnd V_INWhen the frequency of (2) is changed to 20 gigahertz (20GHz), the amount of the bias current Ibias can be increased (for example, doubled) so as to increase the current I1 flowing through the transistor Q1 and the current I2 flowing through the transistor Q2. Thus, the delay time td and the input signal V can be controlled_IPAnd V_INIs fixed, the ratio between the frequencies F (or periods TP) of (a) and (b) is fixed.

In one embodiment, FIG. 4B shows an exemplary sub-capacitor C_SW1And C_SW2Capacitance value C of_SWWith respect to the delay time td. Compared with the conventional delay cell, the delay cell has the advantages that the sub-capacitor C_SW1And C_SW2Capacitance value C of_SWIs not subject to other signals (e.g. input signal V)_IPAnd V_IN) Thereby adjusting the capacitance value C_SWThe delay time td can be linearly controlled. In FIG. 4B,

reference numerals

210 and 220 indicate capacitance C at different bias currents Ibias_SWWith respect to the delay time td. For example, reference numeral 210 is shown at a low bias current Ibias, and reference numeral 220 is shown at a high bias current Ibias.

FIG. 5 is a block diagram of an exemplary alternative delay cell 130B architecture. The delay unit 130B includes transistors Q3 and Q4, a capacitor 155, and variable

current sources

160 and 170. In this embodiment, the delay unit 130B does not include the delay unit 130 of FIG. 2And A, a mirror circuit. In the delay unit 130B of fig. 5, the variable current source 160 is coupled between the positive output terminal 135P and the ground GND for drawing a current I1 through the transistor Q3. In addition, the variable current source 170 is coupled between the negative output terminal 135N and the ground GND for drawing a current I2 through the transistor Q4. Similarly, by controlling the sub-capacitance C_SW1And C_SW2Capacitance value C of_SWCan convert an input signal V_IPAnd V_INDelay a delay time td to provide the output signal V at the positive output terminal 135P and the negative output terminal 135N, respectively_OPAnd VON. In addition, when the signal V is input_IPAnd V_INThe variable

current sources

160 and 170 are adjusted to control the currents I1 and I2 such that the delay time td is equal to the input signal V_IPAnd V_INIs proportional to the frequency F (or period TP).

In one embodiment, the delay unit described herein is implemented by adjusting the capacitance C of the delay unit_SWThe delay time td can be linearly controlled. Furthermore, an input signal V_IPAnd V_INAnd an output signal V_OPAnd V_ONThe unit gain (unity gain) is between. Thus, signal distortion can be avoided.

The term "in one embodiment" or the like is used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.

Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.

Claims

1. A delay cell, comprising:

a first input transistor coupled between a power supply and a first output terminal, having a control terminal for receiving a first input signal;

a second input transistor coupled between the power supply and a second output terminal, having a control terminal for receiving a second input signal;

a variable current source;

a first mirror transistor coupled between the variable current source and a ground terminal, having a control terminal coupled to the variable current source;

a second mirror transistor coupled between the first output terminal and the ground terminal, and having a control terminal coupled to the variable current source;

a third mirror transistor coupled between the second output terminal and the ground terminal, having a control terminal coupled to the variable current source; and

a variable capacitor coupled between the first output terminal and the second output terminal,

wherein the first input signal and the second input signal are a first pair of differential signals.

2. The delay unit of claim 1, wherein the variable capacitor comprises a first sub-capacitor and a second sub-capacitor connected in series, and the first sub-capacitor and the second sub-capacitor have the same capacitance value.

3. The delay cell of claim 1, wherein the first and second input transistors and the first, second and third mirror transistors are the same type of transistor.

4. The delay cell of claim 1, wherein the first and second input transistors and the first, second and third mirror transistors are bipolar transistors or field effect transistors.

5. The delay cell of claim 1, wherein the first and second input transistors have the same size, and the first and second mirror transistors have the same size.

6. The delay cell of claim 1, wherein the first output terminal is configured to provide a first output signal and the second output terminal is configured to provide a second output signal, wherein the first output signal and the second output signal are a second pair of differential signals.

7. The delay unit of claim 6, wherein the first pair of differential signals and the second pair of differential signals have a delay time therebetween, and the delay time is determined by a capacitance of the variable capacitor.

8. A delay cell, comprising:

a first variable current source coupled between the first output terminal and a ground terminal;

a second variable current source coupled between the second output terminal and the ground terminal; and

9. The delay unit of claim 8, wherein the variable capacitor comprises a first sub-capacitor and a second sub-capacitor connected in series, and the first sub-capacitor and the second sub-capacitor have the same capacitance value.

10. The delay cell of claim 8, wherein the first input transistor is the same size as the second input transistor.

11. The delay cell of claim 8, wherein the first variable current source and the second variable current source have a same amount of current.

12. The delay cell of claim 8, wherein the first output terminal is configured to provide a first output signal and the second output terminal is configured to provide a second output signal, wherein the first output signal and the second output signal are a second pair of differential signals.

13. The delay unit of claim 8, wherein the first pair of differential signals and the second pair of differential signals have a delay time therebetween, and the delay time is determined by a capacitance of the variable capacitor.

14. The delay unit of claim 13, wherein the first pair of differential signals has a first frequency and the first frequency has a specific ratio to the delay time, and wherein when the first pair of differential signals has a second frequency, the current amounts of the first and second variable current sources are adjusted such that the second frequency has the specific ratio to the delay time.