CN113113392A

CN113113392A - Chip packaging structure and forming method thereof

Info

Publication number: CN113113392A
Application number: CN202110023444.7A
Authority: CN
Inventors: 叶书伸; 林柏尧; 郑心圃; 赖柏辰; 李光君; 杨哲嘉; 汪金华; 林义航
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-01-10
Filing date: 2021-01-08
Publication date: 2021-07-13
Also published as: DE102020130844A1

Abstract

A chip package structure and a method for forming the same are provided. The method includes disposing a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip structure are separated by a gap. The method also includes disposing a ring structure on the circuit substrate. The ring structure has a first opening in which the first chip structure and the second chip structure are located, the first opening has a first inner wall having a first recess, and the gap extends toward the first recess.

Description

Chip packaging structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to a chip package structure and a method for forming the same, and more particularly, to a chip package structure having a ring structure and a method for forming the same.

Background

Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive lines, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using photolithography and etching processes to form circuit elements and devices thereon.

In general, many Integrated Circuits (ICs) are fabricated on a semiconductor wafer, and technological advances in integrated circuit materials and design have produced generations of ICs. Each generation of circuitry is smaller and more complex than previous generations of circuitry. The handling and packaging of the die (die) of the wafer may be performed using a wafer-level (wafer-level), and various techniques for chip-level packaging have been developed. Since a chip package may need to contain multiple chips with multiple functions, it is still challenging to form a reliable chip package with multiple chips.

Disclosure of Invention

The embodiment of the disclosure provides a forming method of a chip packaging structure. The method includes disposing a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip structure are separated by a gap. The method also includes disposing a ring structure on the circuit substrate. The ring structure has a first opening, the first chip structure and the second chip structure are located in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

The embodiment of the disclosure provides a forming method of a chip packaging structure. The method includes disposing a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip structure are separated by a gap. The method also includes disposing a ring structure on the circuit substrate. A ring structure surrounds the first and second chip structures, the ring structure including a first thinner portion and a first thicker portion connected to each other, and a gap is adjacent to the first thinner portion.

The disclosed embodiment provides a chip packaging structure. The chip packaging structure comprises a circuit substrate. The chip packaging structure comprises a first chip structure and a second chip structure which are positioned on the circuit substrate. The first chip structure and the second chip structure are separated by a gap. The chip package structure includes a ring structure disposed on a circuit substrate. The circuit substrate is provided with an opening, the first chip structure and the second chip structure are positioned in the opening, the opening is provided with an inner wall, the inner wall is provided with a recess, and the gap extends towards the recess.

Drawings

The contents of the embodiments of the present disclosure can be understood more clearly by the following detailed description in conjunction with the accompanying drawings. It is emphasized that, in accordance with industry standard practice, many of the features (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1E are schematic cross-sectional views of a process for forming a chip package structure at various stages according to some embodiments.

Fig. 1A-1 is a schematic top view of the chip package structure of fig. 1A, according to some embodiments.

FIG. 1B-1 is a schematic top view of the chip package structure of FIG. 1B according to some embodiments.

Fig. 1C-1 is a schematic top view of the chip package structure of fig. 1C, according to some embodiments.

Fig. 1D-1 is a schematic top view of the chip package structure of fig. 1D, according to some embodiments.

Fig. 1D-2 are perspective schematic views of the chip package structure of fig. 1D according to some embodiments.

Fig. 1D-3 are schematic top views of a ring structure of the chip package structure of fig. 1D, according to some embodiments.

Fig. 1E-1 is a schematic top view of the chip package structure of fig. 1E, according to some embodiments.

Fig. 1E-2 is a perspective schematic view of the chip package structure of fig. 1E, according to some embodiments.

Fig. 2A is a schematic cross-sectional view illustrating a chip package structure according to some embodiments.

Fig. 2B is a schematic top view illustrating the chip package structure of fig. 2A according to some embodiments.

Fig. 2C is a schematic perspective view showing the chip package structure of fig. 2A, according to some embodiments.

Fig. 2D is a schematic perspective view showing the ring structure of fig. 2A, according to some embodiments.

Fig. 2E is a top view schematic diagram showing the chip package structure of fig. 2A without a ring structure, according to some embodiments.

Fig. 3A is a schematic perspective view showing a chip package structure according to some embodiments.

Fig. 3B is a top view schematic diagram showing the chip package structure of fig. 3A without a ring structure, according to some embodiments.

Fig. 4A is a schematic cross-sectional view illustrating a chip package structure according to some embodiments.

Fig. 4B is a schematic top view illustrating the chip package structure of fig. 4A according to some embodiments.

Fig. 4C is a schematic perspective view showing the chip package structure of fig. 4A, according to some embodiments.

Fig. 4D is a top view schematic diagram showing the chip package structure of fig. 4A without a ring structure, according to some embodiments.

Fig. 4E is an expanded schematic view showing the loop structure and adhesive layer of fig. 4A, according to some embodiments.

Fig. 5 is a schematic top view showing a chip package structure according to some embodiments.

Fig. 6 is a schematic top view showing a chip package structure according to some embodiments.

Fig. 7 is a schematic top view showing a chip package structure according to some embodiments.

Fig. 8 is a schematic top view showing a chip package structure according to some embodiments.

Fig. 9 is a schematic cross-sectional view showing a chip package structure according to some embodiments.

Fig. 10 is a cross-sectional schematic diagram illustrating a chip package structure, according to some embodiments.

Wherein the reference numerals are as follows:

100: chip packaging structure

108: conductive pole

110: heavy wiring structure

111: bottom surface

112: line layer

114: conductive vias

116: dielectric layer

122: chip structure

122 a: side wall

124: conductive pole

130: underfill layer

140: molding layer

150: solder bump

160: circuit substrate

162: dielectric layer

164: conducting pad

166: line layer

168: conductive vias

170: underfill layer

180: device for measuring the position of a moving object

190: adhesive layer

192: groove

194: opening of the container

194 a: inner wall

194 b: depressions

196: side wall

200: chip packaging structure

210: ring structure

210A: lower part

210B: the upper part

211: bottom surface

211A: in part

212: groove

212A: groove

213: side wall

214: opening of the container

214 a: inner wall

214 b: depressions

214b 1: inner wall

214A: depressions

215: strip-shaped part

215 a: terminal end

216: outer ring

216 a: the top surface

216 b: the top surface

216A: thinner part

216C: thinner part

216B: thicker part

216D: thicker part

217: strip-shaped part

217 a: terminal end

218: strip-shaped part

219: strip-shaped part

220: cover member

300: chip packaging structure

400: chip packaging structure

410: adhesive layer

412: groove

414: opening of the container

414 a: inner wall

414 b: depressions

500: chip packaging structure

510: ring structure

510A: narrower part

510B: wider part

512: opening of the container

512 a: inner wall

512 b: depressions

600: chip packaging structure

612: in part

614: in part

616: gap

700: chip packaging structure

800: chip packaging structure

A: adhesive layer

D1: distance between two adjacent plates

D2: distance between two adjacent plates

D3: transverse distance

G1: gap

G2: gap

P: packaging structure

W122: width of

W220: width of

W510A: line width

W510B: line width

Detailed Description

The following provides many different embodiments, or examples, for implementing different features of embodiments of the disclosure. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the embodiments of the disclosure. For example, references in the specification to a first feature being formed on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. Various components may be arbitrarily shown in varying sizes for the sake of brevity and clarity. Additionally, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. These iterations are for simplicity and clarity and do not in themselves represent a particular relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms such as "below …," "below …," "below," "above …," "above," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated. Spatially relative terms may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is rotated to other orientations (rotated 90 degrees or otherwise), the spatially relative descriptors used herein should be interpreted as such with respect to the rotated orientation.

In the description, the term "substantially" such as "substantially flat" or "substantially coplanar" will be understood by those of ordinary skill in the art. In some embodiments, the adjective may be substantially removed. Where applicable, the term "substantially" may also encompass embodiments having "entirely (entirely)," entirely (completed), "all (all)". Where applicable, the term "substantially" may also relate to 90% or more, such as 95% or more, especially 99% or more, or comprise 100%. Furthermore, the terms "substantially parallel" or "substantially perpendicular" are to be read as not excluding minor deviations from the specified arrangement and may include deviations of, for example, up to 10 °. The term "substantially" does not exclude "completely", e.g., "substantially free" of Y, which may be completely free of Y.

The term "about" in connection with a particular distance or dimension should be read as not excluding minor deviations from the particular distance or dimension and may include deviations of, for example, up to 10 °. The term "about" in relation to the value x may mean x ± 5 or 10%.

Some embodiments are disclosed herein. Additional steps may be provided before, during, or after the stages mentioned in these embodiments. Some of the stages described may be replaced or eliminated with respect to different embodiments. Additional features may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated with respect to different embodiments. Although some embodiments are discussed with steps performed in a particular order, these steps may be performed in other logical orders.

Other components or processes may also be included. For example, test structures may be included to facilitate verification testing of 3D packages or 3D-IC devices. The test structure may include, for example, a test pad (testing pad) formed on a redistribution layer or a substrate, which allows a 3D package or a 3D-IC to be tested, a probe (probe) or a probe card (probe card) to be used, and the like. Verification testing may be performed on the intermediate structure and the final structure. In addition, the structures and methods disclosed herein may be used in conjunction with testing methods that integrate intermediate verification of good die (good die) identification to improve yield and reduce cost.

Fig. 1A-1E are schematic cross-sectional views of a process for forming a chip package structure at various stages according to some embodiments. Fig. 1A-1 is a schematic top view of the chip package structure of fig. 1A, according to some embodiments.

According to some embodiments, a package P is provided, as shown in fig. 1A and 1A-1. According to some embodiments, the package body P includes a redistribution structure 110, a chip structure 122, conductive pillars 124, an underfill (underfill) layer 130, and a molding (molding) layer 140. According to some embodiments, the rewiring structure 110 includes a wire (wiring) layer 112, a conductive via (via)114, and a dielectric layer 116.

According to some embodiments, line layer 112 and conductive vias 114 are formed in dielectric layer 116. According to some embodiments, the conductive vias 114 are electrically connected between different circuit layers 112, as shown in fig. 1A. According to some embodiments, only two line layers 112 are shown in fig. 1A for simplicity.

According to some embodiments, the dielectric layer 116 is formed of an insulating material, such as a polymeric material (e.g., polybenzo)

An azole (polybenzoxazole), polyimide (polyimide), or a photosensitive material), a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), silicon oxynitride, or the like.

According to some embodiments, the dielectric layer 116 is formed using a deposition process (e.g., a chemical vapor deposition process or a physical vapor deposition process), a photolithography process, and an etching process. According to some embodiments, the line layer 112 and the conductive vias 114 are formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten), or alloys of the foregoing.

According to some embodiments, the chip structure 122 is bonded to the rerouting structure 110 by conductive pillars 124. According to some embodiments, the chip structures 122 are separated from each other by a gap G1. According to some embodiments, the conductive pillars 124 are physically and electrically connected between the chip structure 122 and the redistribution structure 110. According to some embodiments, each chip structure 122 includes a chip, such as a system on chip (SoC).

According to some embodiments, the chip comprises a substrate. In some embodiments, the substrate is formed of an elemental semiconductor material comprising silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure. In other embodiments, the substrate is formed from a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), an alloy semiconductor (e.g., SiGe, or GaAsP), or a combination of the foregoing. The substrate may also comprise multiple layers of semiconductors, Semiconductor On Insulator (SOI), such as silicon on insulator, or germanium on insulator, or combinations thereof.

In some embodiments, the substrate includes various device elements. In some embodiments, various device elements are formed in and/or on the substrate. Device elements are not shown in the figures for clarity and conciseness. Exemplary device components include active components, passive components, other suitable components, or combinations of the foregoing. The active devices may include transistors or diodes (not shown) formed at the surface of the substrate. The passive elements may include resistors, capacitors, or other suitable passive elements.

For example, the transistors may be Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, double junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (pFETs/nFETs), and the like. Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, may be performed to form various device elements. The front-end semiconductor fabrication process may comprise deposition, etching, implantation, lithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in the substrate. The isolation component is used for defining an active region and electrically isolating various device elements, and the device elements are formed in the active region and in the substrate and/or on the substrate. In some embodiments, the isolation feature comprises a Shallow Trench Isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, other suitable isolation features, or a combination thereof.

In other embodiments, chip structure 122 comprises a chip package structure. In some embodiments, the chip package structure includes one chip. In other embodiments, the chip package structure includes a plurality of chips that are juxtaposed or stacked on top of each other (e.g., 3D packages or 3DIC devices).

According to some embodiments, the conductive pillars 124 are formed of a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni), or zinc (Sn). According to some embodiments, the conductive pillars 124 are formed using a plating process, such as an electroplating (electroplating) process.

According to some embodiments, the underfill layer 130 is interposed between the chip structure 122 and the redistribution structure 110, as shown in fig. 1A and 1A-1. According to some embodiments, the underfill layer 130 surrounds the conductive pillars 124 and the chip structure 122.

According to some embodiments, the underfill layer 130 extends into the gap G1. According to some embodiments, the gap G1 is filled by the underfill layer 130. According to some embodiments, the underfill layer 130 is formed of an insulating material, such as a polymer material.

According to some embodiments, a mold layer 140 is formed over the redistribution structure 110 and the underfill layer 130, as shown in fig. 1A and 1A-1. According to some embodiments, the molding layer 140 surrounds the chip structure 122, the conductive pillars 124, and the underfill layer 130. According to some embodiments, the molding layer 140 is formed of an insulating material, such as epoxy (epoxy).

According to some embodiments, the conductive pillars 108 are formed on the bottom surface 111 of the redistribution structure 110, as shown in fig. 1A and 1A-1. According to some embodiments, the conductive pillars 108 are formed of a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni), or zinc (Sn). According to some embodiments, the conductive pillars 108 are formed using a plating process, such as an electroplating (electroplating) process.

According to some embodiments, a solder bump (solder bump)150 is formed on the conductive pillar 108, as shown in fig. 1A and 1A-1. According to some embodiments, the solder bumps 150 are formed of tin (Sin) or other suitable conductive material having a melting point lower than the melting point of the conductive pillars 108. According to some embodiments, the solder bump 150 is formed using a plating process, such as an electroplating (electroplating) process.

FIG. 1B-1 is a chip package structure of FIG. 1B according to some embodiments. According to some embodiments, the package structure P is bonded to a wiring substrate (wiring substrate)160 by solder bumps 150, as shown in fig. 1B and 1B-1. According to some embodiments, the wiring substrate 160 includes a dielectric layer 162, a conductive pad (pad)164, a wiring layer 166, and a conductive via 168.

According to some embodiments, the conductive pad 164 is formed over the dielectric layer 162. According to some embodiments, the solder bump 150 is bonded to the conductive pad 164. According to some embodiments, a line layer 166 and conductive vias 168 are formed in the dielectric layer 162.

According to some embodiments, the conductive vias 168 are electrically connected between different circuit layers 166, and between the circuit layers 166 and the conductive pads 164. According to some embodiments, only two line layers 166 are shown in fig. 1B for simplicity.

According to some embodiments, the dielectric layer 162 is formed of an insulating material, such as a polymeric material (e.g., polybenzo)

Oxazole (polybenzoxazole), polyimide (polyimide), or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., oxygen)Silicon oxide), silicon oxynitride, or the like. According to some embodiments, the dielectric layer 162 is formed using a deposition process (e.g., a chemical vapor deposition process or a physical vapor deposition process), a photolithography process, and an etching process.

According to some embodiments, the conductive pad 164 is formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten), or alloys of the foregoing. According to some embodiments, the wiring layer 166 is formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten), or alloys of the foregoing. According to some embodiments, the conductive vias 168 are formed of a conductive material, such as a metal (e.g., copper, aluminum, or tungsten), or alloys of the foregoing.

In some embodiments, the conductive pad 164, the line layer 166, and the conductive via 168 are formed of the same material. In other embodiments, the conductive pad 164, the line layer 166, and the conductive via 168 are formed of different materials.

According to some embodiments, an underfill layer 170 is formed between the package body P and the circuit substrate 160, as shown in fig. 1B and 1B-1. According to some embodiments, the filling layer 170 surrounds the conductive pillars 108, the solder bumps 150, and the package body P. According to some embodiments, the underfill layer 170 is formed of an insulating material, such as a polymer material.

According to some embodiments, the device 180 is bonded to the wiring substrate 160, for example, by Surface Mount Technology (SMT), as shown in fig. 1B and 1B-1. The device 180 comprises a passive device, other suitable device, or a combination of the foregoing. Passive devices include resistors, capacitors, inductors, or other suitable passive devices.

Fig. 1C-1 is a schematic top view of the chip package structure of fig. 1C, according to some embodiments. According to some embodiments, an adhesive layer 190 is formed on the circuit substrate 160, as shown in FIGS. 1C and 1C-1. According to some embodiments, the adhesive layer 190 has a groove 192 and an opening 194. According to some embodiments, the device 180 is located in a groove 192. According to some embodiments, the package P is located in the opening 194.

According to some embodiments, the groove 192 surrounds the opening 194. According to some embodiments, the opening 194 has an inner wall 194 a. According to some embodiments, the inner wall 194a has a recess 194 b. According to some embodiments, each recess 194b communicates with a corresponding groove 192. According to some embodiments, the gap G1 extends toward the recess 194 b. According to some embodiments, the adhesive layer 190 is formed of a polymer material, such as epoxy or silicone.

Fig. 1D-1 is a schematic top view of the chip package structure of fig. 1D, according to some embodiments. Fig. 1D-2 are perspective schematic views of the chip package structure of fig. 1D according to some embodiments. For simplicity, the underfill layer 170 is omitted from FIGS. 1D-2.

According to some embodiments, a ring structure 210 is disposed on the adhesive layer 190, as shown in FIG. 1D, FIG. 1D-1, and FIG. 1D-2. Fig. 1D-3 are schematic top views of a ring structure 210 of the chip package structure of fig. 1D, according to some embodiments. According to some embodiments, the ring structure 210 has a trench 212 and an opening 214, as shown in FIGS. 1D, 1D-1, 1D-2, and 1D-3. According to some embodiments, the trench 212 surrounds the opening 214.

According to some embodiments, the groove 212 has a substantially rectangular shape. According to some embodiments, the opening 214 has a substantially rectangular shape. According to some embodiments, the grooves 212 are adjacent to four inner walls 214a of the opening 214, respectively. According to some embodiments, the device 180 is located in the trench 212. According to some embodiments, the trench 212 and the opening 214 are formed using a milling process or a wire cutting process.

According to some embodiments, the opening 194 of the adhesive layer 190 is located below the opening 214, as shown in FIG. 1D, FIG. 1D-1, and FIG. 1D-2. According to some embodiments, the package P is located in the opening 214. Two of these inner walls 214a have recesses 214 b. According to some embodiments, each recess 214b communicates with a corresponding groove 212 and opening 214. According to some embodiments, the recess 214b has a substantially rectangular shape.

According to some embodiments, the gap G1 extends toward the recess 214 b. According to some embodiments, the recess 194b of the adhesive layer 190 is located below the recess 214 b. According to some embodiments, the

recesses

214b and 194b have substantially the same width W1.

According to some embodiments, the ring structure 210 has an outer ring 216 and

strip portions

215, 217, 218, and 219. According to some embodiments, the

strip portions

215, 217, 218, and 219 are also referred to as ribs (rib). According to some embodiments, the

strips

215, 217, 218, and 219 are surrounded by an outer ring 216.

According to some embodiments, the strip portion 215 has a substantially rectangular shape. According to some embodiments, the strip portion 215 has opposite ends 215a connected to the outer ring 216. According to some embodiments, the recess 214b is located in the strip portion 215. According to some embodiments, the recess 214b passes through the strip portion 215.

According to some embodiments, the strip portion 217 has a substantially rectangular shape. According to some embodiments, the strip portion 217 has opposite ends 217a connected to the outer ring 216. According to some embodiments, the recess 214b is located in the strip portion 217. According to some embodiments, the recess 214b passes through the strip portion 217.

According to some embodiments, the strip portion 218 has a substantially rectangular shape. According to some embodiments, strip portion 218 is interposed between strip portion 215 and strip portion 217. According to some embodiments, strip portion 218 is connected to strip portion 215 and strip portion 217.

According to some embodiments, the strip portion 219 has a substantially rectangular shape. According to some embodiments, stripe 219 is between stripe 215 and stripe 217. According to some embodiments, stripe 219 is connected to stripe 215 and stripe 217. Thus, according to some embodiments,

strip portions

218, 215, and 217 collectively form a first I-shaped structure, and

strip portions

219, 215, and 217 collectively form a second I-shaped structure. According to some embodiments, the two I-shaped structures are disposed on opposite sides of the package body P.

In some embodiments, the distance D1 between the chip structure 122 and the strip portion 215 ranges from about 7 centimeters (mm) to about 20 mm. According to some embodiments, if the distance D1 is less than about 7mm, the stress at the corners of the chip is greater, which is undesirable. According to some embodiments, if the distance D1 is greater than about 20mm, the size of the ring structure 210 is larger, which takes up too much surface area of the wiring substrate 160.

In some embodiments, the distance D2 between the chip structure 122 and the strip portion 218 ranges from about 7mm to about 20 mm. According to some embodiments, if the distance D2 is less than about 7mm, the stress at the corners of the chip is greater, which is undesirable. According to some embodiments, if the distance D2 is greater than about 20mm, the size of the ring structure 210 is larger, which takes up too much surface area of the wiring substrate 160.

According to some embodiments, chip structure 122 has a width W122. According to some embodiments, each chip structure 122 has a sidewall 122a facing the gap G1. In some embodiments, the lateral distance D3 is between the side wall 122a and the inner wall 214b1 of the recess 214 b. In some embodiments, the ratio of the lateral distance D3 to the width W122 ranges from about 0.3 to about 0.7. According to some embodiments, the ratio (D3/W122) ranges from about 0.5 to about 0.7. In some embodiments, the distance D4 between sidewalls 122a ranges from about 40 nanometers (nm) to about 120 nm.

According to some embodiments, the ring structure 210 is formed of a rigid material, such as a metal (e.g., copper or iron), an alloy of the foregoing (e.g., stainless steel), or other suitable material that is harder than the wiring substrate 160.

Fig. 1E-1 is a schematic top view of the chip package structure of fig. 1E, according to some embodiments. Fig. 1E-2 is a perspective schematic view of the chip package structure of fig. 1E, according to some embodiments. For simplicity, the underfill layer 170 and the adhesive layer A are omitted from FIGS. 1E-2.

According to some embodiments, a lid (lid)220 is disposed over the chip structure 122, as shown in FIG. 1E, FIG. 1E-1, and FIG. 1E-2, respectively. In this step, the chip package structure 100 is substantially formed, according to some embodiments. According to some embodiments, the cover 220 is narrower than the underlying chip structure 122. That is, according to some embodiments, the width W220 of the cover 220 is less than the width W122 of the chip structure 122.

According to some embodiments, the cap member 220 is formed from a high thermal conductivity material, such as a metallic material (e.g., aluminum or copper), an alloy material (e.g., stainless steel), or aluminum-silicon carbide (AlSiC).

In some embodiments, an adhesive layer a is formed between the cover member 220 and the chip structure 122, as shown in fig. 1E. According to some embodiments, the adhesive layer A is formed of a conductive polymer and a metal (e.g., silver paste) or a polymer (e.g., epoxy or silicone).

According to some embodiments, when a ring structure is used to reduce warpage (warpage) of the wiring substrate 160, stress is easily concentrated on the underfill layer 130 in the gap G1. According to some embodiments, the stress is susceptible to causing cracks (craks) or delaminations (delaminations) in the underfill layer 130 in the gap G1. Thus, according to some embodiments, the method of embodiments of the present disclosure removes portions of the ring structure 210 near the gap G1 to reduce the ability of the ring structure 210 to resist warping near the gap G1. As such, according to some embodiments, the stress of the underfill layer 130 concentrated in the gap G1 is reduced. According to some embodiments, because the method of embodiments of the present disclosure removes only the portion of the ring-shaped structure 210 proximate to the gap G1, the warp resistance of the entire ring-shaped structure 210 is substantially maintained within an acceptable range. According to some embodiments, the yield of the chip package structure 100 is thus improved.

According to some embodiments, the cover member 220 can reduce warpage of the chip structure 122, which can reduce warpage of the circuit substrate 160. According to some embodiments, the chip package structure 100 is thus improved.

In some embodiments, sidewall 196 of adhesion layer 190 is aligned with or coplanar with sidewall 213 of ring structure 210. In other embodiments, sidewall 196 of adhesion layer 190 is recessed from sidewall 213 of ring structure 210, as shown in FIG. 9. In other embodiments, sidewall 196 of adhesive layer 190 protrudes from sidewall 213 of ring structure 210, as shown in FIG. 10.

Fig. 2A shows a chip package structure 200, according to some embodiments. Fig. 2B is a schematic top view of the chip package structure 200 of fig. 2A according to some embodiments. Fig. 2C is a schematic perspective view showing the chip package structure 200 of fig. 2A, according to some embodiments. For simplicity, the underfill layer 170 and the adhesive layer a are omitted from fig. 2C.

Fig. 2D is a schematic perspective view showing the ring structure 210 of fig. 2A, according to some embodiments. According to some embodiments, fig. 2D is viewed from a bottom surface 211 of the ring structure 210. Fig. 2E is a schematic top view illustrating the chip package structure 200 of fig. 2A without the ring structure 210 according to some embodiments

According to some embodiments, chip package structure 200 is similar to chip package structure 100 of fig. 1E, except that ring structure 210 has a lower portion 210A and an upper portion 210B, and both have different structures, as shown in fig. 2A, 2B, 2C, 2D, and 2E. According to some embodiments, the ring structure 210 has an opening 214. According to some embodiments, the package P is located in the opening 214.

According to some embodiments, the lower portion 210A is similar in structure to the ring structure 210 of fig. 1E. According to some embodiments, the lower portion 210A has a trench 212A and a recess 214A, as shown in fig. 2B and 2D. According to some embodiments, the trench 212A surrounds the opening 214. According to some embodiments, each recess 214A communicates with a corresponding trench 212A and opening 214. According to some embodiments, the device 180 is located in the trench 212A, as shown in fig. 2A.

According to some embodiments, the upper portion 210B is a continuous plate that overlies the lower portion 210A and covers the groove 212A and the recess 214A, as shown in fig. 2A, 2B, and 2D. According to some embodiments, the upper portion 210B is thinner than the lower portion 210A.

According to some embodiments, the ring structure 210 includes

thinner portions

216A and 216C and

thicker portions

216B and 216D, as shown in fig. 2A, 2B, and 2D. According to some embodiments, the thinner portion 216A is relative to the thinner portion 216C. According to some embodiments, the thinner portion 216A is connected between the

thicker portions

216B and 216D. According to some embodiments, the thinner portion 216C is connected between the

thicker portions

216B and 216D.

According to some embodiments, the gap G1 between the chip structures 122 extends toward the

thinner portions

216A and 216C, as shown in fig. 2B, 2C. According to some embodiments, the gap G1 is proximate to the

thinner portions

216A and 216C. According to some embodiments, the top surface 216A of the thinner portion 216A is substantially coplanar with the top surface 216B of the thicker portion 216B, as shown in fig. 2C.

Fig. 3A is a perspective schematic view of a chip package structure 300 according to some embodiments. Fig. 3B is a top view diagram illustrating the chip package structure 300 of fig. 3A without the ring structure 210, according to some embodiments. For simplicity, the underfill layer 170 and the adhesive layer a are omitted from fig. 3A.

According to some embodiments, chip package structure 300 is similar to chip package structure 200 of fig. 2C and 2E, except that recess 194B of adhesive layer 190 of fig. 3A and 3B is wider than recess 194B of adhesive layer 190 of fig. 2C and 2E, as shown in fig. 3A and 3B.

According to some embodiments, recess 194B is wider than recess 214A of lower portion 210A, as shown in fig. 3A and 3B. Thus, according to some embodiments, the portion 211A of the lower portion 210A is not bonded to the wiring substrate 160 through the adhesive layer 190. According to some embodiments, there is a gap G2 between portion 211A and wiring substrate 160.

Fig. 4A is a cross-sectional schematic diagram illustrating a chip package structure 400, according to some embodiments. Fig. 4B is a schematic top view illustrating the chip package structure 400 of fig. 4A according to some embodiments.

Fig. 4C is a perspective schematic view of the chip package structure 400 of fig. 4A according to some embodiments. For simplicity, the underfill layer 170 and the adhesive layer a are omitted from fig. 4C. Fig. 4D is a top view diagram showing the chip package structure 400 of fig. 4A without the ring structure 210, according to some embodiments. Fig. 4E is an expanded schematic view showing the loop structure 210 and adhesive layer 190 of fig. 4A, according to some embodiments.

According to some embodiments, the chip package structure 400 is similar to the chip package structure 200 of fig. 2A, 2B and 2C, except that the ring structure 210 of the chip package structure 400 further has an adhesive layer 410 located between the lower portion 210A and the upper portion 210B, as shown in fig. 4A, 4B and 4C.

According to some embodiments, the adhesive layer 410 has a trench 412 and an opening 414, as shown in fig. 4D and 4E. According to some embodiments, the device 180 is located in the trench 412. According to some embodiments, the trench 412 surrounds the opening 414. According to some embodiments, the opening 414 has an inner wall 414 a.

According to some embodiments, the inner wall 414a has a recess 414 b. According to some embodiments, each recess 414b communicates with a corresponding groove 412. According to some embodiments, the gap G1 extends toward the recess 414 b. According to some embodiments, the adhesive layer 410 is formed of a polymer material, such as epoxy or silicone.

Fig. 5 is a schematic top view showing a chip package structure 500 according to some embodiments. According to some embodiments, chip package structure 500 is similar to chip package structure 100 of fig. 1E-1, except that ring structure 510 of chip package structure 500 does not have trench 212 of chip package structure 100 of fig. 1E-1, as shown in fig. 5.

According to some embodiments, the ring-shaped structure 510 has an opening 512. According to some embodiments, the opening 512 has an inner wall 512 a. According to some embodiments, the inner wall 512a has a recess 512 b. According to some embodiments, the depressions 512b are opposite to each other. According to some embodiments, the gap G1 between the chip structures 122 extends toward the recess 512 b.

According to some embodiments, the ring-shaped structure 510 has a narrower portion 510A and a wider portion 510B. According to some embodiments, the line width W510A of narrower portion 510A is less than the line width W510B of wider portion 510B. According to some embodiments, the gaps G1 between the chip structures 122 extend toward the narrower portion 510A.

Fig. 6 is a schematic top view showing a chip package structure 600 according to some embodiments. According to some embodiments, chip package structure 600 is similar to chip package structure 500 of fig. 5 except that ring structure 610 of chip package structure 600 is divided into

portions

612 and 614 by a gap 616, as shown in fig. 6. According to some embodiments,

portions

612 and 614 are spaced apart from each other. According to some embodiments, gap G1 extends toward gap 616.

Fig. 7 is a schematic top view showing a chip package structure 700 according to some embodiments. According to some embodiments, chip package structure 700 is similar to chip package structure 100 of fig. 1E-1, except that recess 194b does not pass through

strip portions

215 and 217, as shown in fig. 7.

Fig. 8 is a schematic top view showing a chip package structure 800 according to some embodiments. According to some embodiments, chip package structure 800 is similar to chip package structure 100 of fig. 1E-1, except that recess 194b extends further into outer ring 216, as shown in fig. 8.

The processes and materials used to form

chip package structures

200, 300, 400, 500, 600, 700, and 800 may be similar or equivalent to the processes and materials used to form chip package structure 100.

According to some embodiments, a chip package structure and a method of forming the same are provided. The method for forming the chip packaging structure removes a part of the anti-warping annular structure close to the gap between the chip structures so as to reduce the anti-warping capability of the annular structure close to the gap between the chip structures. Thus, stress concentrated in the underfill layer is reduced. Because this method only removes portions of the ring-shaped structure near the gap, the anti-warp capability of the entire ring-shaped structure is substantially maintained within an acceptable range. Therefore, the yield of the chip packaging structure is improved.

The method arranges a cover member on the chip structure to reduce warpage of the chip structure, which reduces warpage of a wiring substrate carrying the chip structure. Therefore, the yield of the chip packaging structure is improved.

In some embodiments, methods of forming chip package structures are provided. The method includes disposing a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip structure are separated by a gap. The method also includes disposing a ring structure on the circuit substrate. The ring structure has a first opening, the first chip structure and the second chip structure are located in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess. In some embodiments, the step of disposing the first chip structure and the second chip structure on the circuit substrate includes disposing a package on the circuit substrate. The packaging body comprises a rewiring structure, a first chip structure, a second chip structure and an underfill layer, wherein the first chip structure, the second chip structure and the underfill layer are positioned on the rewiring structure. The underfill layer is located in the gap, between the first chip structure and the redistribution structure, and between the second chip structure and the redistribution structure. In some embodiments, the method further comprises forming an adhesive layer on the circuit substrate before disposing the ring structure on the circuit substrate. The chip structure is located on the adhesion layer. In some embodiments, the adhesive layer has a second opening below the first opening, the second opening has a second inner wall, and the second inner wall has a second recess below the first recess. In some embodiments, the first recess and the second recess have substantially the same width. In some embodiments, the second recess is wider than the first recess. In some embodiments, the annular structure has an upper portion and a lower portion, and the first recess is located in the lower portion. In some embodiments, the annular structure further comprises an adhesive layer between the upper portion and the lower portion. In some embodiments, the method further comprises disposing a lid over the first chip structure. In some embodiments, the cover is narrower than the first chip structure.

In some embodiments, methods of forming chip package structures are provided. The method includes disposing a first chip structure and a second chip structure on a circuit substrate. The first chip structure and the second chip structure are separated by a gap. The method also includes disposing a ring structure on the circuit substrate. A ring structure surrounds the first and second chip structures, the ring structure including a first thinner portion and a first thicker portion connected to each other, and a gap is adjacent to the first thinner portion. In some embodiments, the annular structure comprises a second thinner portion and a second thicker portion, the first thinner portion being interposed between and connected to the first thicker portion and the second thicker portion, and the second thinner portion being interposed between and connected to the first thicker portion and the second thicker portion. In some embodiments, the gap is proximate the second thinner portion. In some embodiments, the first thinner portion is opposite the second thinner portion. In some embodiments, the first top surface of the first thinner portion is substantially coplanar with the second top surface of the first thicker portion.

In some embodiments, a chip package structure is provided. The chip packaging structure comprises a circuit substrate. The chip packaging structure comprises a first chip structure and a second chip structure which are positioned on the circuit substrate. The first chip structure and the second chip structure are separated by a gap. The chip package structure includes a ring structure disposed on a circuit substrate. The circuit substrate is provided with an opening, the first chip structure and the second chip structure are positioned in the opening, the opening is provided with an inner wall, the inner wall is provided with a recess, and the gap extends towards the recess. In some embodiments, the ring structure has an outer ring and a first strip portion surrounding the outer ring, the first strip portion has a first end connected to the outer ring and a second end, and the recess is located in the first strip portion. In some embodiments, the recess passes through the first strip portion. In some embodiments, the ring-shaped structure has an upper portion and a lower portion, and the recess is located in the lower portion. In some embodiments, the annular structure further comprises an adhesive layer between the upper portion and the lower portion.

The components of several embodiments are summarized above so that those skilled in the art to which the disclosure pertains can more clearly understand the views of the embodiments of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Accordingly, the scope of the disclosure is to be determined by the claims that follow.

Claims

1. A method for forming a chip packaging structure comprises the following steps:

arranging a first chip structure and a second chip structure on a circuit substrate, wherein the first chip structure and the second chip are separated by a gap; and

and arranging a ring structure on the circuit substrate, wherein the ring structure is provided with a first opening, the first chip structure and the second chip structure are positioned in the first opening, the first opening is provided with a first inner wall, the first inner wall is provided with a first recess, and the gap extends towards the first recess.

2. The method of claim 1, wherein the step of disposing the first chip structure and the second chip structure on the circuit substrate comprises:

disposing a package on the circuit substrate, wherein the package comprises: a rewiring structure, and the first chip structure, the second chip structure and an underfill layer located above the rewiring structure, wherein the underfill layer is located in the gap, between the first chip structure and the rewiring structure, and between the second chip structure and the rewiring structure.

3. The method of forming a chip package structure of claim 1, further comprising:

before the ring structure is arranged on the circuit substrate, an adhesive layer is formed on the circuit substrate, wherein the chip structure is positioned on the adhesive layer.

4. The method of claim 3, wherein the adhesive layer has a second opening under the first opening, the second opening has a second inner wall, and the second inner wall has a second recess under the first recess.

5. The method of forming a chip package structure of claim 1, further comprising:

a cap is disposed over the first chip structure.

6. A method for forming a chip packaging structure comprises the following steps:

arranging a first chip structure and a second chip structure on a circuit substrate, wherein the first chip structure and the second chip structure are separated by a gap; and

disposing a ring structure on the circuit substrate, wherein the ring structure surrounds the first chip structure and the second chip structure, and the ring structure includes: a first thinner portion and a first thicker portion connected to each other, and the gap is adjacent to the first thinner portion.

7. The method for forming a chip package structure according to claim 6, wherein the ring structure comprises: a second thinner portion and a second thicker portion, the first thinner portion being interposed between and connected to the first thicker portion and the second thicker portion, and the second thinner portion being interposed between and connected to the first thicker portion and the second thicker portion.

8. A chip package structure, comprising:

a circuit substrate;

a first chip structure and a second chip structure located on the circuit substrate, wherein the first chip structure and the second chip structure are separated by a gap; and

and the annular structure is positioned on the circuit substrate, wherein the circuit substrate is provided with an opening, the first chip structure and the second chip structure are positioned in the opening, the opening is provided with an inner wall, the inner wall is provided with a recess, and the gap extends towards the recess.

9. The chip package structure according to claim 8, wherein the ring structure has an outer ring and a first bar portion surrounded by the outer ring, the first bar portion has a first end and a second end connected to the outer ring, and the recess is located in the first bar portion.

10. The chip package structure of claim 8, wherein the ring structure has an upper portion and a lower portion, and the recess is located in the lower portion.