CN113113062B - Magnetic random access memory based on 3T-3MTJ storage unit and reading method thereof - Google Patents
Magnetic random access memory based on 3T-3MTJ storage unit and reading method thereof Download PDFInfo
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- CN113113062B CN113113062B CN202110449356.3A CN202110449356A CN113113062B CN 113113062 B CN113113062 B CN 113113062B CN 202110449356 A CN202110449356 A CN 202110449356A CN 113113062 B CN113113062 B CN 113113062B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
- G11C11/2257—Word-line or row circuits
Abstract
The invention discloses a magnetic random access memory based on a 3T-3MTJ storage unit and a reading method thereof, belonging to the field of nonvolatile memories and comprising the 3T-3MTJ storage unit, a logic control circuit, a multilateral selection circuit MUX and a sensitive amplifier SA. When the multi-edge selection circuit MUX gates the S0 end and the S1 end, the NMOS transistor N3 is turned off, and the sense amplifier SA reads out the stored information of the magnetic tunnel junctions M01 and M02; when the multi-edge selection circuit MUX gates the S0 terminal and the S2 terminal, the NMOS transistor N3 is turned on, and the sense amplifier SA reads out the stored information of the magnetic tunnel junction M03 by comparing the magnitude of the currents on both sides. Therefore, one 3T-3MTJ memory cell can store 2Bit data; compared with a 2T-2MTJ memory cell, the density of the memory cell can be greatly improved, and the read-out reliability is higher compared with a 1T-1MTJ memory cell.
Description
Technical Field
The invention relates to the technical field of nonvolatile memories, in particular to a magnetic random access memory based on a 3T-3MTJ storage unit and a reading method thereof.
Background
The magnetic random access memory is a novel nonvolatile information memory and has the advantages of low power consumption, high read-write speed, high reliability, compatibility with standard CMOS (complementary metal oxide semiconductor) process and the like. With the continuous development of semiconductor technology, more recent electronic products have made higher demands on the performance of the memory, including higher density, higher read/write speed, lower power consumption, and the like.
A typical MRAM memory cell has two cell structures, 1T-1MTJ and 2T-2 MTJ. Wherein, the reading circuit of the 1T-1MTJ memory cell needs to introduce a reference cell; the reference unit is generally composed of a plurality of MTJ devices, the resistance value window between the reference unit and the data unit is smaller than the high-low resistance value window of the MTJ unit, and meanwhile, due to the temperature characteristic and the voltage bias effect of the MTJ devices, the design difficulty of the reference unit and the read error rate of a reading circuit are increased, and the reliability of the circuit is influenced. In order to solve the problems, a 2T-2MTJ memory cell structure is proposed, and a self-reference mode is adopted, two MTJ devices in a cell are always in opposite storage states, so that the memory cell structure can improve the reading reliability of a memory, but the area of a memory array can be increased by using a cell with complementary two storage states to store 1Bit data.
Disclosure of Invention
The invention aims to provide a magnetic random access memory based on a 3T-3MTJ storage unit and a reading method thereof, which have storage characteristics under the structures of a 1T-1MTJ unit and a 2T-2MTJ unit in reliability and density.
In order to solve the technical problem, the invention provides a magnetic random access memory based on a 3T-3MTJ storage unit, which comprises the 3T-3MTJ storage unit, a logic control circuit, a multi-edge selection circuit MUX and a sense amplifier SA;
the multilateral selection circuit MUX selects to read out data stored by the 3T-3MTJ storage unit;
the sensitive amplifier SA is connected with the multi-edge selection circuit MUX and used for amplifying and reading data signals;
the logic control circuit is respectively connected with the sense amplifier SA, the multi-edge selection circuit MUX and the 3T-3MTJ storage unit through an SAE line, a SEL line and a word line WL.
Optionally, the 3T-3MTJ memory cell includes a first 1T-1MTJ cell, a second 1T-1MTJ cell, a third 1T-1MTJ cell, and an NMOS transistor N3; the first 1T-1MTJ cell includes an NMOS transistor N0 magnetic tunnel junction M01; the second 1T-1MTJ cell includes an NMOS transistor N1 magnetic tunnel junction M02; the third 1T-1MTJ cell includes an NMOS transistor N2 magnetic tunnel junction M03;
one end of the magnetic tunnel junction M01 is connected with the drain end of an NMOS tube N0, and the other end is connected with the S0 end of the multilateral selection circuit MUX; one end of the magnetic tunnel junction M02 is connected with the drain end of an NMOS tube N1, and the other end is connected with the S1 end of the multilateral selection circuit MUX; one end of the magnetic tunnel junction M03 is connected with the drain end of an NMOS tube N2, and the other end is connected with the S2 end of the multilateral selection circuit MUX;
the source of the NMOS transistor N3 is connected to the S0 terminal of the multi-edge selection circuit MUX, the drain is connected to the S1 terminal of the multi-edge selection circuit MUX, and the gate is connected to the SE switch signal terminal of the logic control circuit.
Optionally, the magnetic tunnel junctions M01 and M02 are reference cells, and store information of 1 Bit; the magnetic tunnel junction M03 is a data cell that stores 1Bit of information.
Optionally, gates of the NMOS transistor N0, the NMOS transistor N1, and the NMOS transistor N2 are all connected to a word line WL, sources are all connected to a source line SL, and the source line SL is connected to a ground GND when reading is performed.
The invention also provides a reading method of the magnetic random access memory based on the 3T-3MTJ storage unit, which comprises the following steps:
when the multi-edge selection circuit MUX gates the S0 end and the S1 end, the NMOS tube N3 is turned off, and the sense amplifier SA reads out the stored information of the magnetic tunnel junction M01;
when the multi-edge selection circuit MUX gates the S0 end and the S2 end, the NMOS tube N3 is conducted, and the sense amplifier SA compares the current of the two sides to read out the stored information of the magnetic tunnel junction M03.
The magnetic random access memory based on the 3T-3MTJ storage unit and the reading method thereof comprise the 3T-3MTJ storage unit, a logic control circuit, a multi-edge selection circuit MUX and a sensitive amplifier SA. When the multi-edge selection circuit MUX gates the S0 end and the S1 end, the NMOS transistor N3 is turned off, and the sense amplifier SA reads out the stored information of the magnetic tunnel junctions M01 and M02; when the multi-edge selection circuit MUX gates the S0 terminal and the S2 terminal, the NMOS transistor N3 is turned on, and the sense amplifier SA reads out the stored information of the magnetic tunnel junction M03 by comparing the magnitude of the currents on both sides. Therefore, one 3T-3MTJ memory cell can store 2Bit data; compared with a 2T-2MTJ memory cell, the density of the memory cell can be greatly improved, and the read-out reliability is higher compared with a 1T-1MTJ memory cell.
Drawings
FIG. 1 is a schematic structural diagram of a 3T-3MTJ memory cell-based MRAM according to the present invention;
FIG. 2 is a waveform diagram illustrating the operation of a read circuit of a magnetic random access memory based on a 3T-3MTJ memory cell according to the present invention;
FIG. 3 is a schematic diagram of the reading process of the magnetic tunnel junction M01 and the magnetic tunnel junction M02 as data storage cells;
FIG. 4 is a schematic diagram of a read process of the magnetic tunnel junction M03 as a data storage cell.
Detailed Description
The following describes a 3T-3MTJ memory cell-based magnetic random access memory and a reading method thereof in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a magnetic random access memory based on a 3T-3MTJ (magnetic tunnel junction) storage unit, which has a structure shown in figure 1 and comprises the 3T-3MTJ storage unit, a logic control circuit, a multi-edge selection circuit MUX (multiplexer) and a sense amplifier SA (SA); the multilateral selection circuit MUX selects to read out data stored by the 3T-3MTJ storage unit; the sensitive amplifier SA is connected with the multi-edge selection circuit MUX and used for amplifying and reading data signals; the logic control circuit is respectively connected with the sense amplifier SA, the multi-edge selection circuit MUX and the 3T-3MTJ storage unit through an SAE line, a SEL line and a word line WL. The magnetic tunnel junctions M01 and M02 are reference cells and store 1Bit of information; the magnetic tunnel junction M03 is a data cell that stores 1Bit of information.
With continued reference to FIG. 1, the 3T-3MTJ memory cell includes a first 1T-1MTJ cell, a second 1T-1MTJ cell, a third 1T-1MTJ cell, and an NMOS transistor N3; the first 1T-1MTJ cell includes an NMOS transistor N0 magnetic tunnel junction M01; the second 1T-1MTJ cell includes an NMOS transistor N1 magnetic tunnel junction M02; the third 1T-1MTJ cell includes an NMOS transistor N2 magnetic tunnel junction M03; one end of the magnetic tunnel junction M01 is connected with the drain end of an NMOS tube N0, and the other end is connected with the S0 end of the multilateral selection circuit MUX; one end of the magnetic tunnel junction M02 is connected with the drain end of an NMOS tube N1, and the other end is connected with the S1 end of the multilateral selection circuit MUX; one end of the magnetic tunnel junction M03 is connected with the drain terminal of the NMOS transistor N2, the other end is connected with the S2 terminal of the multi-edge selection circuit MUX, and current difference is formed when current flows through the S0 terminal, the S1 terminal and the S2 terminal. The source of the NMOS transistor N3 is connected to the S0 terminal of the multi-edge selection circuit MUX, the drain is connected to the S1 terminal of the multi-edge selection circuit MUX, and the gate is connected to the SE switch signal terminal of the logic control circuit. The gates of the NMOS transistor N0, the NMOS transistor N1, and the NMOS transistor N2 are all connected to a word line WL, the sources are all connected to a source line SL (not shown in the figure), and the source line SL is connected to a ground GND when reading.
The magnetic tunnel junction has two states, Parallel (Parallel) and Antiparallel (Antiparallel), Parallel denoted as P and Antiparallel denoted as AP, exhibiting a low resistance state and a high resistance state, respectively. The states of the magnetic tunnel junction M01 and the magnetic tunnel junction M02 are denoted by "0" when they are P and AP, respectively, and the states of the magnetic tunnel junction M01 and the magnetic tunnel junction M02 are denoted by "1" when they are AP and P, respectively. The state of the magnetic tunnel junction M03 is denoted as "0" or "1" when P or AP, respectively. As shown in Table 1, the 3T-3MTJ memory cell has 4 data information states, while the 2T-2MTJ memory cell has 2 data information states, and the 3T-3MTJ memory cell has a higher storage density.
TABLE 13 data information Table for T-3MTJ cell
The working waveforms are shown in fig. 2, and a read-out method of the magnetic random access memory based on the 3T-3MTJ memory cell can be expressed as follows:
(1) when the multi-edge selection circuit MUX gates the end S0 and the end S1, the NMOS transistor N3 is turned off, and since the magnetic tunnel junctions M01 and M02 always present opposite storage states, a large resistance value window is formed between the magnetic tunnel junction M01 and the magnetic tunnel junction M02, a current difference can be formed between the end S0 and the end S1, the storage information of the magnetic tunnel junction M01 and the magnetic tunnel junction M02 is read out through the amplification of the sense amplifier SA, the working principle is as shown in FIG. 3, and the data read in the method has high reliability;
(2) when the multi-edge selection circuit MUX gates the S0 end and the S2 end, the NMOS transistor N3 is conducted, the magnetic tunnel junction M01 and the magnetic tunnel junction M02 are used as reference units, the sense amplifier SA reads out the stored information of the magnetic tunnel junction M03 by comparing the current magnitude of the two sides of the S0 end and the S2 end, and the working principle is as shown in FIG. 4. Compared with a reading circuit of a 1T-1MTJ (magnetic tunnel junction) storage unit architecture, a reference unit in the reading circuit only participates in the data reading process of a 3T-3MTJ unit, and the probability of occurrence of reading interference is low; meanwhile, the reference cell is also written as a data cell, and the data information is read out in the first stage, as shown in fig. 2, so that the reliability of the reference cell can be ensured.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (4)
1. A magnetic random access memory based on a 3T-3MTJ memory cell is characterized by comprising the 3T-3MTJ memory cell, a logic control circuit, a multi-edge selection circuit MUX and a sense amplifier SA;
the multilateral selection circuit MUX selects to read out data stored by the 3T-3MTJ storage unit;
the sensitive amplifier SA is connected with the multi-edge selection circuit MUX and used for amplifying and reading data signals;
the logic control circuit is respectively connected with the sense amplifier SA, the multi-edge selection circuit MUX and the 3T-3MTJ storage unit through an SAE line, a SEL line and a word line WL;
the 3T-3MTJ memory cell comprises a first 1T-1MTJ cell, a second 1T-1MTJ cell, a third 1T-1MTJ cell, and an NMOS transistor N3; the first 1T-1MTJ cell includes an NMOS transistor N0 and a magnetic tunnel junction M01; the second 1T-1MTJ cell includes an NMOS transistor N1 and a magnetic tunnel junction M02; the third 1T-1MTJ cell includes an NMOS transistor N2 and a magnetic tunnel junction M03; one end of the magnetic tunnel junction M01 is connected with the drain end of an NMOS tube N0, and the other end is connected with the S0 end of the multilateral selection circuit MUX; one end of the magnetic tunnel junction M02 is connected with the drain end of an NMOS tube N1, and the other end is connected with the S1 end of the multilateral selection circuit MUX; one end of the magnetic tunnel junction M03 is connected with the drain end of an NMOS tube N2, and the other end is connected with the S2 end of the multilateral selection circuit MUX;
the source of the NMOS transistor N3 is connected to the S0 terminal of the multi-edge selection circuit MUX, the drain is connected to the S1 terminal of the multi-edge selection circuit MUX, and the gate is connected to the SE switch signal terminal of the logic control circuit.
2. The 3T-3MTJ memory cell-based magnetic random access memory of claim 1, wherein the magnetic tunnel junctions M01 and M02 are reference cells, storing 1Bit of information; the magnetic tunnel junction M03 is a data cell that stores 1Bit of information.
3. The 3T-3MTJ memory cell based magnetic random access memory of claim 2 wherein the gates of NMOS transistor N0, NMOS transistor N1 and NMOS transistor N2 are all connected to word line WL, the sources are all connected to source line SL, and source line SL is connected to ground GND when reading is performed.
4. A method for reading a 3T-3MTJ memory cell based magnetic random access memory according to any of claims 1 to 3, wherein the method comprises:
when the multi-edge selection circuit MUX gates the S0 end and the S1 end, the NMOS tube N3 is turned off, and the sense amplifier SA reads out the stored information of the magnetic tunnel junction M01;
when the multi-edge selection circuit MUX gates the S0 end and the S2 end, the NMOS tube N3 is conducted, and the sense amplifier SA compares the current of the two sides to read out the stored information of the magnetic tunnel junction M03.
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