CN113111620A - Semiconductor circuit yield prediction method and device - Google Patents

Abstract

A method for predicting yield of semiconductor circuit comprises setting the lowest yield P of semiconductor circuit_crit(ii) a With P_critSearching for a fault region of the circuit as a guide; recording the searched fault areas, establishing a response surface in each fault area, and establishing a local response surface model; carrying out numerical integration on the constructed local response surface model to obtain the fault rate P of the circuit_fThen the yield P of the circuit_yield＝1‑P_f。

Description

Semiconductor circuit yield prediction method and device

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor circuit yield prediction method and device.

Background

Along with the guidance of moore's law, the integration level of transistors in integrated circuits is rapidly increasing as the device size is made smaller. In 1971, the first microprocessor 4004 of Intel corporation comprised only 2300 transistors; in 2010, Intel corporation's microprocessor Core i7, contained 20 hundred million transistors; in 2019, processor A13, by Apple Inc., was already capable of containing 85 billion transistors. However, as semiconductor manufacturing processes enter the deep nanometer stage, guaranteeing high precision and high reliability of modern integrated circuit fabrication becomes extremely challenging due to inevitable uncertainties and process variations.

Uncertainties in the manufacturing process, as well as variations in supply voltage and operating temperature, are three major sources of variation in circuit design. The voltage and temperature variations are dynamic and change over time as they depend on the operating environment. While the uncertainty due to process fluctuations is "static" (time-zero) once the circuit is fabricated. This "static" process variation is believed to be a major cause of circuit performance fluctuations and resulting circuit yield loss. Meanwhile, as the integrated circuit is continuously aged during use, the aging process of the integrated circuit is another cause of circuit yield loss along with the increase of the use time.

Time-independent process fluctuations are mainly caused by uncertainties in the manufacturing processes of chemical mechanical polishing, etching, photolithography, etc. The differences between design and fabrication result in differences between ideal and actual fabricated circuits. For example, the designed physical parameters such as channel width, length, oxide thickness, etc. may change in practical situations. Variations in these design parameters can result in variations in the threshold voltage, causing large variations in circuit behavior, such as leakage power, timing delays, output swing, etc. As transistor dimensions decrease, the magnitude of the process parameter variations continues to increase. The superposition of all transistor variations in a circuit can affect the performance of the circuit, further affecting yield.

To assist designers in analyzing the impact of process parameter variations on integrated circuit circuits, typically below 90nm, large process plants provide a library of Monte Carlo models of transistors whose parameters are derived from a large number of device analysis tests. The Monte Carlo model is applied to the actual circuit design, so that the sensitivity of the circuit to device parameters can be obtained, and the robustness of the circuit can be obtained. The monte carlo method is a simulation method that approximates a probability by an experiment. For the yield prediction problem, what is required is the yield (or failure rate) of the circuit. After a large number of circuit simulation experiments, the frequency at which the circuit can work normally (or cannot work normally) is used as the yield (or failure rate). Wherein, in order to simulate the influence of the process fluctuation on the circuit parameters, the values of the circuit parameters obey certain probability distribution. The values of the circuit parameters are randomly sampled according to probability distribution each time.

Disclosure of Invention

The invention provides a semiconductor circuit yield prediction method, which aims to solve the problem that the conventional yield prediction acceleration algorithm cannot meet the high yield (more than 7sigma) required by a large-scale integrated circuit under the condition of ensuring the precision.

In one embodiment of the present invention, a method for predicting yield of semiconductor circuit comprises setting a minimum yield P of semiconductor circuit_crit；

With P_critSearching for a fault region of the circuit as a guide;

recording the searched fault areas, establishing a response surface in each fault area, and establishing a local response surface model;

carrying out numerical integration on the constructed local response surface model to obtain the fault rate P of the circuit_fThen the yield P of the circuit_yield＝1-P_f。

The method is based on the characteristic of high accuracy of the response surface model, and the yield of the circuit is accurately predicted in the circuit design stage. Because the construction cost of the complete response surface model is very high, the invention adopts an algorithm to search a local area needing to construct the response surface model and optimizes the sampling method when constructing the response surface. The effect of constructing the local response surface with low cost is achieved.

Compared with the error of the traditional Monte Carlo method, the high-accuracy yield rapid prediction algorithm provided by the invention can be controlled within 1 percent, and is lower than the existing method. And the Monte Carlo method can be accelerated by millions times. The yield prediction method not only can consider the influence of the reliability problem irrelevant to the time on the yield, but also can simultaneously consider the yield loss caused by the reliability problem relevant to the time. The yield predicted by the method can further guide the circuit design to meet the requirement of high yield.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

FIG. 1 is a flowchart illustrating a method for predicting yield of a semiconductor circuit according to one embodiment of the present invention.

FIG. 2 is a graph showing the variation of probability predicted by the method of the present invention with the number of simulations.

FIG. 3 is a schematic error diagram of the present invention versus Monte Carlo.

FIG. 4 is a schematic diagram of a test circuit according to an embodiment of the invention.

Detailed Description

For highly integrated memories, the conventional method is not applicable. For example, if a memory with 8Gb size is desired to achieve a yield of 99.9%, the failure rate of a single memory cell is required to be no higher than 1.4E-14, i.e., the yield is required to achieve 7.6 sigma. This means that the conventional Monte Carlo method requires at least one million circuit simulations to ensure that the circuit yield reaches such a high level, which is not possible in reality.

The key problem with monte carlo being difficult to predict high yield is that a circuit failure condition will only occur when the tail of the probability distribution to which the parameter is subjected is sampled. However, random sampling of the distribution subject to the parameters is difficult to sample the tail of the probability distribution, which results in a situation that circuit failure occurs through a large number of experiments, so that the frequency can be used as the probability of failure, and the yield can be obtained by subtracting the probability of failure from 1. In order to quickly and accurately predict yield in the circuit design stage, many acceleration algorithms have been proposed. Current mainstream methods can be divided into three categories: importance Sampling (Importance Sampling) based on the Monte Carlo method, Response Surface Model (Response Surface Model) of the non-Monte Carlo method, and Statistical Blockade (Statistical Block) as a classification method.

Importance sampling is a monte carlo-based method, and monte carlo experiments are performed on new distributions by artificially changing the probability distribution of sampling. The probability that the selected new probability distribution appears at the tail is larger, so that the circuit fault condition can occur only by a small amount of experiments, and the frequency is taken as the probability. The response surface model is a non-Monte Carlo method, and a response surface of the circuit performance is constructed by uniformly sampling probability distribution. Statistical lockout is a method to replace circuit simulation software. The core idea of statistical lockout is to simulate only possible failure points, thereby reducing the number of circuit Simulator (SPICE) simulations to speed up. Firstly, a classifier is trained by a few sample points, and whether a circuit fails or not can be judged according to input process parameter values, so that the function of replacing SPICE is achieved. During the experiment, a large number of samples are generated and taken into the classifier. And (4) the sample points which are considered as faults by the classifier are brought into SPICE for simulation.

Statistical blockade was proposed by a.singhee et al in 2007. This method can reduce the number of sample points that need to be simulated by screening the sample points in advance by the classifier. However, as circuit complexity increases and yield requirements increase, it becomes difficult to train an accurate classifier with the number of samples that can be tolerated. This method has therefore rarely been applied or improved today.

The importance sampling method theoretically can estimate the yield with the least number of sample points, and thus has been continuously improved from the proposition to the present. However, this method still has disadvantages in practical use. For circuits under current technology, there are often multiple failure regions. It is difficult to cover all the fault areas with a new sampling function and therefore the accuracy of the method is affected.

Weckx P et al proposed a response surface technique in 2014, which constructs a response surface by spatially uniform sampling of the entire sample values. The corresponding surface model can accurately measure the yield, but the sample number required for constructing the response surface has an exponential relation with the dimensionality, so that the response surface is difficult to deal with the high-dimensional problem.

In order to solve the defects of the prior art and quickly and accurately predict the yield, the embodiment of the invention is provided, and the overall algorithm of the technical scheme is shown in fig. 1 based on the minimum response surface yield prediction method. Firstly, an input parameter probability equipotential surface is constructed, and the equipotential surface is sampled and simulated. Constructing a circuit performance response surface, and obtaining the lowest requirement P for the yield of a certain circuit in practical application according to the situation_crit. With P_critThe defective area is searched as an index, and is defined as a sample space capable of causing a circuit failure. And recording the searched fault areas, and establishing a response surface in each fault area. Because only part of the sample space is constructed, the constructed response surface model can be called a local response surface model. And because the corresponding surface is constructed only on part of the sample space, the number of required samples is greatly reduced compared with the whole sample space construction response surface. Finally, the fault rate P of the circuit can be obtained by carrying out numerical integration on the constructed local response surface_fYield of circuit P_yield＝1-P_f。

For searching for the fault area, searching for the fault area through an algorithm is crucial to yield prediction. Only if all the fault areas are searched, the accuracy of the result can be ensured. The pseudo algorithm for searching for a defective area is as follows.

Inputting: x ═ X₁x₂...x_M]^TM-dimension, which is used to represent parameters that affect circuit yield. The joint probability density f (x) of the parameters is a known quantity, measured by experimental data. Minimum requirement P for circuit yield_critAnd is specified by human. The circuit performance concerned in actual production is y, and the critical point for artificially specifying whether the circuit can normally work is y_crit。

And (3) outputting: the area in the parameter sample space where a circuit failure can arise. Among them are mentioned that there are,

1, considering that the value of a common i-dimensional parameter deviates from the value of parameter design, and until M cycles, for i is 1;

2, sampling the i-dimensional parameters for N times, wherein the sample point is

Keeping the probability of the sample point same during sampling, wherein the for start probability is P_highProbability P until final stop_low；

3, spotting the sample

Carrying in circuit simulation simulator to carry out simulation to obtain circuit performance

It is reacted with y_critComparing to judge whether the circuit is in fault;

4, if the circuit is in fault, recording the value of the sample point causing the fault, namely the probability of the sample point

And selecting the largest value as P_max；

5, ending for;

recording all sample points which can cause circuit faults, and dividing regions;

and ending the for.

The parameters in the above pseudo-algorithm are described next. i represents that several dimensions of the parameters in the M dimensions are considered to be changed. This may occur for some critical parameter. Namely, only the values of the key parameters are different from the normal values, and the values of the rest parameters are uniform and the same as the normal values, but the circuit still breaks down. P_highAnd P_lowThe range of the sampling interval is determined, and the accuracy is higher when the range is larger. P_maxWhen the i-dimensional parameter changes, the probability value of the sample with the highest probability in the sample points which can cause the fault is obtained. In fact, when the probability of a fault point is compared to the probability P of the sample point most likely to cause the fault_maxWhen the probability of the sample points is small to a certain value, the probability contribution of the sample points to the whole circuit fault event is very low and can even be ignoredSlightly disregarded. N is the number of samples sampled by the same sample probability, and the coverage of a sample space is larger when the number of the sampled samples is larger. When i takes different values P_maxThere will also be different values, when i is P under some value conditions_maxThis i value can be left out much smaller than otherwise.

For constructing the local response surface, after the fault area is found through an algorithm, the response surface can be constructed in the fault area. The construction of the response surface is also crucial to the accuracy of the final prediction. The finer the response surface is constructed, i.e. the greater the number of samples sampled, the more accurate the prediction results become. The pseudo algorithm for constructing the local response surface is as follows:

inputting: sample point set X sampled in fault area algorithm and capable of causing circuit fault_f，X_fCorresponding probability P (X)_f) Fault region omega in sample space_uU1, 2, U being the total number of failure zones.

And (3) outputting: a local response surface. Among them are mentioned that there are,

1, search for Ω_uThe point with the highest probability is marked as P_umax，u＝1,2,...,U

2，forP_sample,U＝aσ+P_umaxUp to P_sample,U＝P_umax-bσ

3 at P_sample,UDown-sampling, wherein the number of samples sampled in each dimension is N;

4, mixing the sample X⁽ⁿ⁾N is 1, N is simulated to obtain circuit performance y⁽ⁿ⁾

And 5, ending for.

Here, the non-analytic expression is used in constructing the response surface, and the same effect can be achieved by replacing the analytic expression.

The significance of the parameters in constructing the local response surface algorithm is described next. P_umaxThe probability of the largest fault sample measured by each fault area when searching for the fault area. Theoretically, only a response surface needs to be constructed in the fault area, but in order to improve accuracy and prevent the missing probability when searching the fault area, the probability is higherLarge fault point, initial response surface construction probability slightly greater than P_umax. Parameter a controls the initial sampling probability ratio P_umaxLarger, the larger the parameter a, the greater the sampling probability representing the start. The parameter b controls the probability of terminating the sample, which can be understood as being much smaller than P_umaxThe probability of (c). The number of samples N per dimension may be fixed-pitch or non-fixed-pitch. The sampling of the non-fixed region can be densely sampled in a high probability part and sparsely sampled in a low probability part. Since the low probability part contributes less to the overall failure probability as a whole.

For the calculation yield, the failure rate can be calculated after a local response surface exists, and P is obtained through numerical integration calculation_f. Let the probability density function of circuit performance failure be g (x), the joint probability density function of parameters f (ζ). The probability density function to which the circuit performance is obeyed can be obtained by integrating the parameter joint probability density function through the formula (3-1).

Further integrate g (x) to get cumulative probability function G (x) of circuit performance fault

After G (x) is present, the failure rate P can be known_f. Looking at equation (3-2) it can be seen that the integral computation probability requires an infinite number of sample points. In practical algorithms, a minimum sampling probability needs to be set, and this also causes errors. The error depends on the setting of the parameter b, the larger b the lower the lowest sampling probability, and thus the smaller the error. The error is calculated by:

final circuit yield P_yieldIt can be calculated:

P_yield＝1-P_f (3-4)

here, the probability is calculated by using the riemann-steuer jess integral, and the same effect can be achieved by using other numerical integration.

The integration level of chips is high nowadays, and in order to ensure the yield of the whole chip, the yield requirement of a single device in the chip reaches 7.6sigma, namely the failure rate cannot be higher than 1.4E-14. The chip yield is required to be so high, and the manufacturing cost of the chip is also rapidly increased. Therefore, the yield after the circuit is manufactured must be predicted in the circuit design stage. If the yield does not meet the standard, the design of the circuit needs to be further improved. Therefore, the reverse work of the chip can be reduced to the maximum extent, and the design cost of the chip is suddenly reduced. Also, chips may suffer from long-term reliability issues after they are manufactured, such as long-term operation of the chip or extremely high operating temperatures. These problems need to be taken into account in the circuit design. The traditional Monte Carlo method for predicting yield needs millions of experiments to predict the yield of 7.6 sigma. This is clearly not practical. In view of this problem, the present invention provides a method for predicting yield with high accuracy and speed.

The invention has the advantage that the speed of the traditional method is greatly increased under the condition of ensuring the accuracy by constructing the local response surface. The method is tested in SRAM, and for the condition that the yield rate requires 2.5sigma, FIG. 2 shows the relation that the probability predicted by the method of the invention changes with the simulation times. It can be seen from the figure that the method only needs 100 times of simulation, while the Monte Carlo method needs 10000 times of simulation, and the error of the method compared with the Monte Carlo method is only 0.6%; the comparison between the prior art and the yield requirement of 4.5sigma is shown in fig. 3. It can be seen from the figure that the error of the method is the smallest of all known methods and the method requires relatively little time; for the condition that the yield rate requires 7.5sigma, the method only needs 4856 circuit simulations, is about 2E6 times faster than the traditional Monte Carlo method, and has an error of only 0.2% compared with the Monte Carlo method. It should be noted that the present invention is a general algorithm and is not limited by the use condition. Any parameter that affects the yield of the chip during the manufacturing process and the use process of the chip can be used as an input variable. Therefore, the method can be suitable for all scenes of predicting the yield of the chip, and the design of the circuit can be guided by the change of the yield along with the parameter value.

The beneficial effects of the invention include:

1. the invention provides a universal algorithm capable of rapidly predicting the yield of a circuit in a circuit design stage on the premise of ensuring the accuracy.

2. The proposed algorithm is independent of circuit structure and can be used to predict yield after any circuit has been produced.

3. In addition, the method can consider any scene which can affect the yield. Including time-independent reliability issues during the manufacturing process and yield loss due to time-dependent reliability issues during use after manufacturing is complete.

4. The method can be easily reproduced without a highly configured computer, and the time required by the method can be reduced by adding a parallel computing mode.

To verify the effect of the present invention, the following verification tests were performed.

(1) The circuit of the design (shown in fig. 4, taking SRAM as an example) is selected, and it is considered that a certain critical performance (SNM as an example) of the circuit is affected by the reliability problem and deviates from the circuit performance expected by the design.

(2) The reliability problem is considered to reflect which parameters are affected in the circuit (taking transistor threshold voltage as an example). The distribution to which the transistor threshold voltage obeys is sampled. The lowest yield requirement (in the example of 4 sigma) is determined. The distribution of threshold voltages is sampled such that the probability of a sample point is 4 sigma. And observing whether the fault point exists or not, finding that the fault point does not exist, continuously reducing the probability of the sample point to be 5sigma (taking 1sigma reduction every time as an example), and continuously observing whether the fault point exists or not. If a fault point is found, 1sigma is reduced continuously until a minimum probability (8 sigma for example) is specified artificially.

(3) The sample points causing the fault are divided into areas (taking 3 areas as an example), and the construction of the response surface is carried out in each area (taking 10 sample points sampled in each dimension as an example). The start probability of the response surface area needs to be fixed to the probability of a non-failure point (4 sigma for example). The probability interval for each dimension of sampling can be specified artificially (taking uniform sampling as an example).

(4) And screening out response surface areas with performance not meeting the standard in the constructed circuit performance (SNM) response surface, performing numerical integration to obtain a fault rate, and further converting to obtain a yield.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (6)

1. A method for predicting yield of semiconductor circuit, the method comprises the steps of,

setting the minimum yield P of the semiconductor circuit_crit；

With P_critSearching for a fault region of the circuit as a guide;

recording the searched fault areas, establishing a response surface in each fault area, and establishing a local response surface model;

carrying out numerical integration on the constructed local response surface model to obtain the fault rate P of the circuit_fThen the yield P of the circuit_yield＝1-P_f。

2. The method of claim 1, wherein the input of the search fault region model is X ═ X₁x₂...x_M]^TThe parameter affecting the circuit yield is expressed by M, the combined probability density f (x) of the parameter is a known quantity, the circuit performance is y, and the critical point of the normal operation of the circuit is y_crit，

The output of the search fault region model is the region of the circuit causing the circuit fault.

3. The method of claim 2, wherein the input of the partial response surface model is a set of sample points X sampled during the search for the failure region and causing the circuit failure_f，X_fCorresponding probability P (X)_f) Fault region omega in sample space_uU1, 2, U being the total number of failure zones.

4. The method of claim 3, wherein the yield calculation process comprises,

let the probability density function of circuit performance failure be g (x), the joint probability density function of parameters f (ζ),

the probability density function obeyed by the circuit performance can be obtained by integrating the parameter joint probability density function through the formula (3-1),

further integrating g (x) to obtain the cumulative probability function G (x) of circuit performance fault,

according to G (x) available failure rate P_fG (x), circuit yield P_yieldIs composed of

P_yield＝1-P_f (3-4)。

5. A semiconductor circuit yield prediction device, the device comprising a memory; and

a processor coupled to the memory, the processor configured to execute instructions stored in the memory, the processor to:

setting the minimum yield P of the semiconductor circuit_crit；

With P_critSearching for a fault region of the circuit as a guide;

recording the searched fault areas, establishing a response surface in each fault area, and establishing a local response surface model;

carrying out numerical integration on the constructed local response surface model to obtain the fault rate P of the circuit_fThen the yield P of the circuit_yield＝1-P_f。

6. A storage medium on which a computer program is stored which, when executed by a processor, carries out the method of any one of claims 1 to 4.

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