CN113098673A - Full duplex communication device based on serial link mirror image cache - Google Patents
Full duplex communication device based on serial link mirror image cache Download PDFInfo
- Publication number
- CN113098673A CN113098673A CN202110325360.9A CN202110325360A CN113098673A CN 113098673 A CN113098673 A CN 113098673A CN 202110325360 A CN202110325360 A CN 202110325360A CN 113098673 A CN113098673 A CN 113098673A
- Authority
- CN
- China
- Prior art keywords
- receiving
- sending
- controller
- data frame
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9057—Arrangements for supporting packet reassembly or resequencing
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Environmental & Geological Engineering (AREA)
- Communication Control (AREA)
Abstract
The invention discloses a full-duplex communication device based on serial link mirror image cache, which consists of two FPGA chips, wherein each FPGA chip comprises a double-port RAM, a sending controller, a sending link layer, a sending high-speed serial interface, a receiving link layer and a receiving controller, wherein the sending high-speed serial interface on one FPGA chip is connected to the receiving high-speed serial interface on the other FPGA chip through an inter-board PCB (printed circuit board) connecting line; the light-weight upper protocol stack based on the mirror image cache is provided through the double-port RAM, the protocol compatibility is high, the safety is high, the occupied resource is few, the power consumption is low, and the method can be used for serial data communication between the FPGAs of the same manufacturer or different chip manufacturers.
Description
Technical Field
The invention belongs to the field of communication, and relates to a full-duplex communication device based on serial link mirror image caching.
Background
In avionic products, a large number of FPGAs are used for data communication, and high-speed serial data interconnection communication is usually performed among FPGA chips by adopting bus protocols such as SRIO, PCIE, AURORA and the like. SRIO and PCIE are suitable for data communication of networking among multiple chips, the protocol is complex, more FPGA resources are occupied, communication can be performed only after software configuration and maintenance are needed, and the danger of application layer breakdown caused by bottom link failure exists; AURORA is a point-to-point communication protocol developed by Xilinx corporation, streaming data based communication, does not provide a complete communication protocol stack, and is not compatible with shared cache based communication used in large numbers in avionics.
Disclosure of Invention
The invention aims to provide a full-duplex communication device based on serial link mirror image cache, wherein a bottom layer physical link adopts a mode of interconnection of PCB (printed circuit board) wires among boards, a light upper layer protocol stack based on mirror image cache is provided through a double-port RAM (random access memory), the protocol compatibility is high, the safety is high, the occupied resource is less, the power consumption is low, and the full-duplex communication device can be used for serial data communication among FPGA (field programmable gate array) of the same manufacturer or different chip manufacturers.
The invention aims to be realized by the following technical scheme:
a full-duplex communication device based on serial link mirror image cache comprises two FPGA chips, wherein each FPGA chip comprises a double-port RAM, a sending controller, a sending link layer, a sending high-speed serial interface, a receiving link layer and a receiving controller, wherein the sending high-speed serial interface on one FPGA chip is connected to the receiving high-speed serial interface on the other FPGA chip through an inter-board PCB (printed circuit board) connecting line;
the dual-port RAM is divided into a sending storage area and a receiving storage area, a sending state register and a receiving state register are arranged in a designated area, the sending storage area is used for storing a data block to be sent, and the size, the block sequence number and the sending state of the data block to be sent are recorded on the sending state register; the receiving storage area is used for storing the received data blocks and recording the size, the block sequence number and the receiving state of the received data blocks on the receiving state register;
the sending controller periodically acquires the information of the sending state register through a preset refreshing period, judges whether a new data block is ready to be sent in the dual-port RAM or not through the sending state, if so, the sending state register acquires the size and the block number of the data block, reads the data block to be sent from the dual-port RAM, marks the block number on the data block, and then forms a data frame to be sent to a sending link layer;
the data frame is transmitted to the high-speed serial interface through the transmitting link layer and then transmitted to the high-speed serial interface on the other FPGA chip, and the transmitting process is completed; the data frame entering the receiving high-speed serial interface is transmitted to a receiving controller after passing through a receiving link layer;
the receiving controller takes out the data block from the received data frame and writes the data block into the dual-port RAM, and marks the size, the block sequence number and the receiving state of the related data block in the receiving state register.
Further, before data frame transmission, a sending controller on the FPGA chip is powered on and started up, and a handshake request signal is continuously sent; after a receiving controller on the later-powered FPGA chip receives the handshake request signal, a sending controller sends a handshake response signal; after a receiving controller of the FPGA chip which is powered on firstly receives the handshake response signal, a sending controller sends a response receiving signal, and the sending controller enters a synchronous state to send a synchronous signal; and after receiving the response receiving signal, the receiving controller of the later-powered FPGA chip also enters a synchronous state, and the sending controller sends a synchronous signal.
Furthermore, the number of credits is negotiated between the two FPGA chips in advance, a sending controller on the FPGA chip as a data sending party consumes one credit every time a data frame is sent, and a receiving controller recovers one credit every time a receiving response message is received; once the credit is exhausted, the sending controller stops sending the data frame and waits for the credit to recover; and meanwhile, the receiving controller performs timing, and if the data frame is not received after the timing is over, the sending controller sends a reset command to the other FPGA chip to perform link reset.
Further, two transmission channels are arranged on a sending link layer and a receiving link layer which are connected in series, a data frame sent by a sending controller can be transmitted in the two transmission channels, and a receiving controller carries out redundancy check according to a redundancy check rule after receiving the data frame.
Further, the sending controller divides the data block taken out from the double-port RAM into a plurality of small pieces, and each small piece is marked with a block serial number and a piece serial number to form a data frame for sending; and after the receiving controller receives the data frame, restoring the data block through the sequence of the chip serial numbers of each small chip, and if the sequence of the chip serial numbers is wrong, discarding the data block as a whole.
Further, the sending controller fills small pieces of CRC codes in each data frame, the receiving controller calculates the CRC codes after receiving the data frames, if the check is correct, the data are stored, and if the check is wrong, the data frames are discarded.
Further, dividing a receiving storage area of the dual-port RAM into a receiving area A and a receiving area B; setting a transmission channel A and a transmission channel B on a sending link layer and a receiving link layer which are connected in series; the receiving controller stores the data frame transmitted by the transmission channel A into the receiving area A, stores the data frame transmitted by the transmission channel B into the receiving area B, and compares the data blocks on the receiving area A and the receiving area B, so that the received data frame is verified in a high integrity mode.
Further, when the error rate exceeds a preset threshold value, the receiving controller counts, and when the counting is full, the sending controller sends a reset command to reset the link and report error information.
Further, the receiving controller may count the number of errors according to different errors of the data frame.
The invention has the beneficial effects that:
1) the light-weight mirror image cache protocol based on the serial link is realized;
2) the realization of the protocol has the advantages of high bandwidth, small resource occupation and low power consumption;
3) the protocol is suitable for data communication among FPGA chips of avionic products, and the application layer interface is simple and has high compatibility and universality;
4) the transmission and application receiving and transmitting of the bottom link are isolated through a dual-port RAM mechanism, so that the link failure can be normally reported, but the application layer error or breakdown cannot be caused.
Drawings
Fig. 1 is a schematic structural diagram of a full-duplex communication device based on serial link mirror image caching.
Fig. 2 is a schematic diagram of a two-channel data frame transmission.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Referring to fig. 1, the full-duplex communication device based on serial link mirror image caching in this embodiment is composed of two FPGA chips adopting a frame of a mirror image caching protocol stack, each FPGA chip includes a dual-port Random Access Memory (RAM), a transmission controller, a transmission link layer, a transmission high-speed serial interface, a reception link layer, and a reception controller, and the transmission high-speed serial interface on one FPGA chip is connected to the reception high-speed serial interface on the other FPGA chip through an inter-board PCB connection line. The data transmission process is as follows:
1. a dual-port RAM: in order to ensure a full-duplex transceiving mode, the dual-port RAM is divided into a transmitting storage area and a receiving storage area, and a transmitting status register and a receiving status register are arranged in a designated area, so that transmission between nodes does not conflict, and the full-duplex transceiving mode is realized.
The sending storage area is used for storing the data block to be sent and recording the information of the size, the block sequence number, the sending state and the like of the data block to be sent on the sending state register. The way that the master control carries the data block to be sent to the dual-port RAM is out of the description scope of the present invention.
The receiving storage area is used for storing the received data blocks and recording information such as the size, the block sequence number, the receiving state and the like of the received data blocks on the receiving state register. The main control periodically acquires the information of the receiving state register, judges whether a new data block is ready to be uploaded in the dual-port RAM or not according to the receiving state, and moves data from the dual-port RAM if the new data block is ready to be uploaded.
2. A transmission controller: the sending controller periodically acquires the information of the sending state register through a preset refreshing period, judges whether a new data block is ready to be sent in the dual-port RAM or not through the sending state, if so, the sending state register acquires the information required by the transmission process such as the size of the data block, the block sequence number and the like, reads the data block to be sent from the dual-port RAM, marks the block sequence number on the data block, and then forms a data frame to be sent to a sending link layer.
3. And the data frame is transmitted to the sending high-speed serial interface through the sending link layer and then transmitted to the receiving high-speed serial interface on the other FPGA chip, so that the sending process is completed. The data frame entering the receiving high-speed serial interface is sent to the receiving controller after passing through the receiving link layer.
4. A receiving controller: the receiving controller takes out the data block from the received data frame and writes the data block into the dual-port RAM, and marks the information such as the size, the block sequence number, the receiving state and the like of the related data block in the receiving state register.
The above steps provide the basic steps of serial data communication between two FPGAs.
Further, in order to ensure the connection state of the links on the two FPGA chips, a handshake mechanism is arranged between the two FPGA chips. The handshake mechanism is: firstly, a sending controller on one FPGA chip which is powered on and started continuously sends a handshake Request (REQ) signal; after the other FPGA is electrified, the receiving controller receives a handshake request signal, and the sending controller sends a handshake response (ACK) signal; after a receiving controller of an FPGA chip which is powered on firstly receives a handshake response (ACK) signal, a sending controller sends a signal responding to receiving (ACK _ GOT), and the sending controller enters a synchronous state and sends a synchronous Signal (SYN); and after receiving the response receiving (ACK _ GOT), the receiving controller of the FPGA chip which is powered up later also enters a synchronization state, and the sending controller sends a synchronization Signal (SYN).
In order to realize link flow control, the number of credits is negotiated between the two FPGA chips in advance, each time a sending controller on the FPGA chip serving as a data sending party sends a data frame, the sending controller consumes one credit, and after a receiving controller on the FPGA chip of a data receiving party receives the data frame, the sending controller sends a receiving response message (such as data like BCB5BCB 5). And recovering a credit amount every time a receiving controller on the FPGA chip of the data sender receives a receiving response message. Once the credit is exhausted, the sending controller stops sending the data frame and waits for the credit to recover; and meanwhile, the receiving controller counts time, if the data frame is not received after the timing is over, the link is required to be reset when the link fails, and the sending controller sends a reset command to another FPGA chip to reset the link.
In order to ensure the transmission quality and reduce the error probability, if the data block transmitted between two FPGA chips is too large, the data block taken out from the double-port RAM is divided into a plurality of small pieces by the sending controller, and a data frame is formed and sent after a block serial number and a chip serial number are marked on each small piece. The tile sequence number represents the location of the tile in the entire data block, with the data payload length of an individual tile not exceeding 2048 bytes. And after the receiving controller receives the data frame, restoring the data block through the sequence of the chip serial numbers of each small chip, and if the sequence of the chip serial numbers is wrong, considering the whole data block as unreliable and discarding the data block integrally.
In order to enhance the security of transmission, when small-chip transmission is adopted, CRC code check may be adopted, that is, the sending controller fills the CRC code of a small chip in each data frame, the receiving controller calculates the CRC code after receiving the data frame, if the check is correct, the data is saved, and if the check is incorrect, the data frame is discarded. For higher security requirements, a high integrity check may be performed on the entire data block. The implementation mode is as follows:
the reception memory area of the dual port RAM is divided into a reception area a and a reception area B.
② a transmission channel A and a transmission channel B are arranged on the serial sending link layer and the serial receiving link layer, as shown in figure 2.
And thirdly, the receiving controller stores the data frame transmitted by the transmission channel A into the receiving area A, stores the data frame transmitted by the transmission channel B into the receiving area B, and compares the data blocks on the receiving area A and the receiving area B, thereby carrying out high integrity check on the received data frame.
In order to implement the redundancy function, a pair of differential lines needs to be arranged between chips, and as shown in fig. 2, two transmission channels are provided on the serial transmission link layer and the serial reception link layer. The data frame sent by the sending controller is transmitted in two transmission channels. After receiving the data frame, the receiving controller uses the chip sequence number to carry out redundancy check if the data frame contains the chip sequence number, otherwise uses the block sequence number to carry out redundancy check.
High integrity checks improve security at the cost of reduced transmission efficiency, so when high integrity checks are enabled, the redundancy check function is disabled by default.
The CRC and high integrity check can find the error code on the link, when the error rate exceeds the preset threshold, the receiving controller counts, when the count is full, the sending controller sends a reset command to reset the link, and error information is reported.
In order to cut off fault transmission in the whole design and enable the whole transmission process to be safer and more efficient, the RAMs are arranged in the sending controller and the receiving controller to perform fault isolation.
During the whole transmission process, various error frames, such as CRC error check, high integrity check error, redundancy check error, etc., may occur, and the receiving controller may count the number of errors according to different errors of the data frame.
The method for caching communication based on the serial link mirror image is applied to data transmission between FPGA chips with simple, efficient and high safety. The existing design mode occupies too much FPGA resources, or has low transmission efficiency and insufficient safety, and brings much trouble to designers in the actual product design. The method is simple in design, simplifies application operation links, occupies less logic resources, fully considers safety factors, and is the best fit design for the existing application scene.
It should be understood that equivalents and modifications of the technical solution and inventive concept thereof may occur to those skilled in the art, and all such modifications and alterations should fall within the scope of the appended claims.
Claims (9)
1. A full duplex communication device based on serial link mirror image cache comprises two FPGA chips, and is characterized in that each FPGA chip comprises a double-port RAM, a sending controller, a sending link layer, a sending high-speed serial interface, a receiving link layer and a receiving controller, wherein the sending high-speed serial interface on one FPGA chip is connected to the receiving high-speed serial interface on the other FPGA chip through an inter-board PCB (printed circuit board) connecting line;
the dual-port RAM is divided into a sending storage area and a receiving storage area, a sending state register and a receiving state register are arranged in a designated area, the sending storage area is used for storing a data block to be sent, and the size, the block sequence number and the sending state of the data block to be sent are recorded on the sending state register; the receiving storage area is used for storing the received data blocks and recording the size, the block sequence number and the receiving state of the received data blocks on the receiving state register;
the sending controller periodically acquires the information of the sending state register through a preset refreshing period, judges whether a new data block is ready to be sent in the dual-port RAM or not through the sending state, if so, the sending state register acquires the size and the block number of the data block, reads the data block to be sent from the dual-port RAM, marks the block number on the data block, and then forms a data frame to be sent to a sending link layer;
the data frame is transmitted to the high-speed serial interface through the transmitting link layer and then transmitted to the high-speed serial interface on the other FPGA chip, and the transmitting process is completed; the data frame entering the receiving high-speed serial interface is transmitted to a receiving controller after passing through a receiving link layer;
the receiving controller takes out the data block from the received data frame and writes the data block into the dual-port RAM, and marks the size, the block sequence number and the receiving state of the related data block in the receiving state register.
2. The full-duplex communication device based on the serial link image cache as claimed in claim 1, wherein before the data frame transmission, the sending controller on the FPGA chip which is powered on and started up is powered on to continuously send the handshake request signal; after a receiving controller on the later-powered FPGA chip receives the handshake request signal, a sending controller sends a handshake response signal; after a receiving controller of the FPGA chip which is powered on firstly receives the handshake response signal, a sending controller sends a response receiving signal, and the sending controller enters a synchronous state to send a synchronous signal; and after receiving the response receiving signal, the receiving controller of the later-powered FPGA chip also enters a synchronous state, and the sending controller sends a synchronous signal.
3. The full-duplex communication device based on the serial link mirror image cache as claimed in claim 1, wherein the number of credits is negotiated between the two FPGA chips in advance, a sending controller on the FPGA chip as a data sending party consumes one credit every time it sends one data frame, and a receiving controller restores one credit every time it receives a receiving response message; once the credit is exhausted, the sending controller stops sending the data frame and waits for the credit to recover; and meanwhile, the receiving controller performs timing, and if the data frame is not received after the timing is over, the sending controller sends a reset command to the other FPGA chip to perform link reset.
4. The full-duplex communication device based on the serial link mirror buffer as claimed in claim 1, wherein two transmission channels are disposed on the serial transmission link layer and the serial reception link layer, the data frame transmitted by the transmission controller is transmitted through the two transmission channels, and the reception controller performs the redundancy check according to the redundancy check rule after receiving the data frame.
5. The full-duplex communication device based on the serial link mirror image cache as claimed in claim 1, wherein the sending controller divides the data block taken out from the dual-port RAM into a plurality of small pieces, and each small piece is marked with a block serial number and a piece serial number to form a data frame for sending; and after the receiving controller receives the data frame, restoring the data block through the sequence of the chip serial numbers of each small chip, and if the sequence of the chip serial numbers is wrong, discarding the data block as a whole.
6. The full-duplex communication device based on the serial link mirror buffer as claimed in claim 5, wherein the sending controller fills small pieces of CRC codes in each data frame, the receiving controller calculates the CRC codes after receiving the data frame, if the check is correct, the data is saved, and if the check is incorrect, the data frame is discarded.
7. The full-duplex communication device based on the serial link image cache as claimed in claim 1, wherein the receiving storage area of the dual-port RAM is divided into a receiving area a and a receiving area B; setting a transmission channel A and a transmission channel B on a sending link layer and a receiving link layer which are connected in series; the receiving controller stores the data frame transmitted by the transmission channel A into the receiving area A, stores the data frame transmitted by the transmission channel B into the receiving area B, and compares the data blocks on the receiving area A and the receiving area B, so that the received data frame is verified in a high integrity mode.
8. The full-duplex communication device based on the serial link mirror buffer as claimed in claim 1, wherein when the bit error rate exceeds a predetermined threshold, the receiving controller performs counting, and when the counting is completed, the transmitting controller sends a reset command to perform link reset and report error information.
9. The apparatus of claim 1, wherein the receiving controller counts the number of errors according to the number of different errors in the data frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110325360.9A CN113098673B (en) | 2021-03-26 | 2021-03-26 | Full duplex communication device based on serial link mirror image cache |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110325360.9A CN113098673B (en) | 2021-03-26 | 2021-03-26 | Full duplex communication device based on serial link mirror image cache |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113098673A true CN113098673A (en) | 2021-07-09 |
| CN113098673B CN113098673B (en) | 2023-03-31 |
Family
ID=76668206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110325360.9A Active CN113098673B (en) | 2021-03-26 | 2021-03-26 | Full duplex communication device based on serial link mirror image cache |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113098673B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102081584A (en) * | 2009-11-30 | 2011-06-01 | 英业达股份有限公司 | Cache mirror system and method of dual-controller storage system |
| CN103902501A (en) * | 2014-04-02 | 2014-07-02 | 浙江大学 | FPGA (field programmable gate array) development board based detection method for optical interconnection network topology structural performance among boards |
| CN104025069A (en) * | 2011-12-15 | 2014-09-03 | 马维尔国际贸易有限公司 | Serial interface for fpga prototyping |
| US20140301187A1 (en) * | 2013-04-09 | 2014-10-09 | International Business Machines Corporation | Credit-based link level flow control and credit exchange using dcbx |
| CN105515926A (en) * | 2015-11-25 | 2016-04-20 | 中国电子科技集团公司第二十八研究所 | FPGA-based binary synchronization communication protocol controller |
| CN110311697A (en) * | 2019-06-24 | 2019-10-08 | 中国航空无线电电子研究所 | Remote data concentrator |
-
2021
- 2021-03-26 CN CN202110325360.9A patent/CN113098673B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102081584A (en) * | 2009-11-30 | 2011-06-01 | 英业达股份有限公司 | Cache mirror system and method of dual-controller storage system |
| CN104025069A (en) * | 2011-12-15 | 2014-09-03 | 马维尔国际贸易有限公司 | Serial interface for fpga prototyping |
| US20140301187A1 (en) * | 2013-04-09 | 2014-10-09 | International Business Machines Corporation | Credit-based link level flow control and credit exchange using dcbx |
| CN103902501A (en) * | 2014-04-02 | 2014-07-02 | 浙江大学 | FPGA (field programmable gate array) development board based detection method for optical interconnection network topology structural performance among boards |
| CN105515926A (en) * | 2015-11-25 | 2016-04-20 | 中国电子科技集团公司第二十八研究所 | FPGA-based binary synchronization communication protocol controller |
| CN110311697A (en) * | 2019-06-24 | 2019-10-08 | 中国航空无线电电子研究所 | Remote data concentrator |
Non-Patent Citations (4)
| Title |
|---|
| GAO ZHEN-BIN等: "《FPGA implementation of a multi-channel HDLC protocol transceiver》", 《IEEE》 * |
| 于戈等: "《双口RAM在航天伺服系统中的应用》", 《导航定位与授时》 * |
| 喻少林等: "《基于FPGA的飞控计算机多路串行通信设计》", 《计算机工程》 * |
| 王剑博等: "基于FPGA的智能串行通信板卡的设计与实现", 《现代电子技术》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113098673B (en) | 2023-03-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2887596B1 (en) | Network device and information transmission method | |
| US9455821B2 (en) | Method, system, and apparatus for dynamically adjusting link | |
| EP0525985B1 (en) | High speed duplex data link interface | |
| US4368512A (en) | Advanced data link controller having a plurality of multi-bit status registers | |
| JP4560213B2 (en) | Multiple reception confirmation management system in data network | |
| CN103051414B (en) | A kind of serial communication error correction and system | |
| US20060153238A1 (en) | Transfer of control data between network components | |
| EP0333225A2 (en) | Packet communication exchange including dummy packet transmission | |
| JPH02228855A (en) | Data communication system and data communication method | |
| US8660125B2 (en) | Node device, integrated circuit and control method in ring transmission system | |
| CN103957155A (en) | Message transmission method and device and interconnection interface | |
| CN101051957B (en) | Dynamically regulating method and device for link state and bundled link state | |
| CN103885910B (en) | The method that many equipment carry out IIC communications under holotype | |
| CN100474823C (en) | A method for transferring connection state of Ethernet port | |
| CN113098673B (en) | Full duplex communication device based on serial link mirror image cache | |
| CN101304296B (en) | Network apparatus and transmission method thereof | |
| US20230171024A1 (en) | Bit Block Sending Method and Apparatus | |
| US20230239180A1 (en) | Transmitter and receiver module, communication system for exchanging ethernet frames on a single m-lvds line | |
| CN101626320A (en) | Method and device for detecting loopback of channel | |
| EP3319249A1 (en) | Transmission checking method, node, system and computer storage medium | |
| CN101193093B (en) | Automatic recovery method and device and using system for bidirectional serial communication disconnection | |
| US6912210B1 (en) | Data communication system and communication device used | |
| US8576704B2 (en) | Communication system, communication device, integrated circuit, and communication method | |
| Fengfeng et al. | A serial physical layer design in RapidIO | |
| US9451338B2 (en) | Line card with network processing device and data pump device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |