CN113098512B - High-speed high-precision impedance data acquisition system based on FFT (fast Fourier transform) and CORDIC (coordinated rotation digital computer) algorithm - Google Patents
High-speed high-precision impedance data acquisition system based on FFT (fast Fourier transform) and CORDIC (coordinated rotation digital computer) algorithm Download PDFInfo
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Abstract
The invention discloses a high-speed high-precision impedance data acquisition system based on FFT and CORDIC algorithms, which belongs to the field of electrical impedance imaging and comprises the following components: the FPGA controls the DAC to generate a sine excitation signal, the sine excitation signal is input into the analog switch array after passing through the constant current source, the excitation current is injected into the EIT sensor under the control of the FPGA, the sine excitation signal is sent into an instrument amplifier, a band-pass filter and a fixed gain amplifier through the analog switch array to obtain an analog signal, and the analog signal is simultaneously sent into the pre-sampling ADC and the four high-precision ADCs; and the signal after passing through the pre-sampling ADC is fed back to an amplifier for a controller to perform gain adjustment so as to complete dynamic gain tracking. Then, the FPGA generates four control clock signals to drive the high-precision ADC to perform parallel acquisition; finally, respectively correcting gain mismatch errors and time phase mismatch errors in the four groups of parallel sampled data by using a broadband mode correction algorithm or a narrowband mode correction algorithm to complete amplitude demodulation and inversion imaging; the invention meets the requirements of the biomedical field on the signal-to-noise ratio and the sampling rate of the electrical impedance imaging system.
Description
Technical Field
The invention belongs to the field of electrical impedance imaging, relates to application of a parallel sampling technology in an electrical impedance imaging system, and particularly relates to a high-speed high-precision impedance data acquisition system based on Fast Fourier Transform (FFT) and Coordinate Rotation Digital Computer (CORDIC) algorithm.
Background
Electrical Impedance Tomography (EIT) is a technique for reconstructing the distribution of electrical conductivity in an imaging region by measuring the voltage value of the boundary of the imaging region, and in an EIT system, the number of unknown quantities is usually much larger than the number of measured quantities, which causes the EIT imaging to be pathological.
However, a lower signal-to-noise ratio can lead to the presence of artifacts in the EIT imaging images, which in turn can interfere with the measurements of the instrument. With the increasing application of the electrical impedance imaging technology in the fields of biomedicine and multiphase flow measurement, the biomedical field now requires the observation of the electrical characteristics of biological tissues in a higher frequency band range, which requires the electrical impedance imaging system to increase the bandwidth of the system as much as possible on the premise of ensuring the signal-to-noise ratio, and further requires the increase of the sampling rate of the system.
The parallel sampling technology is a technology capable of effectively improving the sampling rate of the system, and the parallel sampling technology is combined with the electrical impedance imaging technology, so that the electrical impedance imaging system can meet the requirements of biomedicine and multiphase flow fields on bandwidth and signal to noise ratio.
Disclosure of Invention
Aiming at the problems, the invention provides a high-speed high-precision impedance data acquisition system based on FFT and CORDIC algorithms, and the system simultaneously meets the requirements of high sampling rate and high system signal-to-noise ratio.
The high-speed high-precision impedance data acquisition system comprises: the device comprises an EIT sensor, an analog switch array, an amplifier for the instrument, a band-pass filter, a fixed gain amplifier, an 8-bit pre-sampling ADC, an FPGA, four 24-bit high-precision ADCs, a DAC and a constant current source.
The FPGA is simultaneously connected with the DAC, the instrument amplifier, the analog switch array, the 8-bit pre-sampling ADC and the four 24-bit high-precision ADCs;
the DAC is connected with an analog switch array through a constant current source, the analog switch array is connected with the EIT sensor and the instrument amplifier, and the instrument amplifier is connected with an 8-bit pre-sampling ADC and four 24-bit high-precision ADCs simultaneously after passing through a band-pass filter and a fixed gain amplifier;
the FPGA internally comprises a clock generation module, a data splicing module, an FFT (fast Fourier transform), CORDIC (coordinate rotation digital computer) orthogonal data generation module, a gain error + phase error calibration module, an FIR (finite impulse response) low-pass filter and an amplitude demodulation module; meanwhile, the FPGA is externally connected with an ARM.
The FFT, the gain error + phase error calibration module and the CORDIC orthogonal data generation module adopt a broadband mode correction algorithm; the FIR low-pass filter adopts a narrow-band mode correction algorithm.
The data splicing module is simultaneously connected with the FFT and the FIR low-pass filter, the FFT is connected with the gain error and phase error calibration module, the gain error and phase error calibration module is externally connected with the CORDIC orthogonal data generation module, and the calibrated signal is transmitted to the amplitude demodulation module and simultaneously fed back to the FIR low-pass filter.
The specific working process of the high-speed high-precision impedance data acquisition system is as follows:
firstly, FPGA controls DAC to generate frequency f in Of the sinusoidal excitation signal V in After passing through the constant current source, the excitation current I with the same frequency is generated in Inputting the current I into an analog switch array, and controlling the analog switch array by the FPGA to excite the current I in a mode of adjacent excitation and adjacent measurement in Injecting an EIT sensor; and the voltage between adjacent electrodes of the EIT sensor is sent to an amplifier for the instrument, a band-pass filter and a fixed gain amplifier through an analog switch array to obtain an analog signal, and is simultaneously sent to an 8-bit pre-sampling ADC and four 24-bit high-precision ADCs.
Then, the FPGA controls the 8-bit pre-sampling ADC to pre-sample the analog signal to obtain an amplitude range of the analog signal; and the amplifier for the feedback controller adjusts the gain to complete the dynamic gain tracking. After the gain adjustment is finished, the FPGA respectively generates ADC1_ clk, ADC2_ clk, ADC3_ clk and ADC4_ clk signals for controlling the clock and is used for driving the respective 24-bit high-precision ADCs, parallel acquisition is carried out on the analog signals in an alternative sampling mode, four groups of corresponding sampling data are obtained, and parallel sampling is finished.
And finally, the FPGA respectively corrects the gain mismatch errors and the time phase mismatch errors of the four groups of sampling data by using a broadband mode correction algorithm or a narrowband mode correction algorithm, the corrected data are sent to an amplitude demodulation module to complete amplitude demodulation, and the demodulated data are sent to an ARM to perform inversion imaging.
Compared with the prior art, the invention has the following advantages:
(1) A high-speed and high-precision impedance data acquisition system based on FFT and CORDIC algorithm provides a dynamic gain tracking technology and a parallel sampling technology, so that the invention can give consideration to the requirements of the biomedical field on the signal-to-noise ratio and the sampling rate (bandwidth) of an electrical impedance imaging system.
(2) A high-speed and high-precision impedance data acquisition system based on FFT and CORDIC algorithms provides a parallel sampling mismatch error broadband correction algorithm and a narrow-band correction algorithm, and different working modes can be selected according to actual working conditions to achieve balance of performance and resources.
Drawings
FIG. 1 is a block diagram of a high-speed high-precision impedance data acquisition system based on FFT and CORDIC algorithms according to the present invention;
FIG. 2 is a timing diagram of the FPGA controlling four 24-bit high-precision ADCs to acquire analog signals in parallel;
FIG. 3 is a partial timing diagram of the dynamic gain tracking of the present invention;
FIG. 4 is a schematic diagram of the internal structure of the FPGA of the present invention;
FIG. 5 is a schematic diagram of a micro-scale static electrical impedance imaging sensor based on the PCB + resin outer cavity wall according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a micro-scale dynamic electrical impedance imaging sensor based on the PCB + resin outer cavity wall according to an embodiment of the invention.
1-an EIT sensor; 2-an analog switch array; 3-an instrument amplifier; 4-band pass filter; 5-a fixed gain amplifier; 6-8 bit pre-sampling ADC;7-FPGA;8-24 bit high precision ADC;9-DAC; 10-a constant current source; 11-narrow band mode correction algorithm; 12-wideband mode correction algorithm; 13-an amplitude demodulation module; 14-ARM; 15-resin outer chamber wall; 16-8 electrode/16 electrode PCB; 17-sensor center area; 18-a static electrical impedance imaging sensor; 19-electrode area;
71-a clock generation module; 72-a data stitching module; 73-FFT; 74-gain error + phase error calibration module; 75-CORDIC quadrature data generation module; 76-FIR low pass filter; 77-amplitude demodulation module.
Detailed Description
The present invention will be described in further detail and with reference to the accompanying drawings so that those skilled in the art can understand and practice the invention.
In the prior art, a parallel sampling technology is a technology which can effectively improve the sampling rate of a system; the combination of the parallel sampling technology and the electrical impedance imaging technology enables the electrical impedance imaging system to meet the requirements of the biomedical and multiphase flow fields on bandwidth and signal to noise ratio.
The invention provides a high-speed high-precision impedance data acquisition system based on FFT and CORDIC algorithms, which comprises an EIT sensor 1, an analog switch array 2, an instrument amplifier 3, a band-pass filter 4, a fixed gain amplifier 5, an 8-bit pre-sampling ADC6, an FPGA7, four 24-bit high-precision ADCs 8, a DAC9 and a constant current source 10, wherein the EIT sensor 1 is connected with the analog switch array 2 through a power supply line and the constant current source 10 is connected with the fixed gain amplifier 5 through the power supply line.
The FPGA7 is simultaneously connected with the DAC9, the instrument amplifier 3, the analog switch array 2, the 8-bit pre-sampling ADC6 and the four 24-bit high-precision ADCs 8;
the DAC9 is connected with the analog switch array 2 through a constant current source 10, the analog switch array 2 is connected with the EIT sensor 1 and the instrument amplifier 3, and the instrument amplifier 3 is connected with the 8-bit pre-sampling ADC6 and the four 24-bit high-precision ADCs 8 after passing through the band-pass filter 4 and the fixed gain amplifier 5;
as shown in fig. 4, the FPGA7 internally includes a clock generation module 71, a data splicing module 72, an fft73, a cordic quadrature data generation module 75, a gain error + phase error calibration module 74, an fir low-pass filter 76, and an amplitude demodulation module 77; meanwhile, the FPGA7 is externally connected with an ARM14.
Wherein, the FFT73, the gain error + phase error calibration module 74 and the CORDIC orthogonal data generation module 75 employ a wideband mode correction algorithm; the FIR low pass filter 76 employs a narrow band mode correction algorithm.
The data splicing module 72 is connected to the FFT73 and the FIR low pass filter 76 at the same time, the FFT73 is connected to the gain error + phase error calibration module 74, and the gain error + phase error calibration module 74 is externally connected to the CORDIC quadrature data generation module 75, and transmits the calibrated signal to the amplitude demodulation module 77 and feeds back the calibrated signal to the FIR low pass filter 76.
The electrical impedance imaging method based on parallel sampling and dynamic gain tracking comprises the following specific steps:
firstly, FPGA controls DAC to generate frequency f in Of the sinusoidal excitation signal V in After passing through the constant current source, the excitation current I with the same frequency is generated in Inputting an analog switch array, the FPGA controlling the analog switch array to excite adjacent measurementBy exciting a current I in Injecting an EIT sensor;
and then, the voltage between adjacent electrodes of the EIT sensor is sent into an amplifier for the instrument through an analog switch array, the amplified voltage signal is sent into a band-pass filter to filter out direct-current offset, and the obtained analog signal is sent into an 8-bit pre-sampling ADC and four 24-bit high-precision ADCs simultaneously after passing through a fixed gain amplifier.
The FPGA controls the 8-bit pre-sampling ADC to pre-sample the analog signal to obtain pre-sampling data, and the amplitude range of the analog signal is estimated by calculating the peak-to-peak value of the pre-sampling data.
The FPGA feeds back the amplitude range of the analog signal to the instrument amplifier, when the estimated amplitude of the analog signal is smaller, the instrument amplifier is controlled to amplify the gain, otherwise, when the estimated amplitude of the analog signal is larger, the gain is properly reduced to prevent saturation distortion; and adjusting the gain to obtain the optimal signal-to-noise ratio to complete the dynamic gain tracking.
The dynamic gain tracking specifically comprises: as shown in the timing chart of FIG. 3, the FPGA generates an EIT _ state _ ctr signal to start an excitation measurement period, and a constant current source adds an excitation current I to the ith and I +1 th electrodes of the EIT sensor through an analog switch array in the period in Meanwhile, the analog switch array sends voltage signals of the m-th and m + 1-th electrodes of the EIT sensor into an amplifier for an instrument to be measured.
The following timing relationship is required in this process: first wait for T s Second, the switch switching is stable;
after the switch is switched stably, voltage signals of the m-th electrode and the m + 1-th electrode sequentially pass through an instrument amplifier for preliminary amplification, and due to the existence of direct current bias in the signals, the gain of a first-stage amplifier is generally not too large; filtering out direct current offset and high-frequency noise by a band-pass filter, amplifying the signal with the direct current offset filtered out by a fixed gain amplifier, and allowing the signal to enter an 8-bit pre-sampling ADC (analog to digital converter), wherein the pre-sampling time of the 8-bit pre-sampling ADC is T pre Acquiring amplitude information of the analog signal;
then the FPGA feeds the amplitude information back to the instrument amplifier for gain againAdjusting to obtain optimal gain, which takes T time G 。
Using T after gain adjustment is completed d And carrying out amplitude demodulation in time to obtain amplitude information.
And then, after the gain adjustment is finished, the clock generation module of the FPGA respectively generates control clock signals: the ADC1_ clk, the ADC2_ clk, the ADC3_ clk and the ADC4_ clk are used for driving the 24-bit high-precision ADCs corresponding to each other, and the analog signals are collected in parallel in an alternating sampling mode to obtain four groups of corresponding sampling data.
The method specifically comprises the following steps:
as shown in fig. 2, firstly, the FPGA generates a system clock clk with a period of T, the clock generation module controls the periods of the four clocks ADC1_ clk, ADC2_ clk, ADC3_ clk and ADC4_ clk to be 4T, the duty ratio is 1:3, and the theoretical phase deviations of the four control clocks are sequentially set to pi/2; the sampling rate of the monolithic 24-bit high-precision ADC is
The period of the DATA clock DATA _ clk is the same as that of the system clock clk, and the DATA clock DATA _ clk has a delay of Δ T (Δ T < T) compared to the system clock clk. The DATA clock DATA _ clk alternately receives the DATA from the 4-chip 24-bit high-precision ADC at the rising edge thereof, and the sampling rate of the entire system is f s ＝1/T。
Finally, the FPGA utilizes a broadband mode correction algorithm or a narrowband mode correction algorithm according to the actual use condition to correct the gain mismatch error and the time phase mismatch error in the parallel sampling circuit, the corrected data is sent to an amplitude demodulation module,
the amplitude information of the acquired signal is demodulated by calculating the mean value, and the demodulated data is sent into an ARM (Advanced RISC Machines) to carry out inversion imaging by using algorithms such as LandWeber and the like.
The gain mismatch error is: the analog signals enter errors generated by each ADC in four 24-bit high-precision ADC channels;
the temporal phase mismatch error is: the deviation between the actual phase deviation of the four control clocks and the theoretically set pi/2.
For a four-channel parallel sampling system, the narrow-band operating mode correction algorithm comprises the following steps:
firstly, when the frequency of the input single-point frequency signal to be measured is f in And the system sampling rate is f s And satisfy
Noise spectrum omega caused by time phase error and gain error n The following relationship will be satisfied:
wherein, ω is in ＝2πf in ，ω S ＝2πf in ；ω s For the system sampling rate f s A frequency domain representation of (a); omega in Is a frequency domain expression of the input single-point frequency signal to be measured; k is the peak spectral point position generated by the input signal;
then, calculating the position of a noise spectrum point generated by a mismatch error by using a peak spectrum point position k and a sampling point generated by an input signal;
the calculation formula is as follows:
n is the number of sampling points; k is a radical of 2 、k 3 Respectively representing the positions of the mismatch error generating noise spectrums;
finally, the four groups of sampled data are combined into a data vector x [ n ]]After FFT conversion and low-pass filtering, the noise spectrum omega is eliminated n Obtaining the sampled data
The calculation formula is as follows:
* Represents a convolution operation, N =1 … … N; h is 1 [n]For the coefficients of the low-pass filter, the following constraints are satisfied:
wherein s is f Is a low-pass filter h 1 [n]Stop band cut-off frequency of(s) a Is the stopband attenuation.
Correction of wideband mode correction algorithm, frequency of input signal in wideband mode to obtain more accurate amplitude demodulation value
The method comprises the following specific steps:
vector x [ n ] synthesized by four groups of parallel sampling data in step one]Performing FFT conversion, and calculating to obtain the peak frequency spectrum point position k of the input signal 1 ；
Step two, utilizing the position k of the peak frequency spectrum point of the input signal 1 Calculating the position k of the noise point generated by the mismatch error 2 And k 3 ：
Step three, according to the position k of the noise point 2 And k 3 Estimating noise frequency of mismatch error
And
fourthly, according to the noise frequency by using a CORDIC algorithm
And
generate 3 sets of orthonormal sequences:
the method for generating the orthogonal sequence is not limited to the CORDIC algorithm, and the method adopts the CORDIC algorithm, avoids using a memory when generating the orthogonal sequence, saves the memory space and avoids the time consumption in the process of reading the memory.
The specific process is as follows:
step 401, for the current iteration, three sets of phase steps corresponding to the orthogonal sequences are generated
And
step 402, generating an initial value of the current iteration of the CORDIC algorithm:
step 403, calculating 15 intermediate variables for the current iteration:
where m represents the number of iterations for each value, up to 15.
Step 404, calculate the 16 th orthogonal sequence Q using 15 iterations i [1]And I i [1]：
Step 405, updating the initial value of the CORDIC by phase stepping:
step 406, repeating the above steps, and performing update calculation:
step five, utilizing 3 groups of standard orthogonal sequences and sampling data x [ n ]]Calculating cross-correlation to obtain cross-correlation result
The formula is as follows:
N 0 to calculate the data length of the cross-correlation operation.
Step six, obtaining phase information theta of three noise spectrums by utilizing cross-correlation results k And amplitude information A k ；
And step seven, reconstructing four-channel parallel sampling mismatch error data e [ n ] according to the amplitude and phase information obtained by calculation.
Step eight, using the collected data x [ n ] to subtract the mismatch error e [ n ] to finish the calibration of the four-channel parallel sampling data:
example (c);
FIG. 5 is a schematic diagram of a micro-scale static electrical impedance imaging sensor based on the PCB + resin outer cavity wall; the micro-scale static electrical impedance imaging sensor based on the PCB + resin outer cavity wall is composed of a resin outer cavity wall 15 and an 8 electrode/16 electrode PCB 16. The inner diameter of the resin outer chamber wall 15 is D, the outer diameter is D, and the diameter of the sensor central region 17 is D 1 Requirement d 1 < d. The pattern structure 18 of the static electrical impedance imaging sensor is FR4 plate-gold plating/gold immersion electrode-parylene coating-heparin.
FIG. 6 is a schematic diagram of a micro-scale dynamic electrical impedance imaging sensor based on PCB + resin outer cavity wall
The micro-scale dynamic electrical impedance imaging sensor based on the PCB + resin outer cavity wall is composed of two resin outer cavity walls 15 and an 8/16 electrode PCB16, wherein a sensor central area 17 of the 8/16 electrode PCB16 is hollowed out. The inner diameter of the outer cavity wall of the resin is D, the outer diameter of the outer cavity wall of the resin is D, and the diameter of the hollow processing area is D 1 ，d 1 And (= d). Electrode area cross-section 19 shows a cross-section of an electrode area with an electrode width w and a height h. The coating structure 18 of the static electrical impedance imaging sensor is: FR4 plate + gold plating/gold immersion electrode-parylene coating-heparin.
The invention is based on the micro-scale electrical impedance imaging sensing of the PCB + the resin outer cavity wall, and uses the PCB to match the resin outer cavity wall to complete the design of the static and dynamic micro-scale electrical impedance imaging sensor, and the minimum dimension of the micro-scale electrical impedance imaging is an electrode with the diameter of 100 micrometers/8.
Claims (6)
1. A high-speed high-precision impedance data acquisition system based on FFT and CORDIC algorithm is characterized by comprising: the device comprises an EIT sensor, an analog switch array, an instrument amplifier, a band-pass filter, a fixed gain amplifier, a pre-sampling ADC, an FPGA, four high-precision ADCs, a DAC and a constant current source;
the FPGA is simultaneously connected with the DAC, the instrument amplifier, the analog switch array, the pre-sampling ADC and the four high-precision ADCs;
the DAC is connected with an analog switch array through a constant current source, the analog switch array is connected with the EIT sensor and the instrument amplifier, and the instrument amplifier is connected with the pre-sampling ADC and the four high-precision ADCs simultaneously after passing through a band-pass filter and a fixed gain amplifier;
the FPGA internally comprises a clock generation module, a data splicing module, an FFT (fast Fourier transform), a CORDIC (coordinate rotation digital computer) orthogonal data generation module, a gain error + phase error calibration module, an FIR (finite impulse response) low-pass filter and an amplitude demodulation module; meanwhile, the FPGA is externally connected with an ARM;
the data splicing module is simultaneously connected with the FFT and the FIR low-pass filter, the FFT is connected with the gain error and phase error calibration module, the gain error and phase error calibration module is externally connected with the CORDIC orthogonal data generation module, and the calibrated signal is transmitted to the amplitude demodulation module and simultaneously fed back to the FIR low-pass filter.
2. The FFT and CORDIC algorithm-based high-speed and high-precision impedance data acquisition system of claim 1, wherein the pre-sampling ADC is 8 bits and the high-precision ADC is 24 bits.
3. The high-speed and high-precision impedance data acquisition system based on the FFT and CORDIC algorithm of claim 1, wherein the FFT, gain error + phase error calibration module and CORDIC quadrature data generation module adopt a broadband mode correction algorithm; the FIR low-pass filter adopts a narrow-band mode correction algorithm.
4. The FFT and CORDIC algorithm-based high-speed and high-precision impedance data acquisition system according to claim 1, wherein the high-speed and high-precision impedance data acquisition system comprises the following specific working processes:
firstly, FPGA controls DAC to generate frequency f in Of the sinusoidal excitation signal V in After passing through the constant current source, the excitation current I with the same frequency is generated in Inputting the current I into an analog switch array, and controlling the analog switch array by the FPGA to excite the current I in a mode of adjacent excitation and adjacent measurement in Injecting an EIT sensor; the voltage between adjacent electrodes of the EIT sensor is sent to an amplifier for the instrument, a band-pass filter and a fixed gain amplifier through an analog switch array to obtain an analog signal, and the analog signal is sent to a pre-sampling ADC and four high-precision ADCs;
then, the FPGA controls the pre-sampling ADC to pre-sample the analog signal to obtain the amplitude range of the analog signal; an amplifier for the feedback control instrument adjusts the gain to complete dynamic gain tracking;
after the gain adjustment is finished, the FPGA respectively generates ADC1_ clk, ADC2_ clk, ADC3_ clk and ADC4_ clk signals for controlling a clock and is used for driving the respective corresponding high-precision ADCs, the analog signals are parallelly acquired in an alternative sampling mode, four groups of corresponding sampling data are obtained, and parallel sampling is finished;
and finally, the FPGA respectively corrects the gain mismatch errors and the time phase mismatch errors of the four groups of sampling data by using a broadband mode correction algorithm or a narrowband mode correction algorithm, the corrected data are sent to an amplitude demodulation module to complete amplitude demodulation, and the demodulated data are sent to an ARM to perform inversion imaging.
5. The FFT and CORDIC algorithm-based high-speed and high-precision impedance data acquisition system of claim 3, wherein the narrowband mode correction algorithm comprises the following steps:
firstly, when the frequency of the input single-point frequency signal to be measured is f in And the system sampling rate is f s And satisfy
Noise spectrum omega caused by time phase error and gain error n The following relationship will be satisfied:
wherein, ω is in ＝2πf in ，ω S ＝2πf in ；ω s For the system sampling rate f s A frequency domain representation of (a); omega in Is a frequency domain expression of the input single-point frequency signal to be measured; k is the peak spectral point position generated by the input signal;
then, calculating the position of a noise spectrum point generated by mismatch error by using a peak spectrum point position k and a sampling point generated by an input signal;
the calculation formula is as follows:
n is the number of sampling points; k is a radical of formula 2 、k 3 Respectively representing the positions of the mismatch error generated noise spectrums;
finally, the four groups of sampled data are combined into a data vector x [ n ]]After FFT conversion and low-pass filtering, the noise spectrum omega is eliminated n Obtaining the sampled data
The calculation formula is as follows:
* Represents a convolution operation, N =1 … … N; h is 1 [n]Are coefficients of a low pass filter.
6. The FFT and CORDIC algorithm-based high-speed and high-precision impedance data acquisition system according to claim 3, wherein the wideband mode correction algorithm comprises the following steps:
vector x [ n ] synthesized by four groups of parallel sampling data in step one]Performing FFT conversion, and calculating to obtain the peak frequency spectrum point position k of the input signal 1 ；
Step two, utilizing the position k of the peak frequency spectrum point of the input signal 1 Calculating the position k of the noise point generated by the mismatch error 2 And k 3 ：
Step three, according to the position k of the noise point 2 And k 3 Estimating noise frequency of mismatch error
And
step four, according to the noise frequency
And
generate 3 sets of orthonormal sequences:
step five, utilizing 3 groups of standard orthogonal sequences and sampling data x [ n ]]Calculating cross-correlation to obtain cross-correlation result
The formula is as follows:
N 0 calculating the data length of the cross-correlation operation;
step six, obtaining phase information theta of three noise spectrums by utilizing cross-correlation results k And amplitude information A k ；
Step seven, reconstructing four-channel parallel sampling mismatch error data e [ n ] according to the amplitude and phase information obtained by calculation;
step eight, using the collected data x [ n ] to subtract the mismatch error e [ n ] to finish the calibration of the four-channel parallel sampling data:
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