CN113098509A

CN113098509A - Sampler deviation eliminating method, sampler deviation eliminating circuit, decision feedback circuit and receiving device

Info

Publication number: CN113098509A
Application number: CN202110314629.3A
Authority: CN
Inventors: 王杰
Original assignee: Xinsiyuan Microelectronics Co ltd
Current assignee: Xinsiyuan Microelectronics Co ltd
Priority date: 2021-03-24
Filing date: 2021-03-24
Publication date: 2021-07-09
Anticipated expiration: 2041-03-24
Also published as: CN113098509B

Abstract

The invention provides a method and a circuit for eliminating sampler deviation, wherein a first input end of a sampler is set as a common-mode voltage; then, the digital control logic module continuously adjusts the digital code according to the digital code variation until the output state of the sampler changes, and the digital code is a rough deviation value; adjusting the digital code based on the rough deviation value, and determining a precise deviation value; finally, the second input end of the sampler is set to be compensation voltage corresponding to the accurate deviation value so as to eliminate the deviation of the sampler, and the first input end of the sampler is set to be a data path; the invention also provides a decision feedback circuit and a receiving device; according to the scheme, all the gears of the deviation calibration voltage do not need to be traversed, and the scanning efficiency is improved to a greater extent; the circuit structure is simple, and the integrated design of the chip is facilitated.

Description

Sampler deviation eliminating method, sampler deviation eliminating circuit, decision feedback circuit and receiving device

Technical Field

The invention relates to the field of chip design, in particular to a sampler deviation eliminating method, a sampler deviation eliminating circuit, a sampler deviation eliminating decision feedback circuit and a receiving device.

Background

The sampler circuit function in the receiving end of a high-speed SERDES (serial-parallel transceiver) is mainly used to sample and quantize the analog signal output by the analog front end, so as to obtain

logic signals

0 and 1 for subsequent circuit processing.

Due to the limitations of the semiconductor manufacturing process, the decision threshold of the actually manufactured sampler circuit may have a certain deviation from the design target, as shown in fig. 1.

In fig. 1, the Sampler (SLICER) design expected threshold is V0, and outputs 1 when the voltage of the input analog signal is higher than V0, otherwise outputs 0; however, the actual circuit may become V1 or V2 (deviating from the design expectation by Δ V1 or Δ V2), and V1 or V2 will be a small voltage region, when the voltage of the input analog signal is higher than the region, 1 is output, when the voltage falls in the region, 1 or 0 is not determined, otherwise 0 is output.

This drawback of the sampler circuit is a factor that causes the high speed SERDES reception error rate to increase, and the effect of this bias will increase as the operating speed of the high speed SERDES increases. In order to reduce the receiving error rate of the high-speed SERDES and improve the performance, it is necessary to eliminate the circuit deviation.

The prior art method of determining Sampler (SLICER) offset values is generally a forward scan plus a reverse scan followed by averaging, as shown in fig. 2. The digital control logic starts to scan upwards from the minimum voltage gear 0000 (binary number), and records the current voltage gear digital CODE CODE1 when the output of the sampler is observed to be changed from 1 to 0; then, scanning downwards from the highest voltage gear 1111 (binary number), and recording the current voltage gear digital CODE2 when the output of the sampler is observed to be changed from 0 to 1; and finally, taking the average value (CODE1+ CODE2)/2 as the deviation value of the sampler. The offset value obtained in the example of fig. 4 is (1001+1011)/2 — 1010 (binary number).

The prior art method of forward scanning, reverse scanning and averaging finally can obtain a relatively accurate sampler deviation value, but because all voltage steps must be traversed, the required scanning time is relatively long, and therefore the efficiency is relatively low. For some application scenarios that require fast startup, the performance requirements may not be met. Therefore, how to provide a sampler offset cancellation method and circuit with short scanning time and high efficiency has become one of the problems to be solved by those skilled in the art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a sampler bias elimination method, a sampler bias elimination circuit, a decision feedback circuit, and a receiving apparatus, which are used to solve the problems of long scanning time and low efficiency of the sampler bias elimination method and circuit in the prior art.

To achieve the above and other related objects, the present invention provides a sampler deviation elimination method, comprising:

s1: configuring a digital code variation, a bit upper limit value and an iteration upper limit value;

s2: setting a first input end of a sampler to be a preset voltage;

s3: setting a digital code as an initial value, and inputting a compensation voltage corresponding to the initial value from a second input end of the sampler, wherein the output of the sampler is in a first state;

s4: gradually and monotonously changing the digital code according to the digital code variation and obtaining the corresponding sampler output until the output of the sampler is changed from a first state to a second state, and finishing coarse scanning, wherein the digital code at the moment is a coarse deviation value;

s5: adjusting the digital code based on the coarse deviation value in step S4, and performing a fine scan based on the bit upper value and the iteration upper value, determining a fine deviation value:

s6: setting the second input end of the sampler as a compensation voltage corresponding to the precise deviation value in the step S5 to eliminate the deviation of the sampler;

s7: switching the sampler first input to a data path.

Optionally, in step S3, the start value is a maximum or minimum number code; when the initial value is the maximum digital code, the first state is 0, the second state is 1, the compensation voltage corresponding to the maximum digital code is the maximum deviation calibration voltage, and the digital code is gradually reduced according to the digital code variation in step S4 until the output of the sampler is 1; when the initial value is the minimum digital code, the first state is 1, the second state is 0, the compensation voltage corresponding to the minimum digital code is the minimum deviation calibration voltage, and the digital codes are gradually increased according to the digital code variation in step S4 until the output of the sampler is 0.

Optionally, step S5 includes the following sub-steps:

s501: clearing the bit counter;

s502: the sampler continuously outputs data, 1 bit of data is output each time, and 1 is added to the bit counter when 1 time of data is output until the total number of bits reaches the upper limit value of the bits;

s503: judging whether the bit numbers of 0 and 1 output by the sampler are equal or whether the iteration frequency reaches the iteration upper limit value; when the bit numbers of 0 and 1 output by the sampler are equal or the iteration number reaches the iteration upper limit value, jumping to step S6; when the bit numbers of 0 and 1 output by the sampler are not equal and the iteration times do not reach the iteration upper limit value, jumping to step S504;

s504: determining whether the bit number of the output 0 is larger than the bit number of 1, and jumping to the step S506 when the bit number of the output 0 is larger than the bit number of 1; when the bit number of 0 outputted is less than the bit number of 1, jumping to step S505;

s505: adding 1 to the digital code, judging whether the initial value is the maximum digital code or not, and jumping to the step S507 when the initial value is the maximum digital code; when the initial value is not the maximum digital code, returning to the step S501;

s506: subtracting 1 from the digital code, judging whether the initial value is the minimum digital code or not, and jumping to the step S507 when the initial value is the minimum digital code; when the initial value is not the minimum digital code, returning to the step S501;

s507: the iteration count counter is incremented by 1, and the process returns to step S501.

Optionally, in step S1, the digital code variation, the bit upper limit value and the iteration upper limit value are configured according to the manufacturing process and design requirements to meet the preset scanning speed and accuracy.

Optionally, in step S2, the preset voltage is a common mode voltage.

Optionally, the digital code variation is greater than or equal to 2.

Optionally, in steps S2 and S7, the first input of the sampler is switched by a switch to connect the preset voltage or the data path.

Optionally, the digital code is converted by a digital-to-analog conversion module, and the digital code is converted into a compensation voltage corresponding to the digital code.

The present invention also provides a sampler deviation elimination circuit, which includes: the digital control logic module, the digital-to-analog conversion module, the sampler and the switch;

the first input end of the switch is connected with a preset voltage, the second input end of the switch is connected with the data path, the control end receives a control signal, and the input signal is selected based on the control signal;

the digital control logic module is connected with the output end of the sampler and outputs a control signal and a digital code based on the output signal of the sampler;

the digital-to-analog conversion module is connected with the output end of the digital control logic module and outputs corresponding compensation voltage based on the digital code;

the first input end of the sampler is connected with the output end of the switch, the second input end of the sampler is connected with the output end of the digital-to-analog conversion module, and the deviation of the sampler is eliminated based on the compensation voltage.

Optionally, the input signal of the sampler further comprises a clock signal.

The present invention also provides a decision feedback circuit, comprising: the adder, the filtering module and the sampler deviation eliminating circuit;

the first input end of the adder receives an analog signal, the second input end of the adder is connected with the output end of the filtering module, and the signals received by the first input end and the second input end are added to output a combined analog signal;

the sampler deviation eliminating circuit is connected with the output end of the adder, the combined analog signal is used as a data path and input into the sampler deviation eliminating circuit, and a sampling signal is output based on the combined analog signal;

the filtering module is connected with the output end of the sampler deviation eliminating circuit, and is used for filtering the sampling signal and outputting a filtering signal.

Optionally, the filtering module is a finite impulse response filter.

The present invention also provides a receiving apparatus, including: the analog front end, the clock data recovery module and the decision feedback circuit;

the analog front end receives an input signal;

the decision feedback circuit is connected with the output end of the analog front end, samples the output signal of the analog front end based on a recovered clock signal and outputs a sampling signal;

the clock data recovery module is connected with the output end of the decision feedback circuit and outputs the recovered clock signal and the recovered data signal based on the sampling signal.

As described above, the sampler deviation elimination method, circuit, decision feedback circuit and receiving apparatus of the present invention have the following beneficial effects:

1 in the method for eliminating the sampler deviation, all the gears of the deviation calibration voltage do not need to be traversed, so the scheme can improve the scanning efficiency to a greater extent, and the accuracy is equivalent to that of the prior art;

2 the sampler deviation eliminating circuit, the decision feedback circuit and the receiving device of the invention have simple circuit structures and are beneficial to the integrated design of a chip.

Drawings

FIG. 1 is a schematic diagram of the offset of the output sample values of a sampler in the prior art;

FIG. 2 is a schematic diagram of a prior art scanning method for determining a bias value of a sampler;

FIG. 3 is a flow chart of the sampler bias elimination method of the present invention;

FIG. 4 is a schematic diagram of a sampler bias elimination circuit of the present invention;

FIG. 5 is a schematic diagram of a decision feedback circuit according to the present invention;

fig. 6 is a schematic diagram of a receiving device according to the present invention.

Description of the element reference numerals

1 sampler deviation eliminating circuit

11 digital control logic module

12D/A conversion module

13 sampler

14 switch

2 filtering module

3 adder

4-decision feedback circuit

5 analog front end

6 clock data recovery module

S1-S7; s501 to S507

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 3 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

As shown in fig. 3, the present embodiment provides a sampler bias eliminating method, including the following steps:

s2: setting a first input end of a sampler to be a preset voltage;

s4: changing the digital code gradually and monotonously according to the variable quantity of the digital code and obtaining the output state of a corresponding sampler until the output of the sampler is changed from a first state to a second state, and finishing coarse scanning, wherein the digital code at the moment is a coarse deviation value;

s5: adding 1 or subtracting 1 to the digital code based on the rough deviation value in the step S4, and performing accurate scanning based on the upper limit value of the bit and the upper limit value of the iteration to determine an accurate deviation value;

s6: setting the second input end of the sampler as a compensation voltage corresponding to the accurate deviation value in the step S5 to eliminate the deviation of the sampler;

s7: the sampler first input is switched to the data path.

Specifically, in step S1, the digital code variation amount, the bit upper limit value, and the iteration upper limit value are configured according to the manufacturing process and design requirements to satisfy the preset scanning speed and accuracy. As an example, the digital code variation is greater than or equal to 2, and the digital code variation may be set as required in actual use, which is not limited to this embodiment.

It should be noted that when the digital code variation is increased, the speed of the coarse scanning (corresponding to step S4) may be increased, but the deviation of the precise scanning (corresponding to step S5) may be increased due to more target gear steps being skipped, and then the iteration upper limit value may need to be increased to ensure the accuracy, but increasing the iteration upper limit value may increase the number of iterations in the precise scanning, decrease the speed of the precise scanning, and affect the efficiency; when the compensation voltage falls into the output indefinite interval of the sampler, the output of the sampler is 1 or 0, which has uncertainty, and when the bit upper limit value is increased, the probability of 1 or 0 occurring can be reflected more accurately, and the accurate deviation value can be converged more accurately, but at the same time, the speed of accurate scanning is reduced, the efficiency is affected, and therefore, the digital code variation, the bit upper limit value and the iteration upper limit value are reasonably configured according to the preset scanning speed and accuracy.

Specifically, in step S2, the preset Voltage is a Common mode Voltage (Common Voltage).

It should be noted that, when the first input terminal of the sampler is a common-mode voltage, the output of the sampler is completely determined by the second input terminal of the sampler, that is, at this time, the accurate deviation value of the decision threshold of the sampler with respect to the design target exists is determined through steps S3 to S5 without inputting external data. However, the preset voltage includes, but is not limited to, the common mode voltage listed in this embodiment, and when the preset voltage is not the common mode voltage, the deviation corresponding to the preset voltage needs to be removed to determine the precise deviation value of the decision threshold of the sampler with respect to the design target.

Specifically, in step S3, the start value is a maximum or minimum number code; when the initial value is the maximum digital code, the first state is 0, the second state is 1, the compensation voltage corresponding to the maximum digital code is the maximum deviation calibration voltage, and the digital code is gradually reduced according to the digital code variation in step S4 until the output of the sampler is 1; when the initial value is the minimum digital code, the first state is 1, the second state is 0, the compensation voltage corresponding to the minimum digital code is the minimum deviation calibration voltage, and the digital codes are gradually increased according to the digital code variation in step S4 until the output of the sampler is 0.

Specifically, step S5 includes the following sub-steps:

s501: clearing the bit counter;

In step S502, the total number of bits refers to the total number of bits of 0 and 1 output by the sampler; each pair of digital codes is adjusted once, steps S501-S503 are carried out, in step S502, the number of bits of the upper limit value quantity of the bits output by the sampler needs to be judged in step S503, the greater the set upper limit value of the bits is, the more true and false probabilities can be obtained, if the number of

output bits

0 and 1 is equal in step S503, the equal probability of occurrence of 0 and 1 is 50%, and at the moment, the digital codes are accurate deviation values; however, in practice, the probability that

bits

0 and 1 are equal is relatively small, which depends on the step size of the compensation voltage step in the circuit design and the manufacturing process. A relatively large probability occurring in the scanning process is that steps S505 and S506 are continuously repeated above and below the precision deviation value, and at this time, a convergence criterion needs to be set, otherwise, convergence may not be possible, and this convergence criterion is an iteration upper limit value, and needs to be configured according to specific requirements during design.

It should be noted that, in step S504, when the bit number of the output 0 is greater than the bit number of 1, only when the initial value is the minimum number of the codeword, the iteration count counter is incremented by 1; similarly, in step S504, when the bit number of 0 to be output is less than the 1 bit number, the iteration count counter is incremented by 1 only when the start value is the maximum number of digital codes.

Specifically, in steps S2 and S7, the first input terminal of the sampler is switched by a switch to connect the preset voltage or the data path.

More specifically, the switches are controlled by a digital control logic module.

Specifically, the Digital code is converted by a Digital-to-Analog Converter (DAC) 12, and the Digital code is converted into a compensation voltage corresponding to the Digital code.

It should be noted that the module for controlling the switch and the module for converting the digital code into the compensation voltage corresponding to the digital code include, but are not limited to, the modules listed in this embodiment, and any module capable of controlling the switch according to design requirements and the module for converting the digital code into the compensation voltage corresponding to the digital code all satisfy the invention.

The working flow of the sampler deviation eliminating method in the embodiment is as follows: connecting the first input end of the sampler with a common-mode voltage, wherein the output end of the sampler is completely determined by the compensation voltage output by the digital-to-analog conversion module 12; then, the digital control logic module continuously and monotonously adjusts the digital codes according to preset digital code variation until the output state of the sampler changes, and the digital codes at the moment are rough deviation values; based on the rough deviation value, the digital control logic module increases 1 or decreases 1 to the digital code, counts the output number of bits and the number of iterations, and when the number of iterations reaches the iteration upper limit value of a preset value or the output number of bits of 0 or 1 is equal, the digital code at the moment is the precise deviation value; and finally, the second input end of the sampler is set to be compensation voltage corresponding to the accurate deviation value, and the first input end is switched to be a data path, so that the compensation voltage is added when the first input end of the sampler is connected with the data path, and the sampler can accurately sample and quantize data signals corresponding to the data path.

It should be further noted that, because the shift of all offset calibration voltages is not traversed, the scheme can greatly improve the scanning efficiency, and the accuracy is also equivalent to the method in the background art; taking the digital code variation as 2 as an example, the bit upper limit value and the iteration upper limit value are reasonably configured, and in the worst case, the consumed time is about half of that of the background technology method, but the accuracy is equivalent to that in the background technology.

Example two

As shown in fig. 4, the present embodiment provides a sampler deviation elimination circuit 1, and the sampler deviation elimination circuit 1 can be used to implement the sampler deviation elimination method in the first embodiment, but the implemented functions of the sampler deviation elimination circuit include, but are not limited to, the sampler deviation elimination method in the first embodiment. The sampler deviation elimination circuit includes: a digital control logic module 11, a digital-to-analog conversion module 12, a sampler 13 and a switch 14;

a first input end of the switch 14 is connected with a preset voltage, a second input end of the switch is connected with a data path, a control end of the switch receives a control signal, and an input signal is selected based on the control signal;

the digital control logic module 11 is connected with the output end of the sampler 13, and outputs a control signal and a digital code based on the output signal of the sampler;

the digital-to-analog conversion module 12 is connected to the output end of the digital control logic module 11, and outputs a corresponding compensation voltage based on the digital code.

The sampler 13 has a first input end connected to the output end of the switch 14, and a second input end connected to the output end of the digital-to-analog conversion module 12, so as to eliminate the deviation of the sampler based on the compensation voltage.

In particular, the input signal of the sampler 13 also comprises a clock signal.

EXAMPLE III

As shown in fig. 5, the present embodiment provides a Decision Feedback (DFE) circuit 4, which includes an adder 3, a filter block 2 and a sampler bias elimination circuit 1 described in the second embodiment;

the adder 3 has a first input end for receiving analog signals, a second input end connected to the filter module 2, and adds the signals received by the first input end and the second input end to output combined analog signals;

the sampler deviation eliminating circuit 1 is connected with the output end of the adder 3, inputs the combined analog signal into the sampler deviation eliminating circuit as a data path, and outputs a sampling signal based on the combined analog signal;

and the filtering module 2 is connected with the output end of the sampler deviation eliminating circuit 1, and is used for filtering the sampling signal and outputting a filtering signal.

Specifically, the filtering module 2 is a Finite Impulse Response (FIR) filter.

It should be noted that the filtering module 2 includes but is not limited to those listed in this embodiment, and any filtering module composition that can meet the design requirement to filter the sampling signal meets the present invention.

It should be further noted that the decision feedback circuit of the present embodiment is used to eliminate Inter Symbol Interference (ISI).

Example four

As shown in fig. 6, the present embodiment provides a receiving apparatus including: an Analog Front End (AFE) 5, a Clock Data Recovery (CDR) block 6, and a decision feedback circuit 4 described in the third embodiment;

the analog front end 5 receives an input signal;

the decision feedback circuit 4 is connected with the output end of the analog front end 5, samples the output signal of the analog front end 5 based on a recovered clock signal, and outputs a sampling signal;

the clock data recovery module 6 is connected to the output end of the decision feedback circuit 4, and outputs the recovered clock signal and the recovered data signal based on the sampling signal.

Note that the recovered clock signal is input as a clock signal to the sampler 13 in the sampler deviation canceling circuit 1 in the decision feedback circuit 4.

In summary, the present invention provides a method for eliminating sampler bias, in which a first input terminal of a sampler is set to a common-mode voltage, and an output terminal of the sampler is completely determined by a compensation voltage output by a digital-to-analog conversion module 12; then, gradually adjusting the digital code according to a preset digital code variation until the output state of the sampler is changed, wherein the digital code at the moment is a rough deviation value; adjusting the digital code based on the rough deviation value, counting the output bit number and the iteration number, and when the iteration number reaches an iteration upper limit value or the output bit numbers of 0 or 1 are equal, taking the digital code as the precise deviation value; finally, the second input end of the sampler is set to be compensation voltage corresponding to the accurate deviation value, and the first input end of the sampler is set to be a data path, so that the compensation voltage is added when the sampler works normally, and the sampler can accurately sample and quantize data signals corresponding to the data path; the invention also provides a circuit 1 for eliminating sampler deviation, which comprises a digital control logic module 11, a digital-to-analog conversion module 12, a sampler 13 and a switch 14; the invention also provides a decision feedback circuit 4, which comprises an adder 3, a filter module 2 and the sampler deviation elimination circuit 1; the present invention also provides a receiving apparatus comprising: an analog front end 5, a clock data recovery module 6 and the decision feedback circuit 4 described above. The method for eliminating the sampler deviation does not need to traverse all the gears of the deviation calibration voltage, so the method can improve the scanning efficiency to a greater extent, and the accuracy is equivalent to that of the method in the background technology; the sampler deviation eliminating circuit, the decision feedback circuit and the receiving device have simple circuit structures and are beneficial to the integrated design of a chip. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles of the present invention and its efficacy, and are not to be construed as limiting the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A sampler deviation elimination method, characterized by comprising the steps of:

s2: setting a first input end of a sampler to be a preset voltage;

s7: switching the sampler first input to a data path.

2. The sampler bias elimination method of claim 1, wherein: in step S3, the start value is a maximum digit code or a minimum digit code; when the initial value is the maximum digital code, the first state is 0, the second state is 1, the compensation voltage corresponding to the maximum digital code is the maximum deviation calibration voltage, and the digital code is gradually reduced according to the digital code variation in step S4 until the output of the sampler is 1; when the initial value is the minimum digital code, the first state is 1, the second state is 0, the compensation voltage corresponding to the minimum digital code is the minimum deviation calibration voltage, and the digital codes are gradually increased according to the digital code variation in step S4 until the output of the sampler is 0.

3. The sampler bias elimination method of claim 2, wherein: step S5 includes the following substeps:

s501: clearing the bit counter;

4. The sampler bias elimination method of claim 1, wherein: in step S1, the digital code variation, the bit upper limit value, and the iteration upper limit value are configured according to the manufacturing process and design requirements to meet the preset scanning speed and accuracy.

5. Sampler bias cancellation method according to claim 1 or 4, characterised in that: the variation of the digital code is greater than or equal to 2.

6. The sampler bias elimination method of claim 1, wherein: in step S2, the preset voltage is a common mode voltage.

7. The sampler bias elimination method of claim 1, wherein: in steps S2 and S7, the first input of the sampler is switched by a switch to connect the preset voltage or to connect the data path.

8. The sampler bias elimination method of claim 1, wherein: the digital code is converted through a digital-to-analog conversion module, and the digital code is converted into compensation voltage corresponding to the digital code.

9. A sampler deviation elimination circuit is characterized in that: the sampler deviation elimination circuit includes: the digital control logic module, the digital-to-analog conversion module, the sampler and the switch;

the digital control logic module is connected with the output end of the sampler, and outputs the control signal and the digital code based on the output signal of the sampler;

10. The sampler bias cancellation circuit of claim 9, wherein: the input signal of the sampler further comprises a clock signal.

11. A decision feedback circuit, characterized by: the decision feedback circuit includes: a summer, a filter module and a sampler bias elimination circuit as claimed in any one of claims 9 to 10;

12. The decision feedback circuit of claim 11, wherein: the filtering module is a finite impulse response filter.

13. A receiving apparatus, characterized in that: the receiving apparatus includes: an analog front end, a clock data recovery module and a decision feedback circuit as claimed in any one of claims 11 to 12;

the analog front end receives an input signal;