CN113098435B - Superconducting high-frequency down conversion module and method, superconducting high-frequency test system and method - Google Patents
Superconducting high-frequency down conversion module and method, superconducting high-frequency test system and method Download PDFInfo
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Abstract
The invention provides a superconducting high-frequency-reducing module and a method, which are used for receiving a high-frequency clock signal, converting the high-frequency clock signal into a frequency-reducing clock sub-signal and a double clock signal, resetting based on the double clock signal, and periodically selecting and sampling a test signal so as to convert the test signal into a frequency-reducing test signal; the invention also provides a superconducting high-frequency test system and a superconducting high-frequency test method based on the linear feedback shift register; the circuit structure of the invention is relatively simple; continuous high-frequency test can be realized, and the actual working condition of the circuit to be tested is more met; the data frequency-reducing system reduces the frequency to the KHz level by frequency-reducing processing on the outputted GHz level high-frequency signal, can directly output, and simplifies the whole test system.
Description
Technical Field
The invention relates to the field of superconducting circuits, in particular to a superconducting high-frequency down conversion module and method, and a superconducting high-frequency test system and method.
Background
The superconducting SFQ (Single Flux Quantum ) circuit has great potential to be applied to the fields of high-performance calculation and the like because two performance indexes of speed and power consumption are superior to those of a semiconductor CMOS circuit. Therefore, the high-frequency performance of the test circuit is a very important step in the design of the superconducting SFQ circuit and is an important step for truly embodying the advantages of the superconducting circuit. In the superconducting circuit design, a large-scale digital circuit is built, and the high frequency design of each gate circuit (cell) to each module is used until the high frequency design of the whole system is verified through actual high frequency test, so that a stable and feasible general high frequency SFQ circuit test scheme is required.
Whereas for superconducting circuits, the typical operating frequency is about 1-40 GHz, which is much higher than the operating frequency of typical semiconductor circuits, making the typical test scheme less suitable for high frequency testing of superconducting circuits. For high-frequency testing of circuits, a basic mode is that a test sequence and a high-frequency clock are directly input through the outside, and a high-frequency test signal is directly output after the test is finished, and the mode can lead to that signal transmission between the signal and an external test system is high-frequency signal transmission. For superconducting circuits, the transmission of such high frequency signals is difficult to reach in the order of tens of GHz, while the typical amplitude of the output signal of a superconducting circuit is typically hundreds of microvolts, and is also difficult to be recognized by external devices at high frequencies. Therefore, to adopt the scheme, the processing of frequency multiplication, frequency division, multistage amplification and the like is generally needed to be carried out on the circuit signals, so that the circuit scale is large, the design difficulty is large, and the stability of a test system is lower.
Another prior art scheme is to use an Input shift register (Input SR) and an Output shift register (Output SR) to store and read Input test sequences and Output results of a circuit under test at a low frequency, and let signals pass through the circuit under test at a high frequency to realize a "pseudo" high frequency scheme: that is, the input sequence is stored in the input shift register under the drive of the low frequency Clock, then a Clock Generator (CG) is used to generate a plurality of (typically 5) high frequency clocks to drive the test sequence in the input shift register through the circuit to be tested and store the output result in the output shift register, and then the test result is read out through the output shift register under the drive of the low frequency Clock, thereby completing the whole test. The scheme realizes the test of the circuit under the high frequency on the chip, and the interconnection between the input and the output and the outside is realized under the low frequency, so that the test system is simple and stable. However, one disadvantage of this scheme is that the circuit can only be tested at a number of high frequency clocks, the number of which is limited by the size of the input shift register and the output shift register and the clock generator, so that the high frequency test of the circuit is actually only a few clock cycles and is not consistent with the actual operation of the circuit. Therefore, how to provide a superconducting high-frequency down-conversion module and method, which are simple in structure and consistent with the actual working condition of a circuit to be tested, and a superconducting high-frequency testing system and method have become one of the problems to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a superconducting high-frequency down-conversion module and method, and a superconducting high-frequency test system and method, for solving the problems of large circuit scale and inconsistent actual working conditions of the superconducting high-frequency down-conversion and test system in the prior art.
To achieve the above and other related objects, the present invention provides a superconducting high-frequency down-conversion unit including: a Non-destructive readout (Non-destructive read out, NDRO) unit and a flip-flop unit;
The trigger unit comprises two or more T triggers (T flip flop, TFF) which are sequentially connected in series, wherein the output ports of the first T trigger and the last T trigger are two, and the output ports of the rest T triggers are one; the input port of the first T trigger receives a clock signal, the first output port is connected with the reset port of the nondestructive reading unit, and the second output port is connected with the input port of the next T trigger; the first output port of the last T trigger is connected with the setting port of the non-destructive readout unit, and the second output port outputs a down-conversion clock sub-signal;
The data input port of the non-destructive readout unit receives a data signal and the data output port outputs a reduced frequency data sub-signal.
The invention also provides another superconducting high-frequency down-conversion unit, which comprises: a non-destructive readout unit and a flip-flop unit;
The trigger unit comprises a T trigger and a first shunt unit, wherein an input port of the T trigger receives a clock signal, and a first output port of the T trigger is connected with a reset port of the nondestructive reading unit; the input port of the first shunt unit is connected with the second output port of the T trigger, the first output port of the first shunt unit is connected with the setting port of the nondestructive reading unit, and the second output port outputs a down-conversion clock signal;
The data input port of the non-destructive readout unit receives a data signal and the data output port outputs a reduced frequency data sub-signal.
The invention also provides a superconducting high-frequency down conversion module, which comprises at least two superconducting high-frequency down conversion units according to any one of the above steps:
The output port of the trigger unit in the previous superconducting high-frequency down-conversion unit is connected with the input port of the trigger unit in the next superconducting high-frequency down-conversion unit, and the data output port of the non-destructive readout unit in the previous superconducting high-frequency down-conversion unit is connected with the data input port of the non-destructive readout unit in the next superconducting high-frequency down-conversion unit.
The invention also provides a superconducting high-frequency-reducing method, which is realized based on the superconducting high-frequency-reducing module and comprises the following steps of:
The first superconducting high-frequency down-conversion unit receives the high-frequency clock signal and the test signal, the down-conversion clock sub-signal output by the previous superconducting high-frequency down-conversion unit is input as the clock signal of the next superconducting high-frequency down-conversion unit, and the down-conversion data sub-signal output by the previous superconducting high-frequency down-conversion unit is input as the data signal of the next superconducting high-frequency down-conversion unit;
A trigger unit in the i superconducting high-frequency down conversion unit receives a clock signal and converts the clock signal into a down-conversion clock sub-signal and a double clock signal, wherein the period of the down-conversion clock sub-signal is 2 Mi times of the period of the clock signal, and the period of the double clock signal is 2 times of the period of the clock signal; wherein M i is the number of T triggers in the ith superconducting high-frequency down-conversion unit; the non-destructive readout unit of the i superconducting high-frequency down-conversion unit resets based on the double clock signal, periodically samples the data signal based on the down-conversion clock sub-signal, wherein the sampling period is 2 Mi, so that the data signal is converted into a down-conversion data sub-signal; wherein i is a positive integer;
the last frequency-down clock signal output by the superconducting high-frequency-down unit is output as a frequency-down clock signal of the superconducting high-frequency-down module, and the output frequency-down sub-signal is output as a frequency-down test signal of the superconducting high-frequency-down module.
The invention also provides a superconducting high-frequency test system, which comprises: the device comprises a high-frequency clock generation module, a Linear Feedback shift register (Linear Feedback SHIFT REGISTER, LFSR) and a multi-path superconducting high-frequency down conversion module;
the high-frequency clock generation module is realized based on a ring oscillator, receives a trigger pulse signal and outputs a periodic high-frequency clock signal;
The linear feedback shift register is connected with the output end of the high-frequency clock generation module, receives an initial signal to set a non-zero initial state for the linear feedback shift register, and simultaneously outputs a periodic pseudo-random sequence with a plurality of paths of preset period lengths to a circuit to be tested (Circuit Under Test, CUT);
The circuit to be tested is a multi-channel input and multi-channel output, receives the multi-channel pseudo-random sequence and outputs multi-channel test signals;
Each path of superconducting high-frequency down conversion module is respectively connected with each output port of the circuit to be tested, respectively receives test signals of each path of circuit to be tested, and outputs down conversion test signals and down conversion clock signals based on the high-frequency clock signals.
Optionally, the linear feedback shift register includes k D flip-flops, and the period of the pseudo random sequence is 2 k -1, where k is a positive integer.
Specifically, for a circuit to be tested with p paths of input and q bits per path, the number k of the D flip-flops satisfies: k is greater than or equal to p+q+1, wherein p and q are positive integers.
Optionally, the high-frequency clock generation module comprises a combiner and a first shunt unit;
The combiner receives the trigger pulse signal and the shunt clock signal and outputs a combined clock signal;
the first shunt unit is connected with the output end of the combiner, receives the combined clock signal, outputs two paths of signals identical to the combined clock signal, wherein one path of signals is used as the shunt clock signal to be output, and the other path of signals is used as the high-frequency clock signal to be output.
The invention also provides a superconducting high-frequency test method, which comprises the following steps:
receiving a trigger pulse signal and outputting a periodic high-frequency clock signal;
Receiving an initial signal, setting a non-zero initial state for the linear feedback shift register based on a low-frequency clock signal, and simultaneously outputting a periodic pseudo-random sequence with a plurality of paths of preset period lengths based on the high-frequency clock signal;
the circuit to be tested receives the multipath pseudo-random sequence and outputs multipath test signals;
receiving a high-frequency clock signal, and converting the high-frequency clock signal into a frequency-down clock signal, wherein the period of the high-frequency clock signal is 2 M times that of the high-frequency clock signal, and M is a positive integer;
Periodically sampling the test signals, wherein the sampling period is 2 M, so that each path of test signals are respectively converted into corresponding down-conversion test signals;
and comparing the multipath frequency-reducing test signals with expected output results respectively, and determining whether the circuit to be tested works normally or not.
Optionally, the generating process of the high-frequency clock signal is as follows:
Receiving a trigger pulse signal and a shunt clock signal, and outputting a combination clock signal;
Transmitting the combined clock signal to the first shunting unit;
And receiving the combined clock signal, and outputting two paths of signals which are the same as the combined clock signal, wherein one path of signals is output as the split clock signal, and the other path of signals is output as the high-frequency clock signal.
Specifically, when the linear feedback shift register is a k-stage linear feedback shift register, the period of the periodic pseudo-random sequence with the preset period length is 2 k -1, where k is a positive integer.
Optionally, when the linear feedback shift register outputs p paths, each path is a q bit pseudo random sequence, and the number of stages k of the linear feedback shift register satisfies: k is greater than or equal to p+q+1; wherein p and q are positive integers.
As described above, the superconducting high-frequency down conversion module and method, the superconducting high-frequency test system and method have the following beneficial effects:
Compared with the prior art, the invention does not need to carry out frequency multiplication, frequency division, multistage amplification and other treatments on the circuit signals, has relatively simple circuit structure and does not lead the circuit scale to be very large;
2 the input signal of the circuit to be tested does not need external input, is a pseudo-random sequence generated based on a linear feedback shift register, can realize continuous high-frequency test, and is more in line with the actual working condition of the circuit to be tested;
The data frequency-reducing system of the invention reduces the frequency to KHz level by frequency-reducing processing to the outputted GHz level high-frequency signal, and can directly output, thereby simplifying the whole test system.
Drawings
FIG. 1 is a schematic diagram of a superconducting high frequency down conversion unit of the present invention;
FIG. 2 is another schematic diagram of a superconducting high frequency down conversion unit of the present invention;
FIG. 3 is a schematic diagram of a superconducting high frequency down conversion module of the present invention;
FIG. 4 is a schematic diagram of a 1/8 superconducting high frequency down conversion unit of the present invention;
FIG. 5 is a timing diagram of a 1/8 superconducting high frequency down conversion unit of the present invention;
FIG. 6 is a schematic diagram of a superconducting high frequency test system of the present invention;
FIG. 7 is a schematic diagram of a high frequency clock generator in the superconducting high frequency test system of the present invention;
FIG. 8 is a schematic diagram of a 2bit linear feedback shift register with 3 outputs in the superconducting high frequency test system of the present invention;
FIG. 9 is a schematic diagram of an output down-conversion test signal of a 1/2 20 superconducting high-frequency down-conversion module based on a 5-stage linear feedback shift register according to the present invention;
FIG. 10 is a schematic diagram illustrating the ports of a T flip-flop;
FIG. 11 is a schematic diagram showing the state transition of the T flip-flop;
FIG. 12 is a schematic diagram illustrating the ports of a non-destructive readout unit;
FIG. 13 is a schematic diagram showing a state transition of a non-destructive readout unit;
FIG. 14 is a schematic diagram illustrating the ports of the branching unit;
FIG. 15 is a schematic diagram illustrating ports of a combiner;
FIG. 16 is a schematic diagram illustrating the ports of the D flip-flop;
Fig. 17 shows a state transition diagram of the D flip-flop.
Description of element reference numerals
1. Superconducting high-frequency down conversion module
11. Superconducting high-frequency down conversion unit
111. Non-destructive readout unit
112. Trigger unit
113. First split unit
2. High-frequency clock generation module
21. Combiner device
22. Second flow dividing unit
3. Linear feedback shift register
4. Circuit to be tested
5 DC/SFQ converter
6 SFQ/DC converter
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-17. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 1, the present embodiment provides a superconducting high-frequency down-conversion unit 11, and as shown in fig. 1, the superconducting high-frequency down-conversion unit 11 includes: a non-destructive readout unit 111 and a flip-flop unit 112;
The trigger unit 112 includes two or more T-Triggers (TFFs) sequentially connected in series, where the output ports of the first T-trigger and the last T-trigger are two, and the output ports of the remaining T-triggers are one; the input port of the first T flip-flop receives the clock signal, the first output port is connected to the reset port of the non-destructive readout unit 111, and the second output port is connected to the input port of the next T flip-flop; the first output port of the last T trigger is connected with the setting port of the non-destructive readout unit 111, and the second output port outputs a down-conversion clock sub-signal;
The data input port of the non-destructive readout unit 111 receives a data signal and the data output port outputs a frequency-reduced data sub-signal.
The present embodiment also provides another superconducting high-frequency down-conversion unit 11, the superconducting high-frequency down-conversion unit 11 including: a non-destructive readout unit 111 and a flip-flop unit 112;
the trigger unit 112 includes a T-trigger and a first shunt unit 113, where an input port of the T-trigger receives a clock signal, and a first output port is connected to a reset port of the non-destructive readout unit 111; an input port of the first shunt unit 113 is connected to a second output port of the T flip-flop, a first output port of the first shunt unit 113 is connected to a setting port of the non-destructive readout unit 111, and a second output port outputs a down-conversion clock signal;
The data input port of the non-destructive readout unit 111 receives a data signal and the data output port outputs a frequency-reduced data sub-signal.
It should be noted that, the T flip-flop is a superconducting frequency-division sequential logic gate, and each port description and state transition of the T flip-flop having two output ports are shown in fig. 10 and 11, when the AI terminal inputs a signal (single magnetic flux voltage pulse), the state of the circuit is flipped once, and when the state of the circuit is flipped from "1" state to "0" state, AO1 generates an output; conversely, when the circuit state is turned from the "0" state to the "1" state, AO2 generates an output, thereby realizing frequency division; t flip-flops having one output port, one of AO1 or AO2 is reserved.
Further, the non-destructive readout unit 111 corresponds to a switch, when the set port SI receives a high level, the non-destructive readout unit 111 is in a "1" state, which corresponds to the switch being closed, and at this time, the input signal of the data input port is directly output through the data output port of the non-destructive readout unit 111; when the reset port RI receives a high level, the non-destructive output unit non-destructive readout unit 111 is in a "0" state, which is equivalent to that the switch is turned off, and the data output port of the non-destructive output unit non-destructive readout unit 111 outputs no signal until the set port SI of the flip-flop unit 112 receives a high level signal (in this embodiment, a high level clock signal).
Further, as shown in fig. 12 and 13, the port descriptions and state transition diagrams of the non-destructive readout unit 111 are shown, and the non-destructive readout unit 111 finally realizes the control of the output signal by resetting the state of the input signal control circuit of the port RI and the set port SI. Regardless of whether the nondestructive read-out unit 111 is currently in the "0" state or the "1" state, the nondestructive read-out unit 111 is switched to the "1" state when the high level input setting port SI; when there is a high level input to the reset port RI, the non-destructive readout unit 111 transitions to the "0" state. When in the "0" state, the data input port TI has a clock signal input, and the output port TO has no signal output (i.e., outputs a logic "0"); when the circuit state is in the "1" state, the clock signal of the data input port TI is output from the data output port. Since the output signal does not affect the state of the non-destructive readout unit 111, the non-destructive readout unit 111 has the characteristic of non-destructive readout.
Further, the first splitting unit 113 is a superconducting data splitting logic gate, and each port is illustrated in fig. 14, and splits the data input at the AI terminal into data outputs AO1 and AO2, and AO1 = AO2 = AI; the cell does not include a transition of the circuit state, belonging to a non-sequential logic gate.
The working principle of the superconducting high-frequency down conversion unit 11 is as follows: every 2 Mi clock signals in the input clock signals are in a cycle, wherein M i is the number of T triggers in the superconducting high-frequency down-conversion unit 11; every 2 Mi clock signals, 2 (Mi -1) clock signals enter a reset port RI of the nondestructive read-out unit 111, the nondestructive read-out unit 111 is set to be 0, only one clock signal enters a set port SI of the nondestructive read-out unit 111, the nondestructive read-out unit 111 is set to be 1, at the moment, an input data signal can be transmitted to the next stage through the nondestructive read-out unit 111, so that the input data signal is subjected to frequency reduction, a frequency reduction data sub-signal is output, and a second output port of the last T trigger outputs a frequency reduction clock sub-signal; the frequency-down data sub-signal period is 2 Mi times the data signal period, and the frequency-down clock sub-signal period is 2 Mi times the clock signal period.
As an example, fig. 3 shows a 1/8 superconducting high-frequency down-conversion unit 11 composed of 3T flip-flops, and fig. 4 shows a timing chart of the 1/8 superconducting high-frequency down-conversion unit 11; as can be seen from fig. 4, the 8 clock signals are in a cycle, 4 clock signals in each 8 clock signals enter the reset port RI of the non-destructive readout unit 111 to set the non-destructive readout unit 111 to "0", and only 1 clock signal enters the set port SI of the non-destructive readout unit 111 to set the non-destructive readout unit 111 to "1" (the 3 rd clock signal in fig. 4 enters the set port SI, which is related to the initial setting of the T flip-flop, but because the position is not related to the position, there is no relation) so that it is ensured that only 1 clock period in each 8 clock periods the non-destructive readout unit 111 is in the "1" state, and the input data signal can be transmitted to the next-stage superconducting high-frequency down-conversion unit 11 through the non-destructive readout unit 111 (the data signal transmitted to the next-stage superconducting high-frequency down-conversion unit 11 may be the "0" signal or the "1" signal). In this way, the data selection and frequency reduction is completed, and 1 superconducting high-frequency reduction unit 11 at the next stage is selected from 8 data to be input through one unit, and the second output port of the last T trigger outputs a frequency reduction clock sub-signal, namely, the frequency reduction of the input clock signal is completed at the same time.
Example two
The present embodiment provides a superconducting high-frequency down-conversion module 1, as shown in fig. 5, the superconducting high-frequency down-conversion module 1 may include at least two superconducting high-frequency down-conversion units 11: the first superconducting high-frequency down-conversion unit 11 … is an i-th superconducting high-frequency down-conversion unit 11 …, the i is more than or equal to 1 and less than or equal to N, the i-th superconducting high-frequency down-conversion unit 11 is any one of the two superconducting high-frequency down-conversion units 11, and the compositions of the superconducting high-frequency down-conversion units 11 can be the same or different; the output port of the flip-flop unit 112 in the previous superconducting high frequency down-converting unit 11 is connected to the input port of the flip-flop unit 112 in the next superconducting high frequency down-converting unit 11, and the data output port of the non-destructive readout unit 111 in the previous superconducting high frequency down-converting unit 11 is connected to the data input port of the non-destructive readout unit 111 in the next superconducting high frequency down-converting unit 11.
The working principle of the superconducting high-frequency down conversion module 1 is as follows: the total number of the T triggers of the superconducting high-frequency down-conversion module 1 is recorded as M, wherein M=M 1+…+Mi+…+MN,Mi is the number of the T triggers in the ith superconducting high-frequency down-conversion unit 11; the superconducting high-frequency down conversion module 1 receives clock signals and data signals, every 2 M clock signals in the clock signals are in a cycle, 2 (M-1) clock signals in every 2 M clock signals enter a reset port RI of a nondestructive read-out unit 111 in an Nth superconducting high-frequency down conversion unit 11, the nondestructive read-out unit 111 in the Nth superconducting high-frequency down conversion unit 11 is set to be 0, only one clock signal enters a set port SI of the nondestructive read-out unit 111 in the Nth superconducting high-frequency down conversion unit 11, the nondestructive read-out unit 111 is set to be 1, a down frequency data signal is output, meanwhile, a second output end of a last T trigger of the Nth superconducting high-frequency down conversion unit 11 outputs the down frequency clock signal, the period of the down frequency data signal is 2 M times of the period of the data signal, and the period of the down frequency clock signal is 2 M times of the period of the clock signal.
It should be noted that, according to the first embodiment, n T flip-flops connected in series in sequence can be used to realize 1/2 n of data selection and frequency reduction, and as n increases, the connection line of the circuit is prolonged, which leads to unstable circuit operation, so if n is larger, for example 20, i.e. 1/2 20 of data frequency reduction is needed to be performed on the circuit, the data selection and frequency reduction can be realized by adopting one 1/4 superconducting high-frequency reduction unit 11 and then adopting 6 1/8 superconducting high-frequency reduction units 11 connected in series; that is, the superconducting high-frequency down-conversion module 1 is composed of a plurality of superconducting high-frequency down-conversion units 11 which are connected in series, so that the selective down-conversion of the input data signal and the clock signal with larger amplitude can be realized.
The embodiment also provides a superconducting high-frequency down-conversion method, which is realized based on the superconducting high-frequency down-conversion module 1, and comprises the following steps:
The first superconducting high-frequency down-conversion unit 11 receives the high-frequency clock signal and the test signal, the down-conversion clock sub-signal output by the previous superconducting high-frequency down-conversion unit 11 is input as the clock signal of the next superconducting high-frequency down-conversion unit 11, and the down-conversion data sub-signal output by the previous superconducting high-frequency down-conversion unit 11 is input as the data signal of the next superconducting high-frequency down-conversion unit 11;
The trigger unit 112 in the i-th superconducting high-frequency down-conversion unit 11 receives a clock signal, converts the clock signal into a down-conversion clock sub-signal and a double clock signal, wherein the period of the down-conversion clock sub-signal is 2 Mi times of the period of the clock signal, and the period of the double clock signal is 2 times of the period of the clock signal; wherein M i is the number of T triggers in the ith superconducting high-frequency down-conversion unit 11;
The data input end of the non-destructive readout unit 111 in the i-th superconducting high-frequency down-conversion unit 11 receives a data signal, resets based on a double clock signal, periodically samples the data signal based on a down-conversion clock sub-signal, and the sampling period is 2 Mi so as to convert the data signal into a down-conversion data sub-signal;
The last superconducting high-frequency down-conversion unit 11 outputs a down-conversion clock signal as a down-conversion clock signal of the superconducting high-frequency down-conversion module 1, and the down-conversion sub-signal is output as a down-conversion test signal of the superconducting high-frequency down-conversion module 1; thereby, the high-frequency clock signal is converted into a down-conversion clock signal through the superconducting high-frequency down-conversion module 1, the test signal is converted into a down-conversion test signal, the period of the down-conversion clock signal is 2 M times of the period of the high-frequency clock signal, and the period of the down-conversion test signal is 2 M times of the period of the test signal; where m=m 1+…+Mi…+MN.
Example III
The present embodiment provides a superconducting high-frequency test system, as shown in fig. 6, including: the high-frequency clock generation module 2, the linear feedback shift register 3, the superconductive high-frequency down conversion module 1 of the first embodiment; in this embodiment, the superconducting high-frequency test system is implemented based on the superconducting high-frequency down-conversion module 1 in the first embodiment, and in practical application, the method may be implemented based on any superconducting high-frequency down-conversion module 1 capable of implementing the system, and is not limited to this embodiment.
As shown in fig. 6, the superconducting high-frequency test system further includes 3 DC/SFQ (Direct Current/Single Flux Quantum, direct Current/single flux quanta) converters 5, and the trigger pulse signal, the low-frequency clock signal, and the initial signal are respectively converted by the DC/SFQ converters 5 and then input;
The superconducting high-frequency test system also comprises a plurality of SFQ/DC (Single Flux Quantum/Direct Current) converters 6 which are respectively connected with the data output end and the clock output end of each path of superconducting high-frequency down-conversion module 1 to output a plurality of paths of down-conversion test signals and down-conversion clock signals.
The high-frequency clock generation module 2 is realized based on a ring oscillator, receives a trigger pulse signal and outputs a periodic high-frequency clock signal.
Specifically, as shown in fig. 7, the high-frequency clock generation module 2 includes a combiner 21 and a second current dividing unit 22;
the combiner 21 receives the trigger pulse signal and the split clock signal, and outputs a combined clock signal;
The second branching unit 22 is connected to the combiner 21, receives the combined clock signal, and outputs two signals identical to the combined clock signal, one of which is output as a branching clock signal, and the other of which is output as a high-frequency clock signal.
The trigger pulse signal is converted into SFQ pulses by the DC/SFQ converter 5, and one SFQ pulse is output by the second shunt unit 22 every time it passes, and the high-frequency clock signal is composed of these SFQ pulses, and the period of the high-frequency clock signal is determined by the delay of the ring oscillator.
It should be further noted that the high-frequency clock generating module 2 further includes a JTL (Josephson Transmission Line ), and the combiner 21 and the second splitting unit 22 are connected by the josephson transmission line; the modules of the superconducting high-frequency test system and the units of the modules can be selectively connected through JTL (not shown in fig. 6) according to the design and layout wiring requirements, and the JTL only plays roles of connection and signal transmission.
It should be further noted that, the combiner 21 is a superconducting data intersection logic gate, also referred to as a confluence buffer (Confluence Buffer, CB) unit, and each port of the combiner 21 is illustrated in fig. 15, and functions to logically or the data input at the AI end and the data input at the BI end, so as to finally obtain the output at the ABO end; the cell does not include a transition of the circuit state, belonging to a non-sequential logic gate.
The linear feedback shift register 3 is connected with the output end of the high-frequency clock generation module 2, and receives an initial signal to set a non-zero initial state for the linear feedback shift register 3 based on a low-frequency clock signal; the linear feedback shift register 3 outputs a periodic pseudo-random sequence of a plurality of paths of preset length periods to the circuit 4 to be tested at the same time based on a high-frequency clock signal;
The circuit 4 to be tested is a multi-channel input and multi-channel output, receives the multi-channel pseudo-random sequence and outputs multi-channel test signals; each path of superconducting high-frequency down conversion module 1 is respectively connected with each output port of the circuit 4 to be tested, respectively receives each path of test signal, outputs down conversion test signals from each data output end based on the high-frequency clock signals, and outputs down conversion clock signals from each clock output end.
The number of the superconducting high-frequency down-conversion units 11 in each path of the superconducting high-frequency down-conversion module 1 and the number of the T flip-flops in the trigger units of each superconducting high-frequency down-conversion unit 11 may be the same or different, and are not limited herein.
Specifically, the linear feedback shift register 3 includes k D flip-flops (i.e., k stages of linear feedback shift registers 3), and for p inputs, each q bits of circuit 4 to be tested, k is greater than or equal to pxq+1.
Note that, the D flip-flop is a superconducting storage sequential logic gate, and each port of the D flip-flop is illustrated in fig. 16 and 17, and has functions of storing data and transferring data at the same time: when the AI end has data input (single magnetic flux voltage pulse), the TI end does not generate output, and the TO end does not generate output, and the circuit state is changed from 0 TO 1 (one single magnetic flux quantum, namely logic 1 is stored); when the AI end has no input and the TI end has no input, the TO end does not generate output, and the circuit state is still kept at 0 (logic 0 is stored); when the TI terminal generates an input, TO does not generate an output (data 0 is transmitted downwards) if the circuit state is 0, and generates an output (single magnetic flux voltage pulse, data 1 is transmitted downwards) if the circuit state is 1; however, the circuit state returns to "0" after the TI terminal generates the input no matter what the previous circuit state is.
Specifically, when the linear feedback shift register 3 includes k D flip-flops, the period of the periodic pseudo-random sequence of the preset period length is 2 k -1.
It should be noted that, for the circuit 4 to be tested, the requirement of the test sequence is that the test sequence should satisfy all different sequence combinations, for p-way input, p+1 (p-stage cannot generate all zero input sequences, so p+1-stage can generate all possible sequence components with p bits including 0) stages of linear feedback shift register 3 are used for each 1-bit circuit 4 to be tested, wherein the p-D flip-flop shunt output sequences can include all input combinations possible; for 1-way input, the circuit 4 to be tested with q bits (q-stage clock running water, that is, the input signal obtains the output result through q clock signals in the circuit 4 to be tested) is similar, all the possibilities of the q bits needed to be included are similar, and the output can be realized by using any one way of the q+1-stage linear feedback shift register 3.
Further, for a circuit 4 to be tested having p inputs, each q bits; as shown in fig. 8, taking 3 inputs, each of which is a 2-bit circuit 4 to be tested (the number of output paths and the number of input paths of the circuit 4 to be tested are the same, and the number of bits corresponding to each input and each output are the same), as an example: for a circuit 4 to be tested with outputs of A, B and C, each circuit is 2 bits, the required test sequence comprises: for a, there are 2 2 possibilities for a, 01,10,11, and for each possibility of a, B also has all four sequence correspondences, C is similar, and all sequence combinations are common (2 2)3 =64, then the linear feedback shift register 3 needs to cover 64 possible sequences, so as shown in fig. 8, a 2 x 3+1=7 stage linear feedback shift register 3 is required, for a, the output in the next two clock cycles of a is the states in D1 and D2, BC is similar, so as long as D1-D6 can cover all the sequence combinations, whereas the linear feedback shift register 3 covers all the states, e.g. when D1D2 is 00, D5D6 can cover four states from 00 to 11, D1-D4 is otherwise identical, so that in general, for p-way inputs, each of q-bit and p-bit linear feedback shift registers and their 3-D4 can cover all the sequence combinations to be tested as a test signal.
It should be further noted that, after the number of stages and the feedback loop position of the linear feedback shift register 3 are set, the output sequence is a pseudo-random sequence taking MLS (Maximum Length Sequence ) as a period, and the output sequence is obtained after the original sequence is shifted along with different initial states or different positions of the output sequence, so that the k-stage linear feedback shift register 3 is used to output the sequence between different bits as a test sequence, and each output is a different (shifted) sequence taking MLS as a period; the periodic MLS of the pseudo random sequence output by the linear feedback shift register 3 is determined by parameters such as the number of stages of the linear feedback shift register and the feedback position, and the longest sequence length MLS which is not repeated and is possibly output is not equal to 2 k -1, but the composition of the linear feedback shift register 3 corresponding to mls=2 k -1 only meets the requirement that the linear feedback shift register 3 is taken as a signal source to provide a pseudo random test sequence.
The working principle of the superconducting high-frequency test system in the embodiment is as follows: an initial state is set for the linear feedback shift register 3 under a low-frequency clock signal, the corresponding output is an original sequence, a high-frequency clock generator continuously generates a high-frequency clock signal, the linear feedback shift register 3 is driven to continuously output a plurality of paths of pseudo-random sequences, the plurality of paths of pseudo-random sequences are used as test sequences to be input into the circuit 4 to be tested, the circuit 4 to be tested outputs a plurality of paths of test signals corresponding to the test sequences based on the test sequences, the test signals are high-frequency signals, then sampling and frequency-reducing are carried out through the plurality of paths of superconducting high-frequency-reducing modules 1, and a plurality of paths of frequency-reducing test signals and a plurality of paths of frequency-reducing clock signals are output.
The following derives the output down-converted test signal based on the linear feedback shift register 3: according to the basic principle of the linear feedback shift register 3, the maximum length sequence generated by the k-level linear feedback shift register 3 is MLS= k -1, the output sequence is a periodic pseudo-random sequence taking MLS as a period, the output sequences are output through different positions of the linear feedback shift register 3, and the output sequences are the sequences after the original sequences are shifted; for the circuit 4 to be tested, the input sequence is a multi-channel pseudo-random sequence with the MLS as the period, the output is a multi-channel periodic sequence with the MLS as the period, and a complete period can be output through proper parameter selection.
As shown in fig. 9, taking a 5-stage linear feedback shift register 3 as an example, a 1/2 20 data sample down conversion system is illustrated: the 1/2 20 data sampling down-conversion system can convert a GHz level test signal into a KHz level down-conversion test signal (for example, a 40GHz frequency test signal can be converted into a 38KHz down-conversion test signal), the mls= 5 -1=31 corresponding to the 5-level linear feedback shift register 3, that is, the test signal output by the circuit to be tested 4 is a periodic sequence with 31 as a period, after the data sampling down-conversion, because 20 =31×33825+1, after a bit number is selected in a first 31bit period after the data sampling down-conversion, if the first bit is selected, a second bit is selected in a subsequent 33825 th period, and a third bit … … is selected in a 33825×30 th period; the down-conversion test signal thus output is sequentially output for one complete period, and if 62 bits are output, two complete periods are provided, thus eliminating some trouble of data processing. It should be noted that if the data of other multiples is selected to be down-converted, the remainder of the data of other multiples may not be 1, so that the output sequence is not one cycle in sequence, and at this time, but for the output sequence, a complete cycle sequence can always be output, but the sequence may be rearranged in sequence, and through a simple permutation and combination, a correct expected sequence can be obtained, and by comparison, whether the circuit 4 to be tested works normally can be determined.
Example IV
The present embodiment provides a superconducting high-frequency test method, in this embodiment, the superconducting high-frequency test method is implemented based on the superconducting high-frequency test system in the third embodiment, and in practical application, the method may be implemented based on any system capable of implementing the method, and is not limited to this embodiment. The superconducting high-frequency test method comprises the following steps:
the high-frequency clock generation module 2 receives the trigger pulse signal and outputs a periodic high-frequency clock signal;
setting a non-zero initial state for the linear feedback shift register 3 based on the initial signal and the low-frequency clock signal, wherein the linear feedback shift register 3 outputs a plurality of paths of pseudo-random sequences with preset length periods based on the high-frequency clock signal;
The circuit 4 to be tested receives the multipath pseudo-random sequence and outputs multipath test signals;
Each path of superconducting high-frequency down conversion module 1 receives the high-frequency clock signal and each path of down conversion test signal respectively, and converts the high-frequency clock signal into a down conversion clock signal, wherein the period of the down conversion clock signal is 2 M times of the period of the high-frequency clock signal, and M is the total number of T triggers in the superconducting high-frequency down conversion module 1;
Each path of superconducting high-frequency down conversion module 1 periodically samples the test signals, wherein the sampling period is 2 M, so that the multiple paths of test signals are respectively converted into corresponding down conversion test signals;
And comparing the multipath down-conversion test signals with expected output results respectively, so as to determine whether the circuit 4 to be tested works normally.
The components of each path of superconducting high-frequency down-conversion module 1 may be the same or different, and the corresponding M values may be the same or different, which is not limited herein.
Specifically, the generation process of the high-frequency clock signal is as follows:
the combiner 21 receives a trigger pulse signal and a split clock signal, and outputs a combined clock signal;
Transmitting the combined clock signal to the first splitting unit 113 via a josephson transmission line;
The second branching unit 22 receives the combined clock signal, outputs two signals identical to the combined clock signal, one of which is output as the branched clock signal and the other of which is output as the high-frequency clock signal.
Further, when the linear feedback shift register 3 is a k-stage linear feedback shift register 3, the period of the periodic pseudo-random sequence with the preset period length is 2 k -1.
Further, when the output of the linear feedback shift register 3 is p paths, and each path is a q-bit pseudo-random sequence, the number of stages k of the linear feedback shift register 3 is greater than or equal to p×q+1.
In summary, the invention provides a superconducting high-frequency down conversion module 1 and a method, which are used for down conversion treatment of a high-frequency test signal output by a circuit 4 to be tested, and can directly down-convert a GHz-level high-frequency signal to KHz after sampling down conversion for a plurality of times, and can directly output the high-frequency signal by test equipment commonly used by a superconducting SFQ circuit, thereby greatly reducing the complexity of a test system and a test process; the invention also provides a superconducting high-frequency test system and a method, wherein the system takes the linear feedback shift register 3 as a generator of a test sequence input by the circuit 4 to be tested, so that an on-chip high-frequency test system for the superconducting SFQ circuit can be realized, the system utilizes the linear feedback shift register 3 to generate a pseudo-random sequence as the test sequence, and then the output signal is directly down-converted to the KHz level output by sampling down-conversion at the output end of the circuit 4 to be tested under a high-frequency clock. Compared with the prior art, the invention does not need to carry out frequency multiplication, frequency division, multistage amplification and other treatments on the circuit signals, and the circuit structure is relatively simple; the input signal of the circuit 4 to be tested does not need external input, is based on the pseudo-random sequence generated by the linear feedback shift register 3, can realize continuous high-frequency test, and is more in line with the actual working condition of the circuit 4 to be tested; the data frequency-reducing system reduces the frequency to the KHz level by frequency-reducing processing on the outputted GHz level high-frequency signal, so that the data frequency-reducing system can directly output the data frequency-reducing signal, and the whole test system is simplified. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (12)
1. A superconducting high frequency down conversion unit, characterized in that the superconducting high frequency down conversion unit comprises: a non-destructive readout unit and a flip-flop unit;
The trigger unit comprises two or more T triggers which are sequentially connected in series, wherein the output ports of the first T trigger and the last T trigger are two, and the output ports of the rest T triggers are one; the input port of the first T trigger receives a clock signal, the first output port is connected with the reset port of the nondestructive reading unit, and the second output port is connected with the input port of the next T trigger; the first output port of the last T trigger is connected with the setting port of the non-destructive readout unit, and the second output port outputs a down-conversion clock sub-signal;
A data input port of the nondestructive read-out unit receives a data signal, and a data output port outputs a frequency-reduced data sub-signal;
When the setting port receives a high level, the non-destructive reading unit is in a1 state, and at the moment, an input signal of the data input port is directly output through the data output port of the non-destructive reading unit; when the reset port receives a high level, the non-destructive output unit and the non-destructive reading unit are in a 0 state, and at the moment, the data output port of the non-destructive output unit and the non-destructive reading unit do not output signals until the set port of the trigger unit receives a high level signal;
Every 2Mi clock signals in the input clock signals are in a cycle, wherein Mi is the number of T triggers in the superconducting high-frequency down-conversion unit; every 2Mi clock signals, 2 (Mi-1) clock signals enter a reset port of the nondestructive reading unit, the nondestructive reading unit is set to be 0, only one clock signal enters a set port of the nondestructive reading unit, the nondestructive reading unit is set to be 1, and an input data signal is transmitted to the next stage through the nondestructive reading unit, so that the input data signal is subjected to frequency reduction.
2. A superconducting high frequency down conversion unit, characterized in that: the superconducting high-frequency down conversion unit includes: a non-destructive readout unit and a flip-flop unit;
The trigger unit comprises a T trigger and a first shunt unit, wherein an input port of the T trigger receives a clock signal, and a first output port of the T trigger is connected with a reset port of the nondestructive reading unit; the input port of the first shunt unit is connected with the second output port of the T trigger, the first output port of the first shunt unit is connected with the setting port of the nondestructive reading unit, and the second output port outputs a down-conversion clock signal;
A data input port of the nondestructive read-out unit receives a data signal, and a data output port outputs a frequency-reduced data sub-signal;
When the setting port receives a high level, the non-destructive reading unit is in a1 state, and at the moment, an input signal of the data input port is directly output through the data output port of the non-destructive reading unit; when the reset port receives a high level, the non-destructive output unit and the non-destructive reading unit are in a 0 state, and at the moment, the data output port of the non-destructive output unit and the non-destructive reading unit do not output signals until the set port of the trigger unit receives a high level signal;
Every 2Mi clock signals in the input clock signals are in a cycle, wherein Mi is the number of T triggers in the superconducting high-frequency down-conversion unit; every 2Mi clock signals, 2 (Mi-1) clock signals enter a reset port of the nondestructive reading unit, the nondestructive reading unit is set to be 0, only one clock signal enters a set port of the nondestructive reading unit, the nondestructive reading unit is set to be 1, and an input data signal is transmitted to the next stage through the nondestructive reading unit, so that the input data signal is subjected to frequency reduction.
3. A superconducting high frequency down conversion module, characterized in that: the superconducting high frequency down conversion module comprises at least two superconducting high frequency down conversion units according to any one of claims 1 or 2:
The output port of the trigger unit in the previous superconducting high-frequency down-conversion unit is connected with the input port of the trigger unit in the next superconducting high-frequency down-conversion unit, and the data output port of the non-destructive readout unit in the previous superconducting high-frequency down-conversion unit is connected with the data input port of the non-destructive readout unit in the next superconducting high-frequency down-conversion unit.
4. A superconducting high-frequency down-conversion method is characterized in that: the superconducting high-frequency down-conversion method is realized based on the superconducting high-frequency down-conversion module in claim 3 and comprises the following steps:
The first superconducting high-frequency down-conversion unit receives the high-frequency clock signal and the test signal, the down-conversion clock sub-signal output by the previous superconducting high-frequency down-conversion unit is input as the clock signal of the next superconducting high-frequency down-conversion unit, and the down-conversion data sub-signal output by the previous superconducting high-frequency down-conversion unit is input as the data signal of the next superconducting high-frequency down-conversion unit;
A trigger unit in the i superconducting high-frequency down conversion unit receives a clock signal and converts the clock signal into a down-conversion clock sub-signal and a double clock signal, wherein the period of the down-conversion clock sub-signal is 2 Mi times of the period of the clock signal, and the period of the double clock signal is 2 times of the period of the clock signal; wherein M i is the number of T triggers in the ith superconducting high-frequency down-conversion unit; the non-destructive reading unit of the i superconducting high-frequency down-conversion unit resets based on the double clock signal, periodically samples the data signal based on the down-conversion clock sub-signal, and the sampling period is 2 Mi, so that the data signal is converted into a down-conversion data sub-signal; wherein i is a positive integer;
The last frequency-down clock signal output by the superconducting high-frequency-down unit is output as a frequency-down clock signal of the superconducting high-frequency-down module, and the frequency-down sub-signal is output as a frequency-down test signal of the superconducting high-frequency-down module.
5. A superconducting high frequency test system, the superconducting high frequency test system comprising: the device comprises a high-frequency clock generation module, a linear feedback shift register and a multi-path superconducting high-frequency down conversion module;
the high-frequency clock generation module is realized based on a ring oscillator, receives a trigger pulse signal and outputs a periodic high-frequency clock signal;
The linear feedback shift register is connected with the output end of the high-frequency clock generation module, receives an initial signal to set a non-zero initial state for the linear feedback shift register, and simultaneously outputs a periodic pseudo-random sequence with a plurality of paths of preset period lengths to a circuit to be tested;
The circuit to be tested is a multi-channel input and multi-channel output, receives the multi-channel pseudo-random sequence and outputs multi-channel test signals;
Each path of superconducting high-frequency down conversion module is respectively connected with each output port of the circuit to be tested, respectively receives test signals of each path of circuit to be tested, and outputs down conversion test signals and down conversion clock signals based on the high-frequency clock signals.
6. The superconducting high frequency test system according to claim 5, wherein: the linear feedback shift register comprises k D triggers, and the period of the pseudo-random sequence is 2 k -1, wherein k is a positive integer.
7. The superconducting high-frequency test system according to claim 6, wherein: for a circuit to be tested with p paths of input, each path is q bits, and the number k of the D flip-flops meets the following conditions: k is greater than or equal to p+q+1, wherein p and q are positive integers.
8. The superconducting high frequency test system according to any one of claims 5-7, wherein: the high-frequency clock generation module comprises a combiner and a first shunt unit;
The combiner receives the trigger pulse signal and the shunt clock signal and outputs a combined clock signal;
the first shunt unit is connected with the output end of the combiner, receives the combined clock signal, outputs two paths of signals identical to the combined clock signal, wherein one path of signals is used as the shunt clock signal to be output, and the other path of signals is used as the high-frequency clock signal to be output.
9. A superconducting high frequency test method, implemented based on the superconducting high frequency test system according to any one of claims 5-8, characterized in that: the superconducting high-frequency test method comprises the following steps:
receiving a trigger pulse signal and outputting a periodic high-frequency clock signal;
Receiving an initial signal, setting a non-zero initial state for the linear feedback shift register based on a low-frequency clock signal, and simultaneously outputting a periodic pseudo-random sequence with a plurality of paths of preset period lengths based on the high-frequency clock signal;
the circuit to be tested receives the multipath pseudo-random sequence and outputs multipath test signals;
receiving a high-frequency clock signal, and converting the high-frequency clock signal into a frequency-down clock signal, wherein the period of the high-frequency clock signal is 2 M times that of the high-frequency clock signal, and M is a positive integer;
periodically sampling the test signals, wherein the sampling period is 2 M, so that each path of test signals are respectively converted into corresponding down-conversion test signals;
and comparing the multipath frequency-reducing test signals with expected output results respectively, and determining whether the circuit to be tested works normally or not.
10. The superconducting high-frequency test method according to claim 9, wherein: when the high-frequency clock generation module comprises a combiner and a first shunt unit; the combiner receives the trigger pulse signal and the shunt clock signal and outputs a combined clock signal; the first shunt unit is connected with the output end of the combiner, receives the combined clock signal, outputs two paths of signals identical to the combined clock signal, wherein one path of signals is used as the shunt clock signal to be output, and the other path of signals is used as the high-frequency clock signal to be output, and the generation process of the high-frequency clock signal is as follows:
Receiving a trigger pulse signal and a shunt clock signal, and outputting a combination clock signal;
Transmitting the combined clock signal to the first shunting unit;
And receiving the combined clock signal, and outputting two paths of signals which are the same as the combined clock signal, wherein one path of signals is output as the split clock signal, and the other path of signals is output as the high-frequency clock signal.
11. The superconducting high-frequency test method according to claim 9, wherein: when the linear feedback shift register is a k-stage linear feedback shift register, the period of the periodic pseudo-random sequence with the preset period length is 2 k -1, wherein k is a positive integer.
12. The superconducting high frequency test method according to claim 11, wherein: when the linear feedback shift register outputs p paths, each path is a q bit pseudo random sequence, and the number of stages k of the linear feedback shift register meets the following conditions: k is greater than or equal to p+q+1, wherein p and q are positive integers.
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